# IEEE Transactions on Circuits and Systems I: Regular Papers

## Volume 64 Issue 5 • May 2017

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## Filter Results

Displaying Results 1 - 25 of 28

Publication Year: 2017, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I:Regular Papers publication information

Publication Year: 2017, Page(s): C2
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• ### Guest Editorial Special Section on the 2016 IEEE Latin American Symposium on Circuits and Systems (LASCAS 2016)

Publication Year: 2017, Page(s):1017 - 1018
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• ### Design and Experimental Evaluation of a Time-Interleaved ADC Calibration Algorithm for Application in High-Speed Communication Systems

Publication Year: 2017, Page(s):1019 - 1030
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In this work we investigate a new background calibration technique to compensate sampling phase errors in time-interleaved analog-to-digital-converters (TI-ADCs). Timing mismatches in TI-ADC degrade significantly the performance of ultra-high-speed digital transceivers. Unlike previous proposals, the calibration technique used here optimizes a metric directly related to the performance of the comm... View full abstract»

• ### Hardware/Software Approach to Designing Low-Power RNS-Enhanced Arithmetic Units

Publication Year: 2017, Page(s):1031 - 1039
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In this paper, we propose a new approach to use a residue number system (RNS) to design an arithmetic unit to parallelize execution of addition and multiplication. The chosen RNS is defined by a moduli set composed of one larger even modulus 2k and all remaining moduli of the type 2n - 1, selected to fit into the word size of a typical general-purpose processor, e.g., 32 or 64 b. The RN... View full abstract»

• ### Single Bit Filtering Circuit Implemented in a System for the Generation of Colored Noise

Publication Year: 2017, Page(s):1040 - 1050
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The generation of complex signal sources is important for test and validation of electronic systems. With reference to noise sources, commercial systems usually provide white noise sources, while the scientific literature only recently proposed circuits that generate programmable colored noise. This paper proposes a filtering circuit and an algorithm to design the same that produces an arbitrary c... View full abstract»

• ### Design of Efficient Multiplierless Modified Cosine-Based Comb Decimation Filters: Analysis and Implementation

Publication Year: 2017, Page(s):1051 - 1063
Cited by:  Papers (3)
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This paper presents a computationally efficient design of modified cosine-based decimation filters. One of the main contributions of this paper is the proposal of a multiplierless finite impulse response low-order linear-phase filter to increase spurious signal rejection in the so-called folding bands. The resulting filters feature reduced computational complexity compared with other recent propos... View full abstract»

• ### Implementation of Locally-Clocked XBM State Machines on FPGAs Using Synchronous CAD Tools

Publication Year: 2017, Page(s):1064 - 1074
Cited by:  Papers (1)
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Controllers based on Synchronous Finite State Machines (SFSM) are widely used in the control unit design of complex digital systems. These systems can present serious problems related to the global clock. In this context, the asynchronous paradigm shows interesting features that fit as an alternative for the design, despite of the difficulties of the application of asynchronous logic. An interesti... View full abstract»

• ### Analysis and Design of VCO-Based Phase-Domain $Sigma Delta$ Modulators

Publication Year: 2017, Page(s):1075 - 1084
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VCO-based phase-domain ΣΔ modulators employ the combination of a voltage-controlled-oscillator (VCO) and an up/down counter to replace the analog loop filter used in conventional ΣΔ modulators. Thanks to this highly digital architecture, they can be quite compact, and are expected to shrink even further with CMOS scaling. This paper describes the analysis and design of ... View full abstract»

• ### A 1-V 5-MHz Bandwidth 68.3-dB SNDR Continuous-Time Delta-Sigma Modulator With a Feedback-Assisted Quantizer

Publication Year: 2017, Page(s):1085 - 1093
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A low-power continuous-time delta-sigma modulator (CTDSM) incorporating a multi-bit feedback-assisted quantizer (FBAQ) is presented in this paper. The proposed multi-bit quantizer is placed in a negative feedback loop to reduce the signal swing at its input. As a result, the number of comparator required for signal quantization is reduced. Furthermore, the modulator is optimized for low-voltage sw... View full abstract»

• ### An Ultra-Low Power 1.7-2.7 GHz Fractional-N Sub-Sampling Digital Frequency Synthesizer and Modulator for IoT Applications in 40 nm CMOS

Publication Year: 2017, Page(s):1094 - 1105
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This paper introduces an ultra-low power 1.7-2.7-GHz fractional-N sub-sampling digital PLL (SS-DPLL) for Internet-of-Things (IoT) applications targeting compliance with Bluetooth Low Energy (BLE) and IEEE802.15.4 standards. A snapshot time-to-digital converter (TDC) acts as a digital sub-sampler featuring an increased out-of-range gain and without any assistance from the traditional counting of DC... View full abstract»

• ### A 95-dBA DR Digital Audio Class-D Amplifier Using a Calibrated Digital-to-Pulse Converter

Publication Year: 2017, Page(s):1106 - 1117
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A digital class-D amplifier (CDA) converts an audio digital stream into sound directly and power-efficiently. It first encodes the pulse-code-modulated audio input into a digital pulse-width-modulated (PWM) signal. It needs a digital-to-pulse converter (DPC) to translate this digital PWM signal into a series of analog binary pulses accurately. We report a 5-3 segmented DPC that includes both a cou... View full abstract»

• ### A Low-Power Analog Adder and Driver Using a-IGZO TFTs

Publication Year: 2017, Page(s):1118 - 1125
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This paper presents a novel low-power analog circuit, with n-type IGZO TFTs that can function as an adder operator or be designed to operate as a driver. Experiments were set to show summation of up to four signals. However, the design can easily be expanded to add higher number of signals, by appending a single TFT at the input per each additional signal. The circuit is simple, uses a single powe... View full abstract»

• ### A Generalized Combiner Synthesis Technique for Class-E Outphasing Transmitters

Publication Year: 2017, Page(s):1126 - 1139
Cited by:  Papers (1)
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In this paper, a generic combiner design technique is developed for class-E outphasing transmitters. The design procedure starts with calculation of the combiner network parameters that guarantee high efficiency switch mode operation of the PAs in each branch. Recently developed continuous class-E modes theory is then utilized to create an additional degree of freedom for calculation of the combin... View full abstract»

• ### Microwave Characteristics of an Independently Biased 3-Stack InGaP/GaAs HBT Configuration

Publication Year: 2017, Page(s):1140 - 1151
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This paper investigates various important microwave characteristics of an independently biased 3-stack InGaP/GaAs heterojunction bipolar transistor (HBT) monolithic microwave integrated circuit (MMIC) chip at both small-signal and large-signal operation. By taking the advantage of the independently biased functionality, bias condition for individual transistor can be adjusted flexibly, resulting i... View full abstract»

• ### Hardware Implementation Overhead of Switchable Matching Networks

Publication Year: 2017, Page(s):1152 - 1163
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Nowadays, more and more RF systems include switchable matching networks to decrease the impact of the environment-dependent antenna impedance on the RF front end performance. This paper reviews the theoretical lower limit on the required number of matching states to match VSWR ranges and then presents an analysis of hardware implementations to actually implement a suitable switchable matching netw... View full abstract»

• ### A High-Speed and Ultra Low-Power Subthreshold Signal Level Shifter

Publication Year: 2017, Page(s):1164 - 1172
Cited by:  Papers (1)
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In this paper, we present a novel level shifter circuit converting subthreshold signal levels to super-threshold signal levels at high-speed using ultra low-power and a small silicon area, making it well-suited for low-power applications such as wireless sensor networks and implantable medical devices. The proposed circuit introduces a new voltage level shifter topology employing a level-shifting ... View full abstract»

• ### Circuit Designs of High-Performance and Low-Power RRAM-Based Multiplexers Based on 4T(ransistor)1R(RAM) Programming Structure

Publication Year: 2017, Page(s):1173 - 1186
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Routing multiplexers based on pass-transistors or transmission gates are an essential components in many digital integrated circuits. However, whatever structure is employed, CMOS multiplexers have two major limitations: 1) their delay is linearly related to the input size; 2) their performance degrades seriously when operated in near-Vt regime. Resistive Random Access Memory (RRAM) technology bri... View full abstract»

• ### Minimizing Coefficients Wordlength for Piecewise-Polynomial Hardware Function Evaluation With Exact or Faithful Rounding

Publication Year: 2017, Page(s):1187 - 1200
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Piecewise polynomial interpolation is a well-established technique for hardware function evaluation. The paper describes a novel technique to minimize polynomial coefficients wordlength with the aim of obtaining either exact or faithful rounding at a reduced hardware cost. The standard approaches employed in literature subdivide the design of piecewise-polynomial interpolators into three steps (co... View full abstract»

• ### Rakeness-Based Design of Low-Complexity Compressed Sensing

Publication Year: 2017, Page(s):1201 - 1213
Cited by:  Papers (3)
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Compressed Sensing (CS) can be introduced in the processing chain of a sensor node as a mean to globally reduce its operating cost, while maximizing the quality of the acquired signal. We exploit CS as a simple early-digital compression stage that performs a multiplication of the signal by a matrix. The operating costs (e.g., the consumed power) of such an encoding stage depend on the number of ro... View full abstract»

• ### Fractional Hilbert Transform Sampling Method and Its Filter Bank Reconstruction

Publication Year: 2017, Page(s):1214 - 1224
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In this paper, conventional Hilbert transform sampling method is generalized to fractional Hilbert transform sampling method. First, a frequency-domain analysis method is applied to derive the fractional Hilbert transform sampling theorem of a band-limited signal. Then, an analog filter bank method is presented to recover the original continuous-time signal from the discrete-time sampled signals. ... View full abstract»

• ### A Study of Injection Locking in Dual-Band CMOS Frequency Dividers

Publication Year: 2017, Page(s):1225 - 1234
Cited by:  Papers (2)
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We present a study of dual-band injection locking frequency dividers (ILFDs), based on a nonlinear analysis. We develop a quasi-normal model of these dividers suitable for applying the method of averaging, which allowed us to derive in a simple and expressive manner the first-approximation equations for the amplitudes and phases of the locked modes, both in transient and in steady state. The phase... View full abstract»

• ### Stability of Power Control in Multiple Coexisting Wireless Networks: An $mathscr {L}_{2}$ Small-Gain Perspective

Publication Year: 2017, Page(s):1235 - 1246
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Owing to the emerging techniques such as heterogeneous network and cognitive radio that allow a large number of wireless networks to intensively and flexibly use resources of radio spectrum, the network densification and dynamic spectrum access have become two important trends of wireless networking systems, so that the spectral environments will be increasingly crowded in the near future. Under s... View full abstract»

• ### Discrete Adjoint Sensitivity Analysis of Hybrid Dynamical Systems With Switching

Publication Year: 2017, Page(s):1247 - 1259
Cited by:  Papers (1)
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Sensitivity analysis is an important tool for describing power system dynamic behavior in response to parameter variations. It is a central component in preventive and corrective control applications. The existing approaches for sensitivity calculations, namely, finite-difference and forward sensitivity analysis, require a computational effort that increases linearly with the number of sensitivity... View full abstract»

• ### Joint Symbol and Chip Synchronization for a Burst-Mode-Communication Superregenerative MSK Receiver

Publication Year: 2017, Page(s):1260 - 1269
Cited by:  Papers (1)
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In this paper we describe a superregenerative (SR) MSK receiver able to operate in a burst-mode framework where synchronization is required for each packet. The receiver is based on an SR oscillator which provides samples of the incoming instantaneous phase trajectories. We develop a simple yet effective technique to achieve joint chip and symbol synchronization within the time limits of a suitabl... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK