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# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 25 of 28

Publication Year: 2017, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I:Regular Papers publication information

Publication Year: 2017, Page(s): C2
| PDF (72 KB)
• ### Update From the Editor-in-Chief

Publication Year: 2017, Page(s):1 - 2
| PDF (648 KB) | HTML
• ### Frequency-Channelized Mismatch-Shaped Quadrature Data Converters for Carrier Aggregation in MU-MIMO LTE-A

Publication Year: 2017, Page(s):3 - 13
Cited by:  Papers (5)
| | PDF (2915 KB) | HTML

Emerging wireless standards aggregate information by selecting combinations of contiguous or non-contiguous channels, thereby enabling wider transmission bandwidths, and hence, higher data rates. Frequency-interleaved analog-to-digital conversion (FI-ADC) is an attractive emerging technique for carrier aggregation receivers because it facilitates an efficient way to dynamically vary the receiver b... View full abstract»

• ### The Effects of Inter-Symbol Interference in Dynamic Element Matching DACs

Publication Year: 2017, Page(s):14 - 23
Cited by:  Papers (4)
| | PDF (1350 KB) | HTML

Dynamic element matching (DEM) is often applied to multi-bit DACs to avoid nonlinear distortion that would otherwise result from inevitable mismatches among nominally identical circuit elements. Unfortunately, for such a DEM DAC to fully achieve this objective its constituent 1-bit DACs must be free of inter-symbol interference (ISI), i.e., the error from each 1-bit DAC must not depend on prior sa... View full abstract»

• ### A Class of 1-Bit Multi-Step Look-Ahead $\Sigma$ - $\Delta$ Modulators

Publication Year: 2017, Page(s):24 - 37
Cited by:  Papers (9)
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Digital Multi-Step Look-Ahead (MSLA) 1-bit Σ-Δ modulators are introduced. They improve upon the stability and noise shaping characteristics of conventional 1-bit Σ-Δ modulators by minimizing quantization error metrics of the current and future output samples. The mathematical model of the proposed MSLA modulators is analyzed. It is shown that the MSLA modulators are equivalent to a system of conve... View full abstract»

• ### A CMOS Pixel With Embedded ADC, Digital CDS and Gain Correction Capability for Massively Parallel Imaging Array

Publication Year: 2017, Page(s):38 - 49
Cited by:  Papers (4)
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In the paper, a CMOS pixel has been proposed for imaging arrays with massively parallel image acquisition and simultaneous compensation of dark signal nonuniformity (DSNU) as well as photoresponse nonuniformity (PRNU). In our solution the pixel contains all necessary functional blocks: a photosensor and an analog-to-digital converter (ADC) with built-in correlated double sampling (CDS) integrated ... View full abstract»

• ### A Two-Step Prediction ADC Architecture for Integrated Low Power Image Sensors

Publication Year: 2017, Page(s):50 - 60
Cited by:  Papers (6)
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This paper presents a two-step prediction method for the design of low-power column-parallel analog-to-digital converters (ADC) in CMOS image sensors. The proposed prediction method takes advantage of the spatial likelihood of natural scenes, which shows strong correlations between neighboring pixels in the image. Based on this property, the proposed method predicts the MSBs of the selected pixel ... View full abstract»

• ### A Numerical Methodology for the Analysis of Switched-Capacitor Filters Taking Into Account Non-Ideal Effects of Switches and Amplifiers

Publication Year: 2017, Page(s):61 - 71
Cited by:  Papers (2)
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This paper presents an efficient numerical methodology to obtain the frequency response of switched-capacitor filters based on the circuits' differential equations. This methodology uses a non-hierarchical approach in which the non-ideal effects of the transistors (in the switches and in the amplifier) are taken into consideration, allowing the accurate computation of the frequency response, even ... View full abstract»

• ### New Results and Techniques for Computation of Stored Energy in Lossless/All-Pass Systems

Publication Year: 2017, Page(s):72 - 85
Cited by:  Papers (4)
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Lossless and all-pass systems are energy-conservative in the sense that the energy that is extracted from the system always equals that supplied to the system. This stored energy turns out to be independent of the system realization/description. For example, there are different LC realizations of a lossless transfer function, but the energy stored can be uniquely expressed in terms of the port var... View full abstract»

• ### Post-Quantum Cryptography on FPGA Based on Isogenies on Elliptic Curves

Publication Year: 2017, Page(s):86 - 99
Cited by:  Papers (12)
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To the best of our knowledge, we present the first hardware implementation of isogeny-based cryptography available in the literature. Particularly, we present the first implementation of the supersingular isogeny Diffie-Hellman (SIDH) key exchange, which features quantum-resistance. We optimize this design for speed by creating a high throughput multiplier unit, taking advantage of parallelization... View full abstract»

• ### A Hybrid Time Borrowing Technique to Improve the Performance of Digital Circuits in the Presence of Variations

Publication Year: 2017, Page(s):100 - 110
Cited by:  Papers (2)
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Dynamic flip-flop conversion (DFFC) is a time borrowing method for improving the performance of digital circuits. Existing types of DFFC [11], [12] suffer from successive critical and critical feedback paths that are frequently seen in digital circuits. Moreover, they are unable to increase the performance of the designs with short sequential depth. In this paper, we introduce a hybrid technique w... View full abstract»

• ### A Reverse Converter and Sign Detectors for an Extended RNS Five-Moduli Set

Publication Year: 2017, Page(s):111 - 121
Cited by:  Papers (4)
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This paper deals with the extended five moduli set (22n+p, 2n- 1, 2n+ 1, 2n- 2n+1 /2+ 1, 2n+ 2n+1/2+ 1) where n is a positive odd integer and p is nonnegative integer such that p ≤ n-5/2. The paper proposes an efficient residue-to-binary converter along with a converter-based sign detector for this extended set. The paper... View full abstract»

• ### Dynamic Dual-Reference Sensing Scheme for Deep Submicrometer STT-MRAM

Publication Year: 2017, Page(s):122 - 132
Cited by:  Papers (10)
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As process technology downscales, read reliability has become a critical barrier for spin transfer torque magnetic random access memory (STT-MRAM), owing to the increasing process-temperature-voltage (PVT) variations, decreasing critical switching current of magnetic tunnel junction (MTJ) and supply voltage. To deal with the read reliability challenge, we propose herein a dynamic dual-reference se... View full abstract»

• ### A Bias-Bounded Digital True Random Number Generator Architecture

Publication Year: 2017, Page(s):133 - 144
Cited by:  Papers (6)
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Bias phenomenon has been a ubiquitous problem in the designs of digital True Random Number Generator (TRNG). Circuit performance can be improved with some auxiliary modules such as analog circuits and post-processing components, which usually involve the compromising of cost, compatibility, throughput, and security as well. In some cases only sub-optimal designs can be achieved. In this paper, by ... View full abstract»

• ### Analysis of Encoding Degradation in Spiking Sensors Due to Spike Delay Variation

Publication Year: 2017, Page(s):145 - 155
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Spiking sensors such as the silicon retina and cochlea encode analog signals into massively parallel asynchronous spike train output where the information is contained in the precise spike timing. The variation of the spike timing that arises from spike transmission degrades signal encoding quality. Using the signal-to-distortion ratio (SDR) metric with nonlinear spike train decoding based on fram... View full abstract»

• ### Statistical Analysis for Pattern-Dependent Simultaneous Switching Outputs (SSO) of Parallel Single-Ended Buffers

Publication Year: 2017, Page(s):156 - 169
Cited by:  Papers (1)
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Switching currents of simultaneous switching output (SSO) buffers can cause significant power-supply-induced jitter (PSIJ) and uncertainty in the output voltages. The bit error rate (BER) can be simulated by considering all possible input data patterns with a long data sequence; however, it requires large computational efforts. In this paper, the SSO waveforms are analytically calculated, includin... View full abstract»

• ### Reliable Output Feedback Control of Discrete-Time Fuzzy Affine Systems With Actuator Faults

Publication Year: 2017, Page(s):170 - 181
Cited by:  Papers (180)
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This article studies the robust and reliable H∞static output feedback (SOF) control for nonlinear systems with actuator faults in a descriptor system framework. The nonlinear plant is characterized by a discrete-time Takagi-Sugeno (T-S) fuzzy affine model with parameter uncertainties, and the Markov chain is utilized to describe the actuator-fault behaviors. Specifically, by adopting a ... View full abstract»

• ### A 4.7-Gb/s Reconfigurable CMOS Imaging Optical Receiver Utilizing Adaptive Spectrum Balancing Equalizer

Publication Year: 2017, Page(s):182 - 194
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This paper presents a fully integrated imaging receiver for high data rate wireless optical communication. A 3 × 3 matrix of Spatially Modulated Light detectors (SML), each with 730-MHz bandwidth followed by on-chip switches are integrated to allow the detection of photodiodes (PDs) in Line of Sight (LOS) with the transmitter. The imaging optical receiver employs a novel adaptive equalizer that us... View full abstract»

• ### Self-Learning RF Receiver Systems: Process Aware Real-Time Adaptation to Channel Conditions for Low Power Operation

Publication Year: 2017, Page(s):195 - 207
Cited by:  Papers (5)
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Prior research has established that dynamically trading-off the performance of the radio-frequency (RF) front-end for reduced power consumption across changing channel conditions, using a feedback control system that modulates circuit and algorithmic level “tuning knobs” in real-time based on received signal quality, leads to significant power savings. It is also known that the optimal power contr... View full abstract»

• ### Reliable Low-Latency Viterbi Algorithm Architectures Benchmarked on ASIC and FPGA

Publication Year: 2017, Page(s):208 - 216
Cited by:  Papers (3)
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The Viterbi algorithm is commonly applied to a number of sensitive usage models including decoding convolutional codes used in communications such as satellite communication, cellular relay, and wireless local area networks. Moreover, the algorithm has been applied to automatic speech recognition and storage devices. In this paper, efficient error detection schemes for architectures based on low-l... View full abstract»

• ### A 220-mV Power-on-Reset Based Self-Starter With 2-nW Quiescent Power for Thermoelectric Energy Harvesting Systems

Publication Year: 2017, Page(s):217 - 226
Cited by:  Papers (5)
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Miniaturized thin-film thermoelectric generators (TEGs) are emerging energy harvesting sources suitable for wearable and implantable applications. However, these sources usually exhibit large internal equivalent series resistance (ESR) that leads to low energy conversion efficiency and self-startup failures at ultra-low voltages. This paper presents a highly efficient boost converter with a novel ... View full abstract»

• ### Series-Parallel Charge Pump Conditioning Circuits for Electrostatic Kinetic Energy Harvesting

Publication Year: 2017, Page(s):227 - 240
Cited by:  Papers (9)
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This paper presents a new family of conditioning circuits used in electrostatic kinetic energy harvesters (e-KEHs), generalizing a previously reported conditioning circuit known as the Bennet's doubler. The proposed topology implements a conditioning scheme described by a rectangular charge-voltage cycle (QV-cycle) of tunable aspect ratio. These circuits show an exponential increase of the convert... View full abstract»

• ### IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors

Publication Year: 2017, Page(s): 241
| PDF (67 KB)
• ### IEEE Access

Publication Year: 2017, Page(s): 242
| PDF (633 KB)

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK