# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 19 of 19

Publication Year: 2016, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I:Regular Papers publication information

Publication Year: 2016, Page(s): C2
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• ### A 12-bit 210-MS/s 2-Times Interleaved Pipelined-SAR ADC With a Passive Residue Transfer Technique

Publication Year: 2016, Page(s):929 - 938
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A 12-bit 210-MS/s 2-channel time-interleaved analog-to-digital converter (ADC) employing a pipelined-SAR architecture for low-power and high-speed application is presented. The proposed ADC is partitioned into 3 stages with a passive residue transfer technique between the 1st and 2nd stages for power saving and active residue amplification between the 2nd and 3rd stages for noise consideration. Fu... View full abstract»

• ### A 70 mW 25 Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset With 40 dB of Equalization in 65 nm CMOS Technology

Publication Year: 2016, Page(s):939 - 949
Cited by:  Papers (2)
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A 25 Gb/s transmitter (TX) and receiver (RX) chipset designed in a 65 nm CMOS technology is presented. The proposed quarter-rate TX architecture with divider-less clock generation can not only guarantee the timing constraint for the highest-speed serialization, but also save power compared with the conventional designs. A source-series terminated (SST) driver with a 2-tap feed-forward equalizer (F... View full abstract»

• ### A 2.2 $\mu\text{W}$, $-$12 dBm RF-Powered Wireless Current Sensing Readout Interface IC With Injection-Locking Clock Generation

Publication Year: 2016, Page(s):950 - 959
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This paper presents a wireless-powering current-sensing readout system on a CMOS platform for portable electrochemical measurement. The wireless sensing system includes energy-efficient power management circuitry, a sensor readout interface, and a backscattering wireless communication scheme. For power-and-area-constrained bio-sensing applications, the proposed readout circuitry incorporates an ul... View full abstract»

• ### 72 dB SNR, 240 Hz Frame Rate Readout IC With Differential Continuous-Mode Parallel Architecture for Larger Touch-Screen Panel Applications

Publication Year: 2016, Page(s):960 - 971
Cited by:  Papers (1)
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This paper presents a mutual capacitive touch screen panel (TSP) readout IC (ROIC) with a differential continuousmode parallel operation architecture (DCPA). The proposed architecture achieves a high product of signal-to-noise ratio (SNR) and frame rate, which is a requirement of ROIC for large-sized TSP. DCPA is accomplished by using the proposed differential sensing method with a parallel archit... View full abstract»

• ### Micropower Mixed-Signal VLSI Independent Component Analysis for Gradient Flow Acoustic Source Separation

Publication Year: 2016, Page(s):972 - 981
Cited by:  Papers (2)
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A parallel micropower mixed-signal VLSI implementation of independent component analysis (ICA) with reconfigurable outer-product learning rules is presented. With the gradient sensing of the acoustic field over a miniature microphone array as a pre-processing method, the proposed ICA implementation can separate and localize up to 3 sources in mild reverberant environment. The ICA processor is impl... View full abstract»

• ### Frequency-Domain Optimization of Digital Switching Noise Based on Clock Scheduling

Publication Year: 2016, Page(s):982 - 993
Cited by:  Papers (1)
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The simultaneous switching activity in digital circuits challenges the design of mixed-signal SoCs. Rather than focusing on time-domain noise voltage minimization, this work optimizes switching noise in the frequency domain. A two-tier solution based on the on-chip clock scheduling is proposed. First, to cope with the switching noise at the fundamental clock frequency, which usually dominates in t... View full abstract»

• ### Exploiting Weak PUFs From Data Converter Nonlinearity—E.g., A Multibit CT $DeltaSigma$ Modulator

Publication Year: 2016, Page(s):994 - 1004
Cited by:  Papers (1)
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This paper presents a novel approach of deriving physical unclonable functions (PUF) from correction circuits measuring and digitizing nonlinearities of data converters. The often digitally available correction data can then be used to generate a fingerprint of the chip. The general concept is presented and then specifically evaluated on an existing Delta-Sigma (ΔΣ) modulator whose o... View full abstract»

• ### Area-Efficient Approach for Generating Quantized Gaussian Noise

Publication Year: 2016, Page(s):1005 - 1013
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This paper presents an efficient method to generate quantized Gaussian noise. The proposed method is derived based on the fact that any signal received at a digital system should be quantized to several bits. On the contrary to the previous works that have focused on the precision of noise, the quantization process is taken into account in generating noise samples. As a result, the resultant bit-w... View full abstract»

• ### Bitcell-Based Design of On-Chip Process Variability Monitors for Sub-28 nm Memories

Publication Year: 2016, Page(s):1014 - 1022
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On-chip process monitor/sensor circuits capture the process corner of a chip in the postfabrication stage. Logic-NMOS and logic-PMOS based sensors, however, fail to capture the process corners for memories, as bitcells have a different implant from logic cells. In this paper, a novel on-chip bitcell-based process monitor (BPMON) circuit is implemented that distinguishes between and detects the sta... View full abstract»

• ### Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology

Publication Year: 2016, Page(s):1023 - 1032
Cited by:  Papers (2)
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Although near-threshold voltage (NTV) operation is an attractive means of achieving high energy efficiency, it can degrade the circuit stability of static random access memory (SRAM) cells. This paper proposes an NTV 7T SRAM cell in a 14 nm FinFET technology to eliminate read disturbance by disconnecting the path from the bit-line to the cross-coupled inverter pair using the transmission gate. In ... View full abstract»

• ### CMOS Based Gates for Blurring Power Information

Publication Year: 2016, Page(s):1033 - 1042
Cited by:  Papers (2)
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Power analysis attacks have become one of the most significant security threats to modern cryptographic digital systems. In this paper, we introduce a new CMOS-based blurring gate (BG) which increases the immunity of a cryptographic system to these attacks. The BG switches randomly between two operational-modes, static and dynamic. When embedded in the crypto-core, the BGs enforce different and un... View full abstract»

• ### Lightweight TRNG Based on Multiphase Timing of Bistables

Publication Year: 2016, Page(s):1043 - 1054
Cited by:  Papers (1)
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The paper presents a concept of a True Random Number Generator (TRNG) that utilizes phase noise of a pair of ring oscillators (ROs) to increase the variance of the initial condition of a bistable. For this purpose a special TRNG D-latch architecture (TDL) has been proposed, which can either operate in the oscillatory ring-oscillator mode or the nearly-metastable mode. The RO mode increases the pro... View full abstract»

• ### Analysis of Mutually Injection-Locked Oscillators for Differential Resonant Sensing

Publication Year: 2016, Page(s):1055 - 1066
Cited by:  Papers (3)
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The potential benefits of oscillator synchronization are receiving increased interest in the resonant MEMS community, for clocking or sensing applications. In this paper, we explore the possibilities of differential resonant sensing applications based on the phase-difference between two injection-locked resonators, strongly coupled through an electronic mixer. A general model of such oscillators i... View full abstract»

• ### Combined Parametric and Worst Case Circuit Analysis via Taylor Models

Publication Year: 2016, Page(s):1067 - 1078
Cited by:  Papers (4)
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This paper proposes a novel paradigm to generate a parameterized model of the response of linear circuits with the inclusion of worst case bounds. The methodology leverages the so-called Taylor models and represents parameter-dependent responses in terms of a multivariate Taylor polynomial, in conjunction with an interval remainder accounting for the approximation error. The Taylor model represent... View full abstract»

• ### Synchronization of Coupled Harmonic Oscillators via Sampled Position Data Control

Publication Year: 2016, Page(s):1079 - 1088
Cited by:  Papers (9)
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This paper proposes two distributed synchronization protocols for a network of continuous-time coupled harmonic oscillators by utilizing current and past relative sampled position data, respectively. Some necessary and sufficient conditions in terms of coupling strength and sampling period are established to achieve network synchronization. By designing the coupling strength based on the nonzero e... View full abstract»

• ### Stability Analysis and Hardware Resource Optimization in Channel Emulator Design

Publication Year: 2016, Page(s):1089 - 1100
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In this work, we optimize hardware consumption in Rayleigh channel generation. Due to the advantage in saving memory resource, a recursive-structure-based channel generator is considered in this paper. We first investigate the long-term accuracy of channel generation by the recursive structure. Afterwards, we calculate the optimum bit width and channel update period at which normalized mean-square... View full abstract»

• ### IEEE Circuits and Systems Society Information

Publication Year: 2016, Page(s): C3
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## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK