# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 19 of 19

Publication Year: 2016, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

Publication Year: 2016, Page(s): C2
| PDF (135 KB)
• ### Phase Noise Reduction and Optimal Operating Conditions for a Pair of Synchronized Oscillators

Publication Year: 2016, Page(s):1 - 11
Cited by:  Papers (10)
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We investigate the dynamics of a pair of noisy coupled oscillators and derive operating conditions that minimize phase noise. The generic model employed allows for general nonlinear dynamics of the resonant elements of the oscillators, in terms of their amplitude-dependent frequencies, general asymmetric coupling, and both additive and multiplicative noise sources. The model is analyzed using the ... View full abstract»

• ### High-Efficiency Class-E Power Amplifier With Shunt Capacitance and Shunt Filter

Publication Year: 2016, Page(s):12 - 22
Cited by:  Papers (29)
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An analysis of a novel single-ended Class-E mode with shunt capacitance and shunt filter with explicit derivation of the idealized optimum voltage and current waveforms and load-network parameters with their verification by frequency domain simulations with 50% duty ratio is presented. The ideal collector voltage and current waveforms demonstrate a possibility of 100% efficiency. The circuit desig... View full abstract»

• ### Error Control and Limit Cycle Elimination in Event-Driven Piecewise Linear Analog Functional Models

Publication Year: 2016, Page(s):23 - 33
Cited by:  Papers (7)
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Real number modeling of analog circuits in hardware description languages (HDLs) has become more common as a part of mixed-signal SoC validation. We propose two methods that both improve the fidelity and simulation speed, and make the event-driven, piecewise linear (PWL) analog functional models easier to write. First we use the accuracy set by users to dynamically determine when a new output segm... View full abstract»

• ### Digital Calibration of DAC Unit Elements Mismatch in Pipelined ADCs

Publication Year: 2016, Page(s):34 - 45
Cited by:  Papers (5)
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This paper presents a statistics-based digital background calibration technique for digital-to-analog converter (DAC) unit elements mismatch in pipelined analog-to-digital converters (ADCs). The proposed calibration method continuously measures and digitally mitigates sub-DAC (SDAC) mismatch errors in background during the normal data-conversion operation. In this method, the probability density f... View full abstract»

• ### High-Gain Wide-Bandwidth Capacitor-Less Low-Dropout Regulator (LDO) for Mobile Applications Utilizing Frequency Response of Multiple Feedback Loops

Publication Year: 2016, Page(s):46 - 57
Cited by:  Papers (16)
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This paper presents a novel capacitor-less low-dropout regulator (LDO) for mobile applications. The proposed capacitor-less LDO utilizes multiple feedback loops to satisfy several design challenges for some mobile applications which were not considered in the previous capacitor-less LDOs. The proposed LDO has a wide bandwidth of 3.03 MHz at a load current of 150 mA with a bias current of 40 μA, an... View full abstract»

• ### High-Speed Polynomial Basis Multipliers Over$GF(2^{m})$for Special Pentanomials

Publication Year: 2016, Page(s):58 - 69
Cited by:  Papers (6)
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Efficient hardware implementations of arithmetic operations in the Galois field GF(2m) are highly desirable for several applications, such as coding theory, computer algebra and cryptography. Among these operations, multiplication is of special interest because it is considered the most important building block. Therefore, high-speed algorithms and hardware architectures for computing m... View full abstract»

• ### A Standard-Cell-Design-Flow Compatible Energy-Recycling Logic With 70% Energy Saving

Publication Year: 2016, Page(s):70 - 79
Cited by:  Papers (2)
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This paper presents an energy-recycling micro-architecture and the associated adiabatic logic for ultra-low energy applications, such as implantable bioelectronics. The proposed design achieves low power by transferring and recycling energy between digital logic blocks along with the signal propagation. The CMOS-like layout methodology allows the adiabatic logic core to be synthesized and auto-pla... View full abstract»

• ### General Characterization Method and a Fast Load-Charge-Preserving Switching Procedure for the Stepwise Adiabatic Circuits

Publication Year: 2016, Page(s):80 - 90
Cited by:  Papers (6)
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An analytical method is presented to characterize stepwise adiabatic circuits (SACs). In this method, the SACs are modeled as a discrete time system. Unlike previous methods, the stability is verified for arbitrary load capacitor ratios. Moreover, this method presents analytical derivations to offer an area/energy efficient design methodology. MATLAB simulations, post-layout simulations in the CMO... View full abstract»

• ### Exploiting Serial Access and Asymmetric Read/Write of Domain Wall Memory for Area and Energy-Efficient Digital Signal Processor Design

Publication Year: 2016, Page(s):91 - 102
Cited by:  Papers (6)
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In many digital signal processing (DSP) applications, static random access memory (SRAM) based embedded memory and flip-flop based shift registers consume a significant portion of area and power. These DSP units are dominated by sequential memory access where SRAM-based memory or flip-flop based shift registers are inefficient in terms of area and power. We propose spintronic domain wall memory (D... View full abstract»

• ### Minimization of Weighted Pole and Zero Sensitivity for State-Space Digital Filters

Publication Year: 2016, Page(s):103 - 113
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This paper presents a systematic study of pole and zero sensitivity minimization for state-space digital filters in several different yet related settings. First, a new weighted measure for pole and zero sensitivity for state-space digital filters is proposed and the problem of minimizing this measure is investigated. To this end, two efficient iterative techniques for minimizing this measure are ... View full abstract»

• ### On Existence and Stability of Equilibria of Linear Time-Invariant Systems With Constant Power Loads

Publication Year: 2016, Page(s):114 - 121
Cited by:  Papers (25)
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The problem of existence and stability of equilibria of linear systems with constant power loads is addressed in this paper. First, we correct an unfortunate mistake in our recent paper pertaining to the sufficiency of the condition for existence of equilibria in multiport systems given there. Second, we give two necessary conditions for existence of equilibria. The first one is a simple linear ma... View full abstract»

• ### A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s

Publication Year: 2016, Page(s):122 - 133
Cited by:  Papers (6)
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A differential transceiver achieves a 40 mVppd channel signal-swing, a 9 mVppd receiver (RX) input sensitivity, and a 0.59 pJ/b energy efficiency at 9 Gb/s with a 12" FR-4 channel. A current-integrating TIA (CI-TIA) is proposed as a RX pre-amplifier to enhance the RX input sensitivity by increasing the voltage gain of the CI-TIA to around 18 at 9 Gb/s. The RX circuit alone works up to 11 Gb/s with... View full abstract»

• ### A 3.0 Gb/s Throughput Hardware-Efficient Decoder for Cyclically-Coupled QC-LDPC Codes

Publication Year: 2016, Page(s):134 - 145
Cited by:  Papers (9)
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In this paper, we propose a new class of quasi-cyclic low-density parity-check (QC-LDPC) codes, namely cyclically-coupled QC-LDPC (CC-QC-LDPC) codes, and their RAM-based decoder architecture. CC-QC-LDPC codes have a simple structure and are constructed by cyclically-coupling a number of QC-LDPC subcodes. They can achieve throughput and error performance as excellent as LDPC convolutional codes, bu... View full abstract»

• ### System Design and Performance Analysis of Orthogonal Multi-Level Differential Chaos Shift Keying Modulation Scheme

Publication Year: 2016, Page(s):146 - 156
Cited by:  Papers (35)
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A novel non-coherent multi-level differential chaos shift keying (DCSK) modulation scheme is proposed in this paper. This new scheme is based on both the transmitted-reference technique and M-ary orthogonal modulation, where each data-bearing signal is chosen from a set of orthogonal chaotic wavelets constructed by a reference signal. Thanks to this signaling design, the new scheme can achieve a h... View full abstract»

• ### CMOS Power Amplifier Integrated Circuit With Dual-Mode Supply Modulator for Mobile Terminals

Publication Year: 2016, Page(s):157 - 167
Cited by:  Papers (8)
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A CMOS power amplifier integrated circuit with an optimized dual-mode supply modulator is presented. The dual-mode supply modulator, based on a hybrid buck converter consisting of a wideband linear amplifier and a highly efficient switching amplifier, provides two operation modes: envelope tracking (ET) for high average output power and average power tracking (APT) for low output power. For the AP... View full abstract»

• ### IEEE Transactions on Circuits and Systems—I: Regular Papers information for authors

Publication Year: 2016, Page(s): 168
| PDF (124 KB)
• ### IEEE Circuits and Systems Society Information

Publication Year: 2016, Page(s): C3
| PDF (113 KB)

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK