# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 25 of 32

Publication Year: 2011, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

Publication Year: 2011, Page(s): C2
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• ### A 0.5-V 0.4–2.24-GHz Inductorless Phase-Locked Loop in a System-on-Chip

Publication Year: 2011, Page(s):849 - 859
Cited by:  Papers (52)  |  Patents (1)
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A phase-locked loop (PLL) is proposed for low-voltage applications. A new charge pump (CP) circuit, using gate switches affords low leakage current and high speed operation. A low-voltage voltage-controlled oscillator (LV-VCO) composed of 4-stage delay cells and a low-voltage segmented current mirror (LV-SCM) achieves low voltage-controlled oscillator gain (KVCO), a wide tuning r... View full abstract»

• ### A CMOS 1.6 GHz Dual-Loop PLL With Fourth-Harmonic Mixing

Publication Year: 2011, Page(s):860 - 867
Cited by:  Papers (1)
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A 1.5-1.6 GHz dual-loop phase-locked loop in 0.18-μm CMOS locks in 40 μs and draws only 26 mA from 1.8 V. The proposed techniques include a fourth-harmonic mixer that relaxes the secondary PLL requirements, and an auxiliary charge pump that speeds acquisition without affecting steady-state operation. The integrated RMS phase error is 1.1° and the phase noise spectral density is -116.8 dBc/Hz at an... View full abstract»

• ### A Low-Power, Process-and- Temperature- Compensated Ring Oscillator With Addition-Based Current Source

Publication Year: 2011, Page(s):868 - 878
Cited by:  Papers (42)  |  Patents (1)
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The design of a 1.8 GHz 3-stage current-starved ring oscillator with a process- and temperature- compensated current source is presented. Without post-fabrication calibration or off-chip components, the proposed low variation circuit is able to achieve a 65.1% reduction in the normalized standard deviation of its center frequency at room temperature and 85 ppm/°C temperature stability w... View full abstract»

• ### Analysis of Imperfections on Performance of 4-Phase Passive-Mixer-Based High-Q Bandpass Filters in SAW-Less Receivers

Publication Year: 2011, Page(s):879 - 892
Cited by:  Papers (64)  |  Patents (4)
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It has been shown that an arrangement of four MOS switches and four baseband lowpass impedances can synthesize on-chip high-Q bandpass filters if the switches are driven by proper clock phases. The technique has been successfully utilized in receivers to replace external SAW filters. This paper analyzes performance of these filters in SAW-less receivers against imperfections such as clock phase-no... View full abstract»

• ### Circuits and System Design of RF Polar Transmitters Using Envelope-Tracking and SiGe Power Amplifiers for Mobile WiMAX

Publication Year: 2011, Page(s):893 - 901
Cited by:  Papers (37)  |  Patents (1)
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This paper discusses the circuits and system design methodology of a highly-efficient wideband RF polar transmitter (TX) using the envelope-tracking (ET) technique for mobile WiMAX applications. Monolithic power amplifiers (PAs) are designed and fabricated in IBM 0.18 μm SiGe BiCMOS technology, and a linear-assisted switch-mode envelope amplifier is applied to modulate the PA supply voltage to for... View full abstract»

• ### Analysis and Design of Class-E$_{3}$F and Transmission-Line Class-E$_{3}$F$_{2}$Power Amplifiers

Publication Year: 2011, Page(s):902 - 912
Cited by:  Papers (11)
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In this paper, analysis and synthesis approach for two new variants within the Class-EF power amplifier (PA) family is elaborated. These amplifiers are classified here as Class-E3F and transmission-line (TL) Class-E3F2. The proposed circuits offer means to alleviate some of the major issues faced by existing topologies such as substantial power losses due to the pa... View full abstract»

• ### All-Digital Time-Domain Smart Temperature Sensor With an Inter-Batch Inaccuracy of$-{\hbox {0.7}} ~^{\circ}{\hbox {C}}-+{\hbox {0.6}}~^{\circ}{\hbox {C}}$After One-Point Calibration

Publication Year: 2011, Page(s):913 - 920
Cited by:  Papers (45)
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To get rid of the heavy burden of aspect ratio tuning, bias adjustment and porting problem among processes in full-custom or mixed-mode design, a fully digital smart temperature sensor realizable with 140 field programmable gate array (FPGA) logic elements was proposed for painless VLSI on-chip integrations. By simply replacing the cyclic delay line with a retriggerable ring oscillator for accurac... View full abstract»

• ### An Adaptive Resolution Asynchronous ADC Architecture for Data Compression in Energy Constrained Sensing Applications

Publication Year: 2011, Page(s):921 - 934
Cited by:  Papers (60)
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An adaptive resolution (AR) asynchronous analog-to-digital converter (ADC) architecture is presented. Data compression is achieved by the inherent signal dependent sampling rate of the asynchronous architecture. An AR algorithm automatically varies the ADC quantizer resolution based on the rate of change of the input. This overcomes the trade-off between dynamic range and input bandwidth typically... View full abstract»

• ### Low Latency$GF(2^{m})$Polynomial Basis Multiplier

Publication Year: 2011, Page(s):935 - 946
Cited by:  Papers (8)
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Finite fieldGF(2m) arithmetic is becoming increasingly important for a variety of different applications including cryptography, coding theory and computer algebra. Among finite field arithmetic operations,GF(2m) multiplication is of special interest because it is considered the most important building block. This contribution describes a new low latency paralle... View full abstract»

• ### Design of Fixed-Width Multipliers With Linear Compensation Function

Publication Year: 2011, Page(s):947 - 960
Cited by:  Papers (32)  |  Patents (2)
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This paper focuses on fixed-width multipliers with linear compensation function by investigating in detail the effect of coefficients quantization. New fixed-width multiplier topologies, with different accuracy versus hardware complexity trade-off, are obtained by varying the quantization scheme. Two topologies are in particular selected as the most effective ones. The first one is based on a unif... View full abstract»

• ### Design of a Low-Power Coprocessor for Mid-Size Vocabulary Speech Recognition Systems

Publication Year: 2011, Page(s):961 - 970
Cited by:  Papers (6)  |  Patents (3)
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Speech recognition systems have gained popularity in consumer electronics. This paper presents a custom-designed coprocessor for output probability calculation (OPC), which is the most computation-intensive processing step in continuous hidden Markov model (CHMM)-based speech recognition algorithms. To save hardware resource and reduce power consumption, a polynomial addition-based method is used ... View full abstract»

• ### Application-Specific Processor for Piecewise Linear Functions Computation

Publication Year: 2011, Page(s):971 - 981
Cited by:  Papers (7)
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This paper presents an application specific processor architecture for the calculation of simplicial piecewise linear functions of up to six dimensions with 24-bit wide input words. The architecture, in particular registers and bus connections, is specifically designed for the task of simplicial piecewise linear computation. The parameters of the function are stored in an external 16 MB RAM memory... View full abstract»

• ### Radix-8 Booth Encoded Modulo$2 ^{n} -1$Multipliers With Adaptive Delay for High Dynamic Range Residue Number System

Publication Year: 2011, Page(s):982 - 993
Cited by:  Papers (20)
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A special moduli set Residue Number System (RNS) of high dynamic range (DR) can speed up the execution of very-large word-length repetitive multiplications found in applications like public key cryptography. The modulo 2n-1 multiplier is usually the noncritical datapath among all modulo multipliers in such high-DR RNS multiplier. This timing slack can be exploited to reduce the system a... View full abstract»

• ### Exponential$H_{\infty}$Filter Design for Discrete Time-Delay Stochastic Systems With Markovian Jump Parameters and Missing Measurements

Publication Year: 2011, Page(s):994 - 1007
Cited by:  Papers (34)
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In this paper, the exponentialH∞filtering problem is studied for discrete time-delay stochastic systems with Markovian jump parameters and missing measurements. The measurement missing phenomenon, which is related to the modes of subsystems, is described in the form of random matrix function and the missing probability of each sensor at every mode is governed by an individual ran... View full abstract»

• ### Closed-Form Mixed Design of High-Accuracy All-Pass Variable Fractional-Delay Digital Filters

Publication Year: 2011, Page(s):1008 - 1019
Cited by:  Papers (32)
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This paper presents a closed-form method for minimizing the weighted squared error of variable fractional-delay (VFD) of an all-pass VFD digital filter under an equality constraint on its normalized root-mean-squared (NRMS) error of variable frequency response (VFR). The main purpose is to reduce the squared VFD error as much as possible while keeping its NRMS VFR error exactly at a predetermined ... View full abstract»

• ### Stochastic Analysis of the Normalized Subband Adaptive Filter Algorithm

Publication Year: 2011, Page(s):1020 - 1033
Cited by:  Papers (36)
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This paper studies the statistical behavior of the normalized subband adaptive filtering (NSAF) algorithm. An accurate statistical model of the NSAF algorithm is obtained. In the derivation, we focus on Gaussian correlated input signals. By assuming that the analysis filter bank is paraunitary and taking into account the full band adaptation mechanism of the NSAF, expressions for the first and the... View full abstract»

• ### Silicon-Neuron Design: A Dynamical Systems Approach

Publication Year: 2011, Page(s):1034 - 1043
Cited by:  Papers (57)
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We present an approach to design spiking silicon neurons based on dynamical systems theory. Dynamical systems theory aids in choosing the appropriate level of abstraction, prescribing a neuron model with the desired dynamics while maintaining simplicity. Further, we provide a procedure to transform the prescribed equations into subthreshold current-mode circuits. We present a circuit design exampl... View full abstract»

• ### True Random Number Generation Via Sampling From Flat Band-Limited Gaussian Processes

Publication Year: 2011, Page(s):1044 - 1051
Cited by:  Papers (17)
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We consider a true random number generator based on regularly sampling a thresholded wide sense stationary Gaussian noise source of which power spectral density is assumed to be flat between two known frequencies and zero everywhere else. We employ per-sample joint entropy of the resulting bit sequence as the main figure of merit and present novel analytical results on the optimum choice of the sa... View full abstract»

• ### Limit Set Dichotomy and Convergence of Cooperative Piecewise Linear Neural Networks

Publication Year: 2011, Page(s):1052 - 1062
Cited by:  Papers (18)
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This paper considers a class of nonsymmetric cooperative neural networks (NNs) where the neurons are fully interconnected and the neuron activations are modeled by piecewise linear (PL) functions. The solution semiflow generated by cooperative PLNNs is monotone but, due to the horizontal segments in the neuron activations, is not eventually strongly monotone (ESM). The main result in this paper is... View full abstract»

• ### On Full-Connectivity Properties of Locally Connected Oscillatory Networks

Publication Year: 2011, Page(s):1063 - 1075
Cited by:  Papers (3)
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The latest many-core chip technology advances foster highly parallel computing systems. Consequently, it is crucial to conceive hardware oriented architectures and to realize VLSI platforms, with kilo- or mega-processors, that are able to process and recognize spatial-temporal patterns without breaking them into frames. Oscillatory networks, their archetype being the Turing morphogenesis model, re... View full abstract»

• ### On the VLSI Implementation of Adaptive-Frequency Hopf Oscillator

Publication Year: 2011, Page(s):1076 - 1088
Cited by:  Papers (5)
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In this paper, a new VLSI implementable Hopf oscillator with dynamic plasticity is proposed for next-generation portable signal processing application. A circuit-realizable piece-wise linear function has been used to govern the frequency adaptation characteristic of the proposed oscillator. Furthermore, a straightforward method is suggested to extract the frequency component of the input signal. M... View full abstract»

• ### Design-Oriented Analysis of Circuits With Equality Constraints

Publication Year: 2011, Page(s):1089 - 1098
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This paper presents a design-oriented circuit analysis that is augmented with design constraints. This analysis computes the circuit response and also finds the values of circuit parameters (equal to the number of design specifications) that result in a specified circuit performance. An application of this approach is demonstrated for the periodic steady-state analysis with shooting and finite dif... View full abstract»

• ### Notes on the State Space Realizations of Rational Order Transfer Functions

Publication Year: 2011, Page(s):1099 - 1108
Cited by:  Papers (21)
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In this paper, the concept of minimal state space realization for a fractional order system is defined from the inner dimension point of view. Some basic differences of the minimal realization concept in the fractional and integer order systems are discussed. Five lower bounds are obtained for the inner dimension of a minimal state space realization of a fractional order transfer function. Also, t... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK