IEEE Transactions on Circuits and Systems I: Regular Papers

Continuous-time ΔΣ modulators (CTDSMs) with switched-capacitor (SC) feedback digital-to-analog converters (DACs) are relatively less sensitive to clock jitter when compared to converters that use non-return-to-zero feedback DACs. However, as we show in this paper, using an SC DAC can seriously compromise the alias rejection of the modulator, thereby nullifying one of the principal ad... View full abstract»

This paper presents a transmitter architecture based on a pulse-modulated polar transmitter using multiphase pulsewidth modulation. The modulation to the radio-frequency input signal, instead of conventional drain modulation, significantly reduces the circuit complexity, while the multiphase modulation technique reduces the out-of-band emissions. An 836.5-MHz four-phase prototype transmitter using... View full abstract»

Clock jitter is one of the most fundamental obstacles in realizing future generations of wideband receivers. Stringent jitter specifications in the sampling clocks of high-performance single-channel and multichannel time-interleaved analog-to-digital converters severely limit the evolution of baseband receivers. This paper presents an analytical framework for the design of clock-jitter-tolerant lo... View full abstract»

Type-II charge-pump (CP) phase-locked loop (PLLs) are used extensively in electronic systems for frequency synthesis. Recently, a passive sampled loop filter (SLF) has been shown to offer major benefits over the conventional continuous-time loop filter traditionally used in such PLLs. These benefits include greatly enhanced reference spur suppression, elimination of CP pulse-position modulation no... View full abstract»

This paper presents a model of active mixers for a fast and accurate estimation of noise and nonlinearity. Based on closed-form expressions, this model estimates the noise figure, IIP3, and IIP2 of the time-varying mixer by a limited number of time-invariant circuit calculations. The model shows that the decreasing transistor output resistance, together with the low supply voltage in deep-submicro... View full abstract»

The modulation and demodulation blocks in an orthogonal frequency-division multiplexing (OFDM) system are typically implemented digitally using a fast Fourier transform circuit. We propose an analog implementation of an OFDM demodulator as a means for reducing power consumption. The proposed receiver implements the discrete Fourier transform (DFT) as a vector-matrix multiplier using floating-gate ... View full abstract»

This paper reports on a new approach for the analysis and design of vibration-to-electricity converters [vibration energy harvesters (VEHs)] operating in the mode of strong electromechanical coupling. The underlying concept is that the mechanical impedance is defined for a nonlinear electromechanical transducer on the basis of an equivalence between electrical and mechanical systems. This paper de... View full abstract»

The paper describes the development of a model for the calculation of noise-driven phase response of an injection-locked oscillator perturbed by Gaussian white sources. Being based on the state space formalism the framework is unified encompassing all circuit topologies and methods of unilateral coupling. We thus avoid reverting to the kind of simplified block-diagram description that one finds in... View full abstract»

A nonlinear system being composed of multiadaptive notch filters in parallel is introduced to track the sinusoidal components of an almost periodic signal and estimate their frequencies and amplitudes. An almost periodic nonlinear dynamic system for estimation of frequencies is achieved after the existence of a slow integral manifold is proved and results in a nonlinear autonomous system with aver... View full abstract»

This paper derives a novel approach to prove contraction of nonlinear dynamical systems, based on the use of non-Euclidean norms and their associated matrix measures. A graphical procedure is developed to derive conditions for a system to be contracting. Such conditions can also be used to design control strategies to make a system contracting, or to design consensus and synchronization strategies... View full abstract»

In this paper, the H∞ theory is introduced to investigate the robustness and design of synchronization nonlinear coupled network. The H∞ synchronization performance is defined as the disturbance attenuation ability for a synchronized coupled network. To measure the H∞ synchronization performance of a nonlinear coupled netwo... View full abstract»

Six preprocessing algorithms for the detection of firearm gunshots are statistically evaluated, using the receiver operating characteristic method as a previous feasibility metric for their implementation on a low-power VLSI circuit. Circuits are intended to serve as the input detection sensors of a low-power environmental surveillance network. Some possible VLSI implementations for the evaluated ... View full abstract»

Motivated by different applications in circuits, electromagnetics, and optics, this paper is concerned with the synthesis of a particular type of linear circuit, where the circuit is associated with a control unit. The objective is to design a controller for this control unit such that certain specifications on the parameters of the circuit are satisfied. It is shown that designing a control unit ... View full abstract»

This paper is concerned with stabilization of linear systems with arbitrarily large but bounded time-varying delay in the input. A pole assignment based low gain feedback design is adopted to solve the problem. Both delay-dependent and delay-independent results are presented and a series of sufficient conditions for guaranteeing the stability of the closed-loop system are established. By using pro... View full abstract»

Nonbinary low-density parity-check (NB-LDPC) codes constructed over GF(q) (q >; 2) can achieve higher coding gain than binary LDPC codes when the code length is moderate. A complete partial-parallel decoder architecture based on the Min-max algorithm is proposed for quasi-cyclic NB-LDPC codes in this paper. A novel scheme and corresponding architecture are developed to implement the elementary ... View full abstract»

In this paper, we propose dividing the decoding operations of a variety of irregular quasi-cyclic (QC) low-density parity-check (LDPC) codes into several smaller tasks. An algorithm is devised in order to arrange these tasks in a similar form such that a highly reusable multimode architecture can be designed to process these tasks. For this task-based decoder, the associated memory access can be a... View full abstract»

As technology continues to scale down, NAND Flash memory has been increasingly relying on error-correction codes (ECCs) to ensure the overall data storage integrity. Although advanced ECCs such as low-density parity-check (LDPC) codes can provide significantly stronger error-correction capability over BCH codes being used in current practice, their decoding requires soft-decision log-likelihood ra... View full abstract»