# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 17 of 17

Publication Year: 2010, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

Publication Year: 2010, Page(s): C2
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• ### Guest Editorial Special Section on 2009 IEEE System-on-Chip Conference

Publication Year: 2010, Page(s):3037 - 3038
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• ### Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist

Publication Year: 2010, Page(s):3039 - 3047
Cited by:  Papers (36)  |  Patents (2)
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In this paper, asymmetrical Write-assist cell virtual ground biasing scheme and positive feedback sensing keeper schemes are proposed to improve the read static noise margin (RSNM), write margin (WM), and operation speed of a single-ended read/write 8 T SRAM cell. A 4 Kbit SRAM test chip is implemented in 90 nm CMOS technology. The test chip measurement results show that at 0.2 V VDD, a... View full abstract»

• ### Nonclassical Channel Design in MOSFETs for Improving OTA Gain-Bandwidth Trade-Off

Publication Year: 2010, Page(s):3048 - 3054
Cited by:  Papers (14)
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In this paper, gain-bandwidth (GB) trade-off associated with analog device/circuit design due to conflicting requirements for enhancing gain and cutoff frequency is examined. It is demonstrated that the use of a nonclassical source/drain (S/D) profile (also known as underlap channel) can alleviate the GB trade-off associated with analog design. Operational transconductance amplifier (OTA) with 60 ... View full abstract»

• ### Variability Aware Low-Power Delay Optimal Buffer Insertion for Global Interconnects

Publication Year: 2010, Page(s):3055 - 3063
Cited by:  Papers (7)
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Global interconnect delay variations may cause clock skew, unpredictable signal line delays, and degraded system performance. Conventional variation mitigation techniques incur large delay and power overheads, as variability increases in sub-65 nm technologies. This paper presents a methodology to include robustness optimization in power-delay optimal buffer insertion. Closed form expressions are ... View full abstract»

• ### A 14.6 ps Resolution, 50 ns Input-Range Cyclic Time-to-Digital Converter Using Fractional Difference Conversion Method

Publication Year: 2010, Page(s):3064 - 3072
Cited by:  Papers (16)
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This paper presents a time-to-digital converter (TDC) using a fractional difference conversion scheme. Two delay-locked loops (DLLs) provide negative feedbacks to stabilize the delays against process and ambient variations. In addition, by adopting the principles of cyclic Vernier delay line, the resolution is improved while dynamic range is significantly increased. The proposed TDC architecture i... View full abstract»

• ### A High-Speed, Energy-Efficient Two-Cycle Multiply-Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit

Publication Year: 2010, Page(s):3073 - 3081
Cited by:  Papers (8)
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We propose a high-speed and energy-efficient two-cycle multiply-accumulate (MAC) architecture that supports two's complement numbers, and includes accumulation guard bits and saturation circuitry. The first MAC pipeline stage contains only partial-product generation circuitry and a reduction tree, while the second stage, thanks to a special sign-extension solution, implements all other functionali... View full abstract»

• ### Quantization Noise Minimization in $SigmaDelta$ Modulation Based RF Transmitter Architectures

Publication Year: 2010, Page(s):3082 - 3091
Cited by:  Papers (11)
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This paper describes an optimization method for minimization of quantization noise in ΣΔ-based RF transmitters. The aim of the method is to enable the use of reconstruction filters with wider passband, or alternatively, a lower switch-rate. The method uses a general representation of the ΣΔ converters in combination with a differentiable approximation of the quantizer. ... View full abstract»

• ### Implications of Passive Mixer Transparency for Impedance Matching and Noise Figure in Passive Mixer-First Receivers

Publication Year: 2010, Page(s):3092 - 3103
Cited by:  Papers (86)  |  Patents (11)
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In this paper, a class of passive mixer-first, LNA-less receivers is analyzed in depth. Quadrature passive mixers are shown to present the impedance of their baseband port to the RF port and vice versa. This transparency property, in combination with resistive feedback differential amplifiers, and “complex” feedback between the I and Q paths, can be used to control the impedance at t... View full abstract»

• ### Modeling and Filtering Double-Frequency Jitter in One-Way Master–Slave Chain Networks

Publication Year: 2010, Page(s):3104 - 3111
Cited by:  Papers (9)
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One-way master-slave (OWMS) chain networks are widely used in clock distribution systems due to their reliability and low cost. As the network nodes are phase-locked loops (PLLs), double-frequency jitter (DFJ) caused by their phase detectors appears as an impairment to the performance of the clock recovering process found in communication systems and instrumentation applications. A nonlinear model... View full abstract»

• ### A CMOS Current-Mode Dynamic Programming Circuit

Publication Year: 2010, Page(s):3112 - 3123
Cited by:  Papers (5)
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Dynamic programming (DP) is a fundamental algorithm for complex optimization and decision-making in many engineering and biomedical systems. However, conventional DP computation based on digital implementation of the Bellman-Ford recursive algorithm suffers from the “curse of dimensionality” and substantial iteration delays which hinder utility in real-time applications. Previously, ... View full abstract»

• ### Implementation and Testing of High-Speed CMOS True Random Number Generators Based on Chaotic Systems

Publication Year: 2010, Page(s):3124 - 3137
Cited by:  Papers (39)
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We present the design and the validation by means of suitably improved randomness tests of two different implementations of high-performance true-random number generators which use a discrete-time chaotic circuit as their entropy source. The proposed system has been developed from a standard pipeline Analog-to-Digital converter (ADC) design, modified to operate as a set of piecewise-linear chaotic... View full abstract»

• ### Linear Passive Networks With Ideal Switches: Consistent Initial Conditions and State Discontinuities

Publication Year: 2010, Page(s):3138 - 3151
Cited by:  Papers (21)
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This paper studies linear passive electrical networks with ideal switches. We employ the so-called linear switched systems framework in which these circuits can be analyzed for any given switch configuration. After providing a complete characterization of admissible inputs and consistent initial states with respect to a switch configuration, the paper introduces a new state reinitialization rule t... View full abstract»

• ### IEEE Transactions on Circuits and Systems—I: Regular Papers Information for authors

Publication Year: 2010, Page(s): 3152
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• ### 2010 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 57

Publication Year: 2010, Page(s):3153 - 3183
| PDF (420 KB)
• ### IEEE Circuits and Systems Society Information

Publication Year: 2010, Page(s): C3
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## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK