# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 25 of 35

Publication Year: 2010, Page(s):C1 - C4
| PDF (122 KB)
• ### IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

Publication Year: 2010, Page(s): C2
| PDF (135 KB)
• ### Guest Editorial Special Section on 2009 IEEE Custom Integrated Circuits Conference

Publication Year: 2010, Page(s):2245 - 2247
| PDF (526 KB) | HTML

Publication Year: 2010, Page(s):2248 - 2258
Cited by:  Papers (17)
| | PDF (1387 KB) | HTML

Digital receiver frontends have emerged as a possible solution for the next-generation serial I/O receiver design in advanced CMOS technologies. The challenge is to achieve low power dissipation so that the I/O links can be integrated in large ASICs. With a power budget of &lt;; 20 mW/Gb/s, the feasibility of an ADC-based receiver is limited by the high-speed analog-to-digital converter (ADC) ... View full abstract»

• ### Insights Into Wideband Fractional ADPLLs: Modeling and Calibration of Nonlinearity Induced Fractional Spurs

Publication Year: 2010, Page(s):2259 - 2268
Cited by:  Papers (10)
| | PDF (2007 KB) | HTML

As technology pushes deeper into the nanoscale, the difficulty in developing high-performance analog functions has driven an explosion in digitally intensive architectures to replace them. Commonalities among these new architectures include a paradigm shift toward temporal versus voltage encoding of analog signals, and the extensive use of digital calibration. In particular, recent developments in... View full abstract»

• ### 47% Power Reduction and 91% Area Reduction in Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking

Publication Year: 2010, Page(s):2269 - 2278
Cited by:  Papers (6)
| | PDF (2482 KB) | HTML

This paper presents a power reduction scheme and an area reduction scheme in inductive-coupling programmable bus for NAND flash memory stacking. A channel arrangement scheme using three coils enables random access for memory read and memory write. Transmit power is reduced by 47% compared to a previous design with shields. A coil layout style, herein noted as XY coil, allows for the coils to inter... View full abstract»

• ### Ultralow-Power Electronics for Cardiac Monitoring

Publication Year: 2010, Page(s):2279 - 2290
Cited by:  Papers (3)
| | PDF (1771 KB) | HTML

Ultralow-power electronics for cardiac monitoring make possible the development of new light-weight and low-cost devices that are ideal for long-term medical measurements and home-based tele-monitoring services. Nowadays, these devices are seen as a critical technology for reducing health-care costs. In this paper, we present several methods for reducing power consumption while retaining the preci... View full abstract»

• ### A Passive UHF RFID Demodulator With RF Overvoltage Protection and Automatic Weighted Threshold Adjustment

Publication Year: 2010, Page(s):2291 - 2300
Cited by:  Papers (11)  |  Patents (2)
| | PDF (1478 KB) | HTML

This paper presents a passive UHF RFID ASK demodulator that operates over a +24 dBm to -14 dBm RF input power range. The demodulator automatically adjusts between high sensitivity mode for weak RF signal power and overvoltage protection mode for high RF power. The input overvoltage protection circuit is designed to protect the IC from high input power while not impacting the sensitivity at weak in... View full abstract»

• ### ESD Design Strategies for High-Speed Digital and RF Circuits in Deeply Scaled Silicon Technologies

Publication Year: 2010, Page(s):2301 - 2311
Cited by:  Papers (14)
| | PDF (1194 KB) | HTML

Challenges of electrostatic discharge (ESD) protection in deeply scaled silicon technologies are addressed by improving design, characterization, and modeling of I/O MOSFETs, interconnect, ESD protection and power clamp devices. Recent progress on ESD protection design for both high-speed digital I/O and radiofrequency (RF) circuits are presented. Topological trade-offs are compared. High speed ci... View full abstract»

• ### A CMOS Low-Dropout Regulator With a Momentarily Current-Boosting Voltage Buffer

Publication Year: 2010, Page(s):2312 - 2319
Cited by:  Papers (47)  |  Patents (1)
| | PDF (1398 KB) | HTML

An energy-efficient voltage buffer for a low-dropout regulator (LDO) is presented in this paper. The voltage buffer contains a current-boosting circuit with quick-on and auto-off features so that it can momentarily provide an extra current to charge and discharge the large gate capacitance of the power transistor. The voltage buffer is therefore able to increase the slew rate at the gate of the po... View full abstract»

• ### A Randomized Wrapped-Around Pulse Position Modulation Scheme for DC–DC Converters

Publication Year: 2010, Page(s):2320 - 2333
Cited by:  Papers (19)
| | PDF (1129 KB) | HTML

We present a novel randomized wrapped-around pulse position modulation (RWAPPM) scheme for digital modulators of dc-dc converters. Unlike the reported modulation schemes that require a varying switching period (thereby resulting in high attenuation or complete elimination of discrete harmonics), the proposed RWAPPM conversely requires only a constant switching period (thereby advantageous in terms... View full abstract»

• ### Analysis of Class-DE Amplifier With Linear and Nonlinear Shunt Capacitances at 25% Duty Ratio

Publication Year: 2010, Page(s):2334 - 2342
Cited by:  Papers (6)
| | PDF (1469 KB) | HTML

The class-E zero-voltage switching/zero-derivative switching operation within class-DE amplifiers can be easily achieved by adding external shunt capacitances. This paper gives the analytical expressions for the designs of the class-DE amplifiers with the shunt capacitances composed of linear and nonlinear capacitances for any grading coefficient <i>m</i> of MOSFET body junction diodes... View full abstract»

• ### Performance of Coupled-Oscillator Arrays With Angle-Modulated Injection Signals

Publication Year: 2010, Page(s):2343 - 2352
Cited by:  Papers (3)
| | PDF (2186 KB) | HTML

A nonlinear analysis of coupled-oscillator systems under modulated inputs is presented. Angle modulation is introduced to the array by injection locking one of the oscillators to an external modulated reference signal. Envelope transient analysis is used to investigate the effect of the modulation versus scanning angle. Furthermore, a simplified model for the array is provided based on a perturbat... View full abstract»

• ### Analysis and Optimization of Direct-Conversion Receivers With 25% Duty-Cycle Current-Driven Passive Mixers

Publication Year: 2010, Page(s):2353 - 2366
Cited by:  Papers (111)  |  Patents (5)
| | PDF (2929 KB) | HTML

The performance of zero-IF receivers with current-driven passive mixers driven by 25% duty-cycle quadrature clocks is studied and analyzed. It is shown that, in general, these receivers outperform the ones that utilize passive mixers with 50% duty-cycle clocks. The known problems in receivers with 50% duty-cycle mixers, such as having unequal high- and low-side conversion gains, unexpected IIP2 an... View full abstract»

• ### Statistical Analysis of First-Order Bang-Bang Phase-Locked Loops Using Sign-Dependent Random-Walk Theory

Publication Year: 2010, Page(s):2367 - 2380
Cited by:  Papers (12)
| | PDF (707 KB) | HTML

Bang-bang phase-locked loops (BBPLLs) are inherently nonlinear due to the hard nonlinearity introduced by the binary phase detector (BPD). This paper provides an exact statistical analysis of the steady-state timing jitter in a first-order BBPLL when the reference clock is subject to accumulative jitter. By elaborating on the analogy of viewing a first-order BBPLL as a single-integration delta mod... View full abstract»

• ### Nonharmonic Injection-Locked Phase-Locked Loops With Applications in Remote Frequency Calibration of Passive Wireless Transponders

Publication Year: 2010, Page(s):2381 - 2393
Cited by:  Papers (16)
| | PDF (1909 KB) | HTML

This paper proposes a low-power remote frequency calibration method for passive UHF wireless transponders. The frequency of the local oscillator of passive UHF wireless transponders is adjusted to the desired values using an injection-locked phase-locked loop (IL-PLL). A new relaxation oscillator whose oscillation frequency is less sensitive to supply voltage fluctuation is proposed. The power con... View full abstract»

• ### Efficient Dithering in MASH Sigma-Delta Modulators for Fractional Frequency Synthesizers

Publication Year: 2010, Page(s):2394 - 2403
Cited by:  Papers (27)
| | PDF (1822 KB) | HTML

The digital multistage-noise-shaping (MASH) ΣΔ modulators used in fractional frequency synthesizers are prone to spur tone generation in their output spectrum. In this paper, the state of the art on spur-tone-magnitude reduction is used to demonstrate that anM-bit MASH architecture dithered by a simpleM-bit linear feedback shift register (LFSR) can be as effective as more sophisticat... View full abstract»

• ### A/D Conversion Using Asynchronous Delta-Sigma Modulation and Time-to-Digital Conversion

Publication Year: 2010, Page(s):2404 - 2412
Cited by:  Papers (50)  |  Patents (3)
| | PDF (663 KB) | HTML

An analog-to-digital conversion (ADC) scheme based on asynchronous ΔΣ modulation and time-to-digital conversion is presented. An asynchronous ΔΣ modulator translates the analog input to an asynchronous duty-cycle modulated signal. Next, the edge locations are digitally measured using a time-to-digital converter (TDC). This information is then digitally processed into a conventional digital signal.... View full abstract»

• ### Continuous-Time Sigma–Delta Modulator With a Fast Tracking Quantizer and Reduced Number of Comparators

Publication Year: 2010, Page(s):2413 - 2425
Cited by:  Papers (5)  |  Patents (2)
| | PDF (550 KB) | HTML

Using a tracking analog-to-digital converter as the quantizer of a sigma-delta modulator (SDM) has been shown to be an efficient method of reducing the number of comparators. In this paper, a new continuous-time (CT) SDM is proposed where a large reduction in the number of comparators is obtained by clocking the quantizer tracking loop at a high frequency rate. For a given example, the number of b... View full abstract»

• ### Spur-Free MASH Delta-Sigma Modulation

Publication Year: 2010, Page(s):2426 - 2437
Cited by:  Papers (25)
| | PDF (3499 KB) | HTML

For multistage noise-shaping (MASH) delta-sigma modulation, this paper presents a new structure that is free of spurs for all input values. The proposed MASH structure cascades several first-order delta-sigma modulators (DSMs) like the traditional MASH structure but has an additional feedforward connection between two adjacent stages. The proposed MASH structure can increase the sequence length an... View full abstract»

• ### On Chopper Effects in Discrete-Time$\Sigma\Delta$Modulators

Publication Year: 2010, Page(s):2438 - 2449
Cited by:  Papers (5)
| | PDF (1630 KB) | HTML

Analog-to-digital converters based on ΣΔ modulators are used in a wide variety of applications. Due to their inherent monotonous behavior, high linearity, and large dynamic range, they are often the preferred option for sensor and instrumentation. Offset and flicker noise are usual concerns for this type of applications, and one way to minimize their effects is to use a chopper in the front-end in... View full abstract»

• ### A Low-Voltage Fourth-Order Cascade Delta–Sigma Modulator in 0.18-$\mu\hbox{m}$CMOS

Publication Year: 2010, Page(s):2450 - 2461
Cited by:  Papers (16)
| | PDF (1516 KB) | HTML

In this paper, a low-voltage fourth-order 2-2 cascade delta-sigma (ΔΣ) modulator using the proposed double-sampling switched-operational-amplifier (SOP)-based integrator is presented. In the analog part of the ΔΣ modulator, most of the power consumption comes from the SOP used in the integrator. Hence, the requirement of the SOP must effectively be relaxed to reduce the power consumption of the mo... View full abstract»

• ### Digital Calibration of Nonlinear Memory Errors in Sigma–Delta Modulators

Publication Year: 2010, Page(s):2462 - 2475
Cited by:  Papers (5)
| | PDF (1011 KB) | HTML

A digital adaptive calibration technique to linearize sigma-delta (ΣΔ) modulators based on an output-referred distortion analysis of discrete-time integrators (DTIs) is presented. A sequential power series (a special form of Volterra series) is found sufficient to model the nonlinear memory errors in a DTI, which entails the application of adaptive polynomial transversal filtering for error correc... View full abstract»

• ### A Radius Adaptive K-Best Decoder With Early Termination: Algorithm and VLSI Architecture

Publication Year: 2010, Page(s):2476 - 2486
Cited by:  Papers (38)  |  Patents (1)
| | PDF (1621 KB) | HTML

This paper presents a novel algorithm and architecture for K-Best decoding that combines the benefits of radius shrinking commonly associated with sphere decoding and the architectural benefits associated with K-Best decoding approaches. The proposed algorithm requires much smaller K and possesses the advantages of branch pruning and adaptively updated pruning threshold while still achieving near-... View full abstract»

• ### An FPGA-Based Linear All-Digital Phase-Locked Loop

Publication Year: 2010, Page(s):2487 - 2497
Cited by:  Papers (28)
| | PDF (548 KB) | HTML

In this paper, an all-digital phase-locked loop (ADPLL) is presented, and it is implemented on a field-programmable gate array. All components like the phase detector (PD), oscillator, and loop filter are realized as digital discrete-time components fed from analog-to-digital converters. The phase detection is realized by generating first an analytic signal using a compact implementation of the Hi... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK