# IEEE Transactions on Circuits and Systems I: Regular Papers

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Displaying Results 1 - 25 of 43

Publication Year: 2010, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

Publication Year: 2010, Page(s): C2
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• ### Design of $X$-Band and $Ka$-Band Colpitts Oscillators Using a Parasitic Cancellation Technique

Publication Year: 2010, Page(s):1817 - 1828
Cited by:  Papers (9)
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An X-band and two Ka-band monolithic microwave integrated circuit (MMIC) common drain Colpitts oscillators using a parasitic cancellation technique are designed and fabricated in a 0.2-μm GaAs pHEMT technology with a fT of 60 GHz. The parasitic cancellation technique significantly improves the negative resistance and increases the maximum operating frequency,... View full abstract»

• ### An Asynchronous Binary-Search ADC Architecture With a Reduced Comparator Count

Publication Year: 2010, Page(s):1829 - 1837
Cited by:  Papers (29)
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This paper reports an asynchronous binary-search analog-to-digital converter (ADC) with reference range prediction. An original N-bit binary-search ADC requires 2N - 1 comparators while the proposed one only needs 2N - 1 ones. Compared to the (high speed, high power) flash ADC and (low speed, low power) successive approximation register ADC, the proposed architecture achieves the balanc... View full abstract»

• ### Characterization of Random Process Variations Using Ultralow-Power, High-Sensitivity, Bias-Free Sub-Threshold Process Sensor

Publication Year: 2010, Page(s):1838 - 1847
Cited by:  Papers (15)
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We propose a novel ultralow-power, high-sensitivity, bias-free sub-threshold process variation sensor for monitoring the random variations in the threshold voltage. The proposed sensor characterizes the threshold voltage mismatch between closely spaced, supposedly identical transistors using the exponential current-voltage relationship of sub-threshold operation. The sensitivity of the proposed se... View full abstract»

• ### The Transimpedance Limit

Publication Year: 2010, Page(s):1848 - 1856
Cited by:  Papers (46)  |  Patents (2)
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The transimpedance limit describes the maximum transimpedance that a transimpedance amplifier (TIA) can attain for a given bandwidth and technology. We analyze and compare this limit for a wide variety of TIA topologies thus exposing their relative merits. The topologies considered are the shunt-feedback TIA with single and multistage amplifier, the shunt-feedback TIA with feedback capacitor, the ... View full abstract»

• ### Practical Approach to Programmable Analog Circuits With Memristors

Publication Year: 2010, Page(s):1857 - 1864
Cited by:  Papers (259)  |  Patents (8)
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We suggest an approach to use memristors (resistors with memory) in programmable analog circuits. Our idea consists in a circuit design in which low voltages are applied to memristors during their operation as analog circuit elements and high voltages are used to program the memristor's states. This way, as it was demonstrated in recent experiments, the state of memristors does not essentially cha... View full abstract»

• ### Control of MEMS Vibration Modes With Pulsed Digital Oscillators: Part I—Theory

Publication Year: 2010, Page(s):1865 - 1878
Cited by:  Papers (13)
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The aim of this paper is to show that it is possible to excite selectively different mechanical resonant modes of a MEMS structure using pulsed digital oscillators (PDOs). This can be done by simply changing the working parameters of the oscillator, namely its sampling frequency or its feedback filter. A set of iterative maps is formulated to describe the evolution of the spatial modes between two... View full abstract»

• ### Control of MEMS Vibration Modes With Pulsed Digital Oscillators—Part II: Simulation and Experimental Results

Publication Year: 2010, Page(s):1879 - 1890
Cited by:  Papers (6)  |  Patents (2)
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This paper extends our previous work on the selective excitation of mechanical vibration modes in MEMS devices using pulsed digital oscillators (PDOs). It begins by presenting extensive simulation results using the set of iterative maps that model the system and showing that it is possible to activate two or three spatial modes (resonances) of the mechanical structure with a PDO. The second part o... View full abstract»

• ### Recombination of Envelope and Phase Paths in Wideband Polar Transmitters

Publication Year: 2010, Page(s):1891 - 1904
Cited by:  Papers (13)
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We investigate the recombination of discrete-time envelope and phase/frequency components of a polar transmitter, which is based here on an all-digital phase-locked loop (ADPLL) with wideband modulation capability and a digitally controlled power amplifier (DPA). A unified discrete/continuous-time analysis is introduced for the development of the interpolative transfer characteristics of the envel... View full abstract»

• ### Prediction of the Spectrum of a Digital Delta–Sigma Modulator Followed by a Polynomial Nonlinearity

Publication Year: 2010, Page(s):1905 - 1913
Cited by:  Papers (6)
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This paper presents a mathematical analysis of the power spectral density of the output of a nonlinear block driven by a digital delta-sigma modulator. The nonlinearity is a memoryless third-order polynomial with real coefficients. The analysis yields expressions that predict the noise floor caused by the nonlinearity when the input is constant. View full abstract»

• ### Analytical Phase-Noise Modeling and Charge Pump Optimization for Fractional-$N$ PLLs

Publication Year: 2010, Page(s):1914 - 1924
Cited by:  Papers (32)
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We present an analytical frequency-domain phase-noise model for fractional-N phase-locked loops (PLLs). The model includes the noise of the crystal reference, the reference input buffer, the voltage-controlled oscillator (VCO), the loop filter, charge pump (CP) device noise, and sigma-delta modulator (SDM) noise, including its effect on the in-band phase noise. The thermal device noise of t... View full abstract»

• ### Efficient Simulation of Weak Nonlinearities in Continuous-Time Oversampling Converters

Publication Year: 2010, Page(s):1925 - 1934
Cited by:  Papers (12)
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We propose a technique that enables the study of weak loop filter nonlinearities in a class of continuous-time delta-sigma modulators. The technique can easily be implemented in a tool intended to simulate discrete-time modulators with linear loop filters, thereby significantly reducing the simulation time. Thanks to this technique, the utility of the Schreier Delta-Sigma toolbox can be extended t... View full abstract»

• ### Theory of Flying-Adder Frequency Synthesizers—Part I: Modeling, Signals' Periods and Output Average Frequency

Publication Year: 2010, Page(s):1935 - 1948
Cited by:  Papers (31)  |  Patents (1)
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This is a rigorous mathematical theory of the operation of the flying-adder (FA) frequency synthesizer (also called direct digital period synthesizer). The paper consists of two parts: Part I presents a detailed mathematical model of the FA synthesizer, capturing the relationships between the properties of the FA's output and internal signals and the FA's parameters. The counting of the rising edg... View full abstract»

• ### Theory of Flying-Adder Frequency Synthesizers—Part II: Time- and Frequency-Domain Properties of the Output Signal

Publication Year: 2010, Page(s):1949 - 1963
Cited by:  Papers (26)  |  Patents (1)
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This is a rigorous mathematical theory of the operation of the flying-adder (FA) frequency synthesizer (also called direct digital period synthesizer). The paper consists of two parts. Part I presents a detailed mathematical model of the FA synthesizer, capturing the relationships between the properties of the FA's output and internal signals and the FA's parameters. The counting of the rising edg... View full abstract»

• ### Bandwidth Enhancement With Low Group-Delay Variation for a 40-Gb/s Transimpedance Amplifier

Publication Year: 2010, Page(s):1964 - 1972
Cited by:  Papers (39)
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A 40-Gb/s transimpedance amplifier (TIA) is proposed using multistage inductive-series peaking for low group-delay variation. A transimpedance limit for multistage TIAs is derived, and a bandwidth-enhancement technique using inductive-series π -networks is analyzed. A design method for low group delay constrained to 3-dB bandwidth enhancement is suggested. The TIA is implemented in a 0.13-&... View full abstract»

• ### Analysis and Design of an Ultralow-Power CMOS Relaxation Oscillator

Publication Year: 2010, Page(s):1973 - 1982
Cited by:  Papers (57)  |  Patents (7)
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This paper presents the design of a low-voltage ultralow-power relaxation oscillator without external components. The application field for this oscillator is the clock generation of low-power wake-up functions for battery-operated systems. A detailed analysis of the oscillator, including the temperature performance, is derived and verified with experimental results. The oscillator operates at a t... View full abstract»

• ### Available Energy and Passivity of First-Order LLTI One-Ports

Publication Year: 2010, Page(s):1983 - 1992
Cited by:  Papers (3)
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The energy behavior of first-order linear lumped time-invariant one-ports is thoroughly investigated, starting from the definition of available energy introduced by Wyatt in 1981 and exploiting the calculus of variations approach. First, all the extrema of the energy delivered from these components over finite time intervals are identified and evaluated. Then, available energy and passivity are in... View full abstract»

• ### A Wideband Inductorless LNA With Local Feedback and Noise Cancelling for Low-Power Low-Voltage Applications

Publication Year: 2010, Page(s):1993 - 2005
Cited by:  Papers (61)  |  Patents (2)
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A wideband noise-cancelling low-noise amplifier (LNA) without the use of inductors is designed for low-voltage and low-power applications. Based on the common-gate-common-source (CG-CS) topology, a new approach employing local negative feedback is introduced between the parallel CG and CS stages. The moderate gain at the source of the cascode transistor in the CS stage is utilized to boost the tra... View full abstract»

• ### Stability and Operation of Injection-Locked Regenerative Frequency Dividers

Publication Year: 2010, Page(s):2006 - 2019
Cited by:  Papers (2)
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Injection-locked regenerative frequency dividers can achieve a fractional division ratio similar to regenerative frequency dividers and can provide quadrature output phases. An analysis of the steady-state operation, stability, and phase noise of injection-locked regenerative frequency dividers is presented. In addition, two-stage ring oscillators (based on negative-resistance delay cells) are stu... View full abstract»

• ### Crosstalk Glitch Propagation Modeling for Asynchronous Interfaces in Globally Asynchronous Locally Synchronous Systems

Publication Year: 2010, Page(s):2020 - 2031
Cited by:  Papers (5)
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This paper characterizes the potentially catastrophic effect of crosstalk glitches on representative circuit implementations of two widely used asynchronous protocols. It is demonstrated that the crosstalk glitches can induce false events, which can undesirably propagate into asynchronous interface circuits and may cause system failure. Conventionally, to a circuit designer, glitch propagation (GP... View full abstract»

• ### Efficient Soft Error-Tolerant Adaptive Equalizers

Publication Year: 2010, Page(s):2032 - 2040
Cited by:  Papers (11)
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Soft errors are becoming an increasingly important issue for circuit reliability. Traditional techniques to protect against soft errors, like triple modular redundancy (TMR), have a large cost in terms of area and power. This has motivated the development of specific protection techniques for various types of circuits. In this paper, techniques to protect adaptive filters are presented, which prov... View full abstract»

• ### An Efficient Delay Model for MOS Current-Mode Logic Automated Design and Optimization

Publication Year: 2010, Page(s):2041 - 2052
Cited by:  Papers (18)
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MOS current-mode logic (MCML) is a low-noise alternative to CMOS logic. The lack of MCML automation tools, however, has deterred designers from applying MCML to complex digital functions. This paper presents an efficient MCML optimization program that can be used to properly size MCML gates. The delay model accuracy is adjusted by fitting measured gate delays by means of technology-dependent param... View full abstract»

• ### Ground-Bouncing-Noise-Aware Combinational MTCMOS Circuits

Publication Year: 2010, Page(s):2053 - 2065
Cited by:  Papers (28)
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Ground bouncing noise produced during the SLEEP to ACTIVE mode transitions is an important challenge in standard multithreshold CMOS (MTCMOS) circuits. The effectiveness of different noise-aware combinational MTCMOS circuit techniques to deal with the ground-bouncing-noise phenomenon is evaluated in this paper. An intermediate relaxation mode is investigated to gradually dump the charge stored on ... View full abstract»

• ### ULPFA: A New Efficient Design of a Power-Aware Full Adder

Publication Year: 2010, Page(s):2066 - 2074
Cited by:  Papers (27)
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In this paper, we first propose a new structure of a hybrid full adder, namely, the branch-based logic and pass-transistor (BBL-PT) cell, which we implemented by combining branch-based logic and pass-transistor logic. Evolution of the proposed cell from its original version to an ultralow-power (ULP) cell is described. Quantitative comparisons of the optimized version, namely, the ULP full adder (... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK