# IEEE Transactions on Circuits and Systems I: Regular Papers

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Displaying Results 1 - 25 of 42

Publication Year: 2010, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

Publication Year: 2010, Page(s): C2
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• ### Guest Editorial Special Section on Blind Signal Processing and Its Applications

Publication Year: 2010, Page(s):1401 - 1403
Cited by:  Papers (1)
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• ### Complex Blind Source Extraction From Noisy Mixtures Using Second-Order Statistics

Publication Year: 2010, Page(s):1404 - 1416
Cited by:  Papers (20)
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A class of second-order complex domain blind source extraction algorithms is introduced to cater for signals with noncircular probability distributions, which is a typical case in real-world scenarios. This is achieved by employing the so-called augmented complex statistics and based on the temporal structures of the sources, thus permitting widely linear (WL) predictability to be the extraction c... View full abstract»

• ### Complex Independent Component Analysis by Entropy Bound Minimization

Publication Year: 2010, Page(s):1417 - 1430
Cited by:  Papers (67)
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We first present a new (differential) entropy estimator for complex random variables by approximating the entropy estimate using a numerically computed maximum entropy bound. The associated maximum entropy distributions belong to the class of weighted linear combinations and elliptical distributions, and together, they provide a rich array of bivariate distributions for density matching. Next, we ... View full abstract»

• ### Real-Time Independent Vector Analysis for Convolutive Blind Source Separation

Publication Year: 2010, Page(s):1431 - 1438
Cited by:  Papers (16)
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Utilizing dependence over frequencies has shown significant excellence in tackling the frequency-domain blind source separation (BSS), which is also referred to as independent vector analysis (IVA). The IVA method then runs in offline batch processing, which is not well applicable to real-time systems. This paper proposes real-time BSS methods corresponding to that model. First, we derive online a... View full abstract»

• ### A Nonnegative Blind Source Separation Model for Binary Test Data

Publication Year: 2010, Page(s):1439 - 1448
Cited by:  Papers (7)
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A novel method called binNMF is introduced which aimed to extract hidden information from multivariate binary data sets. The method treats the problem in the spirit of blind source separation: The data are assumed to be generated by a superposition of several simultaneously acting sources or elementary causes which are not observable directly. The superposition process is based on a minimum of ass... View full abstract»

• ### A Matrix Pseudoinversion Lemma and Its Application to Block-Based Adaptive Blind Deconvolution for MIMO Systems

Publication Year: 2010, Page(s):1449 - 1462
Cited by:  Papers (4)
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The matrix inversion lemma gives an explicit formula of the inverse of a positive definite matrix A added to a block of dyads (represented as BBH) as follows: (A+BBH)-1= A-1- A-1B(I + BHA-1B)-1BHA-1.... View full abstract»

• ### Colored Subspace Analysis: Dimension Reduction Based on a Signal's Autocorrelation Structure

Publication Year: 2010, Page(s):1463 - 1474
Cited by:  Papers (6)
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Identifying relevant signals within high-dimensional observations is an important preprocessing step for efficient data analysis. However, many classical dimension reduction techniques such as principal component analysis do not take the often rich statistics of real-world data into account, and thereby fail if for example the signal space is of low power but meaningful in terms of some other stat... View full abstract»

• ### Blind Adaptive Equalization of MIMO Systems: New Recursive Algorithms and Convergence Analysis

Publication Year: 2010, Page(s):1475 - 1488
Cited by:  Papers (7)
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An adaptive (recursive in time) filtering method is proposed for blind deconvolution of multiple-input multiple-output (MIMO) channels modeled by an autoregressive moving average (ARMA) process. This method consists of two recursive schemes. The adaptive blind identification algorithm estimates the MIMO system impulse response. These estimates are then used in an adaptive Wiener-type filter to ext... View full abstract»

• ### Noise Estimation Using Mean Square Cross Prediction Error for Speech Enhancement

Publication Year: 2010, Page(s):1489 - 1499
Cited by:  Papers (8)
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This paper shows the feasibility of noise extraction from noisy speech and presents a two-stage approach for speech enhancement. The preproposed mean square cross prediction error (MSCPE) based blind source extraction algorithm is utilized to extract the additive noise from the noisy speech signal in the first stage. After that a modified spectral subtraction and a modified Wiener filter approach ... View full abstract»

• ### Background DAC Error Estimation Using a Pseudo Random Noise Based Correlation Technique for Sigma-Delta Analog-to-Digital Converters

Publication Year: 2010, Page(s):1500 - 1512
Cited by:  Papers (18)  |  Patents (3)
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This paper presents a new approach for estimating non-idealities in unit element feedback digital-to-analog converters of Sigma-Delta analog-to-digital converters. The presented method involves a background correlation technique to determine static and dynamic device mismatches causing linear time-invariant errors of the unit cells, as well as a way to digitally correct a modulator's output. Simul... View full abstract»

• ### An On-Chip-Trainable Gaussian-Kernel Analog Support Vector Machine

Publication Year: 2010, Page(s):1513 - 1524
Cited by:  Papers (27)
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An analog circuit architecture of Gaussian-kernel support vector machines having on-chip training capability has been developed. It has a scalable array processor configuration and the circuit size increases only in proportion to the number of learning samples. Thanks to the hardware-friendly algorithm employed in the present work, the learning function is realized by attaching a small additional ... View full abstract»

• ### Incremental Data Converters at Low Oversampling Ratios

Publication Year: 2010, Page(s):1525 - 1537
Cited by:  Papers (12)
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In this paper the use of incremental A/D converters with low oversampling ratios is investigated. Incremental A/D converters are able to achieve a higher SQNR than delta-sigma modulators at oversampling ratios below 4, allowing them to operate as higher bandwidth converters with medium resolution. The impact of removing the input S/H, as well as analyzing their behaviour at an OSR as low as 1 is e... View full abstract»

• ### Analytical Expression of Quantization Noise in Time-to-Digital Converter Based on the Fourier Series Analysis

Publication Year: 2010, Page(s):1538 - 1548
Cited by:  Papers (5)
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This paper describes a simple, analytical expression for quantization noise in a time-to-digital converter (TDC) based on Fourier-series analysis. We analyzed inverter propagation-delay variations due to fluctuations in the threshold voltage, and here we also discuss phase noise in an all-digital phase locked loop (ADPLL). The large standard deviation in the threshold voltage degrades phase noise ... View full abstract»

• ### A Built-In-Test Circuit for RF Differential Low Noise Amplifiers

Publication Year: 2010, Page(s):1549 - 1558
Cited by:  Papers (13)
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This paper presents an efficient, low-cost, built-in test (BIT) circuit for radio frequency differential low noise amplifiers (DLNAs). The BIT circuit detects amplitude alterations at the outputs of the DLNA, due to parametric or catastrophic faults, and provides a single digital Pass/Fail indication signal. A triple modular redundancy approach has been adopted for the BIT circuit design to avoid ... View full abstract»

• ### Circuit Approaches to Nonlinear-ISI Mitigation in Noise-Shaped Bandpass D/A Conversion

Publication Year: 2010, Page(s):1559 - 1572
Cited by:  Papers (9)
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This paper focuses on the analysis of nonlinear inter-symbol interference (ISI) in RF bandpass delta-sigma power digital-to-analog converters (DACs). Digital RF transmitters based on direct delta-sigma modulation have been proposed for efficient linear multi-functional radios. We show that a realistic one-bit DAC limits the linearity of such a transmitter. The linearity is discussed in terms of IS... View full abstract»

• ### A Fast and High-Precision VCO Frequency Calibration Technique for Wideband $Delta Sigma$ Fractional-N Frequency Synthesizers

Publication Year: 2010, Page(s):1573 - 1582
Cited by:  Papers (34)  |  Patents (11)
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A VCO frequency calibration technique suitable for a wideband fractional-N PLL is presented. It provides a fast and high-precision search for an optimal discrete tuning curve of an LC VCO during the coarse tuning process in a fractional-N PLL. A high-speed frequency error detector (FED) converts the VCO frequency to a digital value and computes the exact frequency difference from a target frequenc... View full abstract»

• ### General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space

Publication Year: 2010, Page(s):1583 - 1596
Cited by:  Papers (42)
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In this paper, a general and complete design flow for nanometer flip-flops (FFs) is presented. The proposed design methodology permits to optimize FFs under constraints within the energy-delay space through extensive adoption of the Logical Effort method, which also allows for defining the bounds in the design space search. Transistors sizing is rigorously discussed by referring to cases that occu... View full abstract»

• ### Understanding DC Behavior of Subthreshold CMOS Logic Through Closed-Form Analysis

Publication Year: 2010, Page(s):1597 - 1607
Cited by:  Papers (83)  |  Patents (1)
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In this paper, the DC behavior of subthreshold CMOS logic is analyzed in a closed form for the first time in the literature. To this aim, simplified large-signal and small-signal models of MOS transistors in subthreshold region are first developed. After replacing transistors with these equivalent models, analysis of the main DC parameters of CMOS logic gates is presented. In particular, the chang... View full abstract»

• ### On-Chip Support for NoC-Based SoC Debugging

Publication Year: 2010, Page(s):1608 - 1617
Cited by:  Papers (4)
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This paper presents a design-for-debug (DfD) technique for network-on-chip (NoC)-based system-on-chips (SoCs). We present a test wrapper and, a test and debug interface unit. They enable data transfer between a tester/debugger and a core-under-test (CUT) or -debug (CUD) through the available NoC to facilitate test and debug. We also present a novel core debug supporting logic to enable transaction... View full abstract»

• ### Synthesis-for-Testability Watermarking for Field Authentication of VLSI Intellectual Property

Publication Year: 2010, Page(s):1618 - 1630
Cited by:  Papers (16)  |  Patents (2)
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Most VLSI watermarking techniques do not allow different authorships of multiple Intellectual Property (IP) cores to be detected directly in the field after the IPs have been integrated, fabricated and packaged into chip. Watermark inserted at the design-for-testability (DfT) stage makes its direct detection after chip packaging possible, but it protects only the downstream placement-and-routing d... View full abstract»

• ### A Data Capturing Method for Buses on Chip

Publication Year: 2010, Page(s):1631 - 1641
Cited by:  Papers (5)
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In this paper, a new data reading technique for a bus of lines is proposed for fast operation. The proposed method utilizes multiple reference voltages available within a line's receiving logic and the initial conditions of wires in order to determine early and accurately the transmitted data of the current cycle. The presented technique does not require repeater insertion for reasonably long line... View full abstract»

• ### A $1/2 times {hbox {VDD}}$ to $3 times {hbox {VDD}}$ Bidirectional I/O Buffer With a Dynamic Gate Bias Generator

Publication Year: 2010, Page(s):1642 - 1653
Cited by:  Papers (12)  |  Patents (1)
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This paper presents a wide-range I/O buffer able to transmit and receive signals of 0.9/1.2/1.8/3.3/5.0 V by using a typical 0.18 μm CMOS process. The Dynamic gate bias circuit in the proposed I/O buffer is composed of two voltage converters, an EOS (Electrical Overstress) protector, and standard logic cells. A High voltage detector detects voltage level of VDDIO and then generates several ... View full abstract»

• ### Enhanced Scaling-Free CORDIC

Publication Year: 2010, Page(s):1654 - 1662
Cited by:  Papers (17)
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Coordinate Rotation DIgital Computer (CORDIC) rotator is a well known and widely used algorithm within computers due to its way of carrying out some calculations such as trigonometric functions, among others. A scale factor compensation inherent to the CORDIC algorithm becomes an important drawback when trying to improve its benefits, although some authors have come up with a new scaling-free vers... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK