IEEE Transactions on Circuits and Systems I: Regular Papers

Microfluidics-based biochips are revolutionizing high-throughput sequencing, parallel immunoassays, blood chemistry for clinical diagnostics, and drug discovery. These devices enable the precise control of nanoliter volumes of biochemical samples and reagents. They combine electronics with biology, and they integrate various bioassay operations, such as sample preparation, analysis, separation, an... View full abstract»

A voltage-controlled oscillator (VCO) based analog-to-digital converter (ADC) is a time-based architecture with a first-order noise-shaping property, which can be implemented using a VCO and digital circuits. This paper analyzes the performance of VCO-based ADCs in the presence of nonidealities such as jitter, nonlinearity, mismatch, and the metastability of D flip-flops. Based on this analysis, d... View full abstract»

Although R-2R ladders are commonly used as digital-to-analog converter (DAC) cores, complete equivalent circuits are still missing from the literature for most of the configurations used in practice. In this paper, expressions for the input and output impedances of R-2R ladders are derived for current- and voltage-mode operations. In addition, since many DACs use segmentation to reach higher resol... View full abstract»

Using behavioral models to perform fast simulation is currently a popular solution to verify SOC designs. Previous analog behavior modeling approaches often treat the noisy VDD waveform as a given input and focus on reflecting such stimuli on circuit performance. However, because the interaction of noise aggressors and victims is not considered, some error may exist while compared with ... View full abstract»

A SiGe BiCMOS mixed-signal adaptive controller-on-chip is presented that implements gradient descent of a supplied analog control objective. Eight analog variables controlling the external plant are perturbed in parallel using sinusoidal dithers, and their gradient components are estimated by parallel synchronous detection of the dithers in the control objective. Translinear all-NPN bipolar circui... View full abstract»

A comprehensive analysis of energy consumption for voltage-mode multilevel signals on a nanometer-technology bus is presented. A transition-dependent model is used which allows simplified calculation of the energy consumption. The accuracy of the approach is demonstrated using circuit simulations of three different electrical models of the bus, namely, lumped-C, distributed-RC, and distributed- RL... View full abstract»

In this paper the power consumption and operating frequency of true single phase clock (TSPC) and extended true single phase clock (E-TSPC) frequency prescalers are investigated. Based on this study a new low power and improved speed TSPC 2/3 prescaler is proposed which is silicon verified. Compared with the existing TSPC architectures the proposed 2/3 prescaler is capable of operating up to 5 GHz... View full abstract»

In advanced CMOS technologies where device mismatches are of major reliability concern, predicting the input-offset voltage of the sensing circuit is a crucial step in the design process as it has a direct impact on the yield. This work uses the Taylor expansion to derive a criterion to evaluate input-offset voltage of a latch-type voltage-mode sense amplifier. By innovatively setting the correct ... View full abstract»

In this paper, a method for the statistical design of the static-random-access-memory bit cell is proposed to ensure a high memory yield while meeting design specifications for performance, stability, area, and leakage. The method generates the nominal design parameters, i.e., the widths and lengths of the bit-cell transistors, which provide maximum immunity to the variations in a transistor's dim... View full abstract»

In this paper, we propose an improvement of the normalized min-sum (MS) decoding algorithm and novel MS decoder architectures with reduced word length using nonuniform quantization schemes for low-density parity-check (LDPC) codes. The proposed normalized MS algorithm introduces a more exact adjustment with two optimized correction factors for check-node-updating computations, while the convention... View full abstract»

Low-density parity-check (LDPC) codes are one of the most promising error-correcting codes approaching Shannon capacity and have been adopted in many applications. However, the efficient implementation of high-throughput LDPC decoders adaptable for various channel conditions still remains challenging. In this paper, a low-complexity reconfigurable VLSI architecture for high-speed LDPC decoders is ... View full abstract»

A programmable architecture is proposed for a flexi-mode quasi-cyclic low-density parity-check code decoder. The proposed architecture has the following advantages: 1) Code rate, length, and pattern can be programmed on the fly; 2) decoding complexity is reduced by algorithm modification; 3) memory read/write operation is reduced by access optimization and hierarchical memory structure; and 4) an ... View full abstract»

The analysis and synthesis parts of a cosine-modulated M-channel filterbank (FB) contain two sections, a modulation block and a prototype filter implemented in a polyphase structure. Although, in many cases, a linear-phase prototype filter is used, the coefficient symmetry of this filter is not utilized when using the existing polyphase structure. In this paper, a method is proposed for implementi... View full abstract»

A common component in digital circuitry for communication systems is the half-band filter. Digital half-band filters are often used in cooperation with upsamplers and downsamplers in multirate systems when a sampling-rate change is required. While techniques for designing these filters are well known, an entirely new method for the design and implementation of lowpass FIR half-band filters is pres... View full abstract»

Fault-tolerant adaptive filters (FTAFs) rely on inherent learning capabilities of the adaptive process to compensate for transient (soft) or permanent (hard) errors in the hardware implementation. In this paper, the use of the Walsh-Hadamard transform is first analyzed as a computationally efficient way of achieving adaptive fault tolerance, where a zero padding strategy is used to compensate for ... View full abstract»

The use of resonant injection-locked frequency dividers in frequency synthesizers has increased in recent years due to their lower power consumption compared to conventional digital prescalers. Numerous circuit ideas have been proposed, but there are few and sometimes contradictory estimates of the locking ranges (LRs) in these dividers. Despite several attempts, there is still no accurate analyti... View full abstract»

This paper presents a new phase-noise model for nonlinear microelectromechanical-system (MEMS) oscillators. Two widely recognized existing phase-noise models, namely, the linear time-invariant and time-variant models, are first reviewed, and their limitations on nonlinear MEMS oscillators are examined. A new phase-noise model for nonlinear MEMS oscillators is proposed according to the state-space ... View full abstract»

The application of a novel Takagi-Sugeno (TS) fuzzy-model-based approach to prohibit the onset of subharmonic instabilities in dc-dc power electronic converters is presented in this paper. The use of a model-based fuzzy approach derived from an average mathematical model to control the nonlinearities in power electronic converters has been reported in the literature, but this is known to act as a ... View full abstract»

This paper addresses the consensus problem of multiagent systems with a time-invariant communication topology consisting of general linear node dynamics. A distributed observer-type consensus protocol based on relative output measurements is proposed. A new framework is introduced to address in a unified way the consensus of multiagent systems and the synchronization of complex networks. Under thi... View full abstract»

With the ever increasing die sizes and the accompanied increase in the average global interconnect length, delay-optimal-routing and buffer-insertion techniques are significantly straining the power budget of modern ICs. To mitigate the impact of the power consumed by the interconnects and buffers, a power-efficient multipin routing technique is proposed in this paper. The problem is based on a gr... View full abstract»

Classical adjoint-sensitivity analysis provides an elegant framework to efficiently compute the first-order sensitivities of a few circuit performances with respect to many circuit parameters. However, the computed sensitivity qualities are incremental in nature, hence only reflecting the performance changes under small perturbations of circuit parameters. In this paper, we rigorously extend the c... View full abstract»

This paper presents a new hybrid nodal-mesh formulation of the equation systems of the 3-D partial element equivalent circuit (PEEC) method for the solution of combined electromagnetic and circuit (EM-CKT) problems. Traditional electromagnetic solution methods suffer from singularity of the system matrix due to the decoupling of the charge and currents at low frequencies. Based on the hypothesis t... View full abstract»