IEEE Transactions on Circuits and Systems I: Regular Papers

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Publication Year: 2009, Page(s):C1 - C4
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• IEEE Transactions on Circuits and Systems&mdash;I: Regular Papers publication information

Publication Year: 2009, Page(s): C2
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• Highly Linear Tunable CMOS $Gm{\hbox{-}}C$ Low-Pass Filter

Publication Year: 2009, Page(s):2145 - 2158
Cited by:  Papers (43)
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A comprehensive analysis of tunable transconductor topologies based on passive resistors is presented. Based on this analysis, a new CMOS transconductor is designed, which features high linearity, simplicity, and robustness against geometric and parametric mismatches. A novel tuning technique using just a MOS transistor in the triode region allows the adjustment of the transconductance in a wide r... View full abstract»

• Resonators in Open-Loop Sigma–Delta Modulators

Publication Year: 2009, Page(s):2159 - 2172
Cited by:  Papers (2)
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In this paper, we introduce the modulo resonator for use in analog-to-digitalopen-loop sigma-delta modulators(OLSDMs). The OLSDM presented in this paper is intended for use in high-accuracy (14-bit) high-speed analog-to-digital converters. The modulo resonator is used with a modulo notch filter to insert a zero in the noise transfer function at a nonzero frequency. The effect of finite gain... View full abstract»

• A Time-Variant Analysis of Fundamental$1/f^{3}$Phase Noise in CMOS Parallel$LC$-Tank Quadrature Oscillators

Publication Year: 2009, Page(s):2173 - 2180
Cited by:  Papers (18)
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This paper presents a rigorous time-variant analysis of the 1/f MOS device noise upconversion into 1/fphase noise for two of the most popular parallel-coupled quadrature CMOS harmonic oscillators. Simple closed-form equations for the fundamental 1/f3phase-noise spectrum are derived and validated through SpectreRF simulations, proving that the two topologies display remarkably dif... View full abstract»

• Theories, Analysis, and Bounds of the Finite-Support Approximation for the Inverses of Mixing-Phase FIR Systems

Publication Year: 2009, Page(s):2181 - 2194
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Inverse-system approximation using finite-impulse responses (FIR) is essential to a broad area of signal-processing applications. The conventional Wiener filtering techniques based on the least-square approach cannot provide an analytical framework simultaneously governing two crucial problems, namely, the selection of model order and the evaluation of asymptotical error bounds. In fact, the squar... View full abstract»

• Tunable FIR and IIR Fractional-Delay Filter Design and Structure Based on Complex Cepstrum

Publication Year: 2009, Page(s):2195 - 2206
Cited by:  Papers (7)
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A cepstrum-based approach is proposed to design finite- and infinite-impulse-response (IIR) fractional-delay (FD) filters. The maximal-flatness criteria on frequency responses are formulated as a system of linear equations to solve the truncated complex cepstrum. The closed-form solutions to cepstrum sequences can be derived. Moreover, it is very attractive that the resultant cepstrum coefficients... View full abstract»

• Generalized WLS Method for Designing All-Pass Variable Fractional-Delay Digital Filters

Publication Year: 2009, Page(s):2207 - 2220
Cited by:  Papers (36)
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This paper presents an optimal weighted least squares (WLS) method for designing low-complexity all-pass variable fractional-delay (VFD) digital filters. Instead of using a fixed range for the VFD parameter <i>p</i> and same-order constant-coefficient filters (subfilters), both the VFD parameter range <i>p</i> isin [<i>p</i> <sub>Min</sub>,<i>p... View full abstract»

• Design and Multiplierless Realization of Digital Synthesis Filters for Hybrid-Filter-Bank A/D Converters

Publication Year: 2009, Page(s):2221 - 2233
Cited by:  Papers (22)
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This paper studies the optimal least squares and minimax design and realization of digital synthesis filters for hybrid-filter-bank analog-to-digital converters (HFB ADCs) to meet a given spurious-free dynamic range (SFDR). The problem for designing finite-impulse-response synthesis filters is formulated as a second-order cone-programming problem, which is convex and allows linear and quadratic co... View full abstract»

• Time-Interleaved Analog-to-Digital-Converter Compensation Using Multichannel Filters

Publication Year: 2009, Page(s):2234 - 2247
Cited by:  Papers (42)  |  Patents (4)
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Published methods that employ a filter bank for compensating the timing and bandwidth mismatches of an M-channel time-interleaved analog-to-digital converter (TIADC) were developed based on the fact that each sub-ADC channel is a downsampled version of the analog input. The output of each sub-ADC is filtered in such a way that, when all the filter outputs are summed, the aliasing components are mi... View full abstract»

• Accurate Time-Domain Simulation of Continuous-Time Sigma–Delta Modulators

Publication Year: 2009, Page(s):2248 - 2258
Cited by:  Papers (4)
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In this paper, we present a methodology for the simulation of continuous-time (CT) sigma-delta converters. This method, based on a fixed-step algorithm, permits not only a time-domain simulation of the modulator output but also the simulation of intermediary signals. The method is based on the discretization of the CT models and the use of a discrete simulator such as Simulink, which is more effic... View full abstract»

• Effect of Mismatch on the Reliability of ON/OFF-Programmable CNNs

Publication Year: 2009, Page(s):2259 - 2269
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In this paper, the reliability of computation of ON/OFF-programmable cellular nonlinear networks (CNNs) is analyzed. This paper redefines the classical concept of robustness (tolerance to physical imperfections) in ON/OFF-programmable CNNs so that it can be used to predict the computation reliability of a physical realization. Also, a systematic approach to improve robustness is described, and gui... View full abstract»

• Fast and Efficient Search for All DC Solutions of PWL Circuits by Means of Oversized Polyhedra

Publication Year: 2009, Page(s):2270 - 2279
Cited by:  Papers (16)
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A fast and efficient method for finding all dc solutions of resistive piecewise linear (PWL) circuits is proposed. This method is based on the introduction of suitable polyhedra, denoted as oversized, surrounding a sequence of certain portions of PWL characteristics. Unlike the minimum-sized polyhedra introduced in the standard polyhedral method, these oversized polyhedra are characterized by simp... View full abstract»

• Projective Synchronization of Driving–Response Systems and Its Application to Secure Communication

Publication Year: 2009, Page(s):2280 - 2291
Cited by:  Papers (40)
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In this paper, we first introduce the model of single-driving double-response system (SDDRS), which consists of a driving system (subsystem) and two response systems (subsystems). By applying the theory of Lyapunov stability, we study the projective synchronization of SDDRS between the driving and response systems. The sufficient conditions for achieving projective synchronization are obtained whe... View full abstract»

• A Dynamic Circuit-Based Ferromagnetic Model

Publication Year: 2009, Page(s):2292 - 2300
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The development of a new dynamic circuit-based ferromagnetic model is described. The investigation of the behavior of a 24-gauge M19 silicon steel led to the conclusion that, for this material, a model that has static parameters is unable to accurately reproduce the behavior of the actual material over a large range of input frequencies and excitation levels without resorting to retuning the param... View full abstract»

• A Flexible DSP Architecture for MIMO Sphere Decoding

Publication Year: 2009, Page(s):2301 - 2314
Cited by:  Papers (29)
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This paper presents the architecture and circuit design of a sphere decoder for agile multi-input multi-output (MIMO) communication systems. Algorithm and architecture co-design is used to reduce hardware complexity, which enables the proposed sphere decoder to support larger antenna-array sizes and higher order modulations. The proposed architecture is also capable of processing multiple frequenc... View full abstract»

• Low-Latency Low-Complexity Architectures for Viterbi Decoders

Publication Year: 2009, Page(s):2315 - 2324
Cited by:  Papers (6)  |  Patents (1)
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Look-ahead techniques are applied in the nonlinear add-compare-select unit for achieving high throughput in Viterbi decoders. Multiple steps of the binary trellis are combined into an equivalent one-step complex trellis in time sequence, which is referred to as the branch metric precomputation (BMP). As the look-ahead level increases, the BMP dominates the complexity and delay of the overall syste... View full abstract»

• A Single-Chip 2.5-Gb/s CMOS Burst-Mode Optical Receiver

Publication Year: 2009, Page(s):2325 - 2331
Cited by:  Papers (7)
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This paper describes the design of a 2.5-Gb/s burst-mode optical receiver in a 0.18-mum CMOS process. A dual-gain-mode transimpedance amplifier (TIA) with constant damping factor control is proposed to tolerate a wide dynamic range input signal. By incorporating an automatic threshold tracking circuit (ATC), the TIA and limiting amplifier (LA) are dc coupled with feedforward offset cancellation. D... View full abstract»

• A Pseudodifferential Class AB DAC for Low-Power Wireless Transmitter

Publication Year: 2009, Page(s):2332 - 2340
Cited by:  Papers (2)  |  Patents (2)
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A low spurious 12-bit 122.88-MS/s digital-to-analog converter (DAC) enabling a low-power wireless transmit (Tx) chain is proposed and demonstrated. Pseudodifferential class AB DACs are introduced, and the benefits of using them in wireless Tx paths are discussed. The major power savings are achieved in multistage baseband Tx filters and upconversion mixers by using code-dependent linearly scaled d... View full abstract»

• A 60-GHz Phased Array Receiver Front-End in 0.13-$\mu {\hbox{m}}$ CMOS Technology

Publication Year: 2009, Page(s):2341 - 2352
Cited by:  Papers (16)
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This paper presents a fully integrated dual-antenna phased-array RF front-end receiver architecture for 60-GHz broadband wireless applications. It contains two differential receiver chains, each receiver path consists of an on-chip balun, agm-boosted current-reuse low-noise amplifier (LNA), a sub-harmonic dual-gate down-conversion mixer, an IF mixer, and a baseband gain stage. An active... View full abstract»

• Bang-Bang Control Class D Amplifiers: Total Harmonic Distortion and Supply Noise

Publication Year: 2009, Page(s):2353 - 2361
Cited by:  Papers (28)  |  Patents (1)
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The total harmonic distortion (THD) and the power supply noise, qualified by the power supply rejection ratio (PSRR) and by the power supply induced intermodulation distortion (PS-IMD), are recognized to be potential drawbacks of class D amplifiers. In this paper, analytical expressions for the THD, PSRR, and PS-IMD of the bang-bang control class D amplifier (bang-bang amp) are derived; the bang-b... View full abstract»

• Analysis and Design of Class DE Amplifier With Nonlinear Shunt Capacitances

Publication Year: 2009, Page(s):2362 - 2371
Cited by:  Papers (15)
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In this paper, equations for waveforms and design relationships are derived for class DE amplifiers with nonlinear shunt capacitances. Using the analytical waveform equations, it is shown that the nonlinearity of the shunt capacitances affects the waveforms only during the dead-time intervals. Additionally, the waveforms with nonlinear and linear shunt capacitances are not very different if class ... View full abstract»

• 2010 IEEE International Symposium on Circuits and Systems (ISCAS2010)

Publication Year: 2009, Page(s): 2372
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• IEEE Circuits and Systems Society Information

Publication Year: 2009, Page(s): C3
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Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK