# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 25 of 54

Publication Year: 2008, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems&mdash;I: Regular Papers publication information

Publication Year: 2008, Page(s): C2
| PDF (39 KB)
• ### Modeling, Evaluation, and Comparison of CRZ and RSD Redundant Architectures for Two-Step A/D Converters

Publication Year: 2008, Page(s):2445 - 2458
Cited by:  Papers (8)
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Redundancy in the output code as an instrument to reduce the impact of nonidealities in different architectures of two-step analog to digital converters (ADC) is investigated. The CRZ converters, which are the converters obtained from the conventional CR architecture with addition of Z extra decision levels, are formalized and compared with the RSD converter. Two distinct models are proposed to in... View full abstract»

• ### A 12-Bit Nonlinear DAC for Direct Digital Frequency Synthesis

Publication Year: 2008, Page(s):2459 - 2468
Cited by:  Papers (15)
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A 12-bit nonlinear digital-to-analog converter (DAC) was fabricated in a 0.35-mum SOI CMOS process. The nonlinear DAC can implement a piecewise-linear approximation to a sine function and results in significant reduction of complexity and power dissipation when used in direct digital frequency synthesizers (DDFSs). The DDFS look-up table only needs to store offset and gain values for each segment.... View full abstract»

• ### A Third-Order 9-Bit 10-MHz CMOS$\Delta \Sigma$Modulator With One Active Stage

Publication Year: 2008, Page(s):2469 - 2482
Cited by:  Papers (17)  |  Patents (1)
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We present a wideband architecture for DeltaSigma modulators using a single active stage and two switched capacitor passive stages. The mixed active-passive implementation has performance advantages over traditional switched-capacitor (SC) or continuous-time implementations, particularly for high-resolution, wideband applications with high sampling rates and moderate oversampling ratios. De... View full abstract»

• ### A Multiphase-Output Delay-Locked Loop With a Novel Start-Controlled Phase/Frequency Detector

Publication Year: 2008, Page(s):2483 - 2490
Cited by:  Papers (17)
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This paper presents a multiphase-output delay-locked loop (MODLL). The proposed phase/frequency detector (PFD) utilizes a new NAND-resettable dynamic D-flip-flop (DFF) circuit to achieve a shorter reset path. Thus, lower power consumption and higher speed can be obtained. The proposed voltage-controlled delay element used in this design can operate at a lower supply voltage and overcome the dead-b... View full abstract»

• ### A Novel Application of FM-ADC Toward the Self-Calibration of Phase-Locked Loops

Publication Year: 2008, Page(s):2491 - 2504
Cited by:  Papers (2)  |  Patents (1)
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This paper presents a charge pump-phase locked loop (CP-PLL) that utilizes a frequency-modulated analog-to-digital converter (FM-ADC) as part of a calibration circuit to compensate for process variations and intemperate operating environments. The calibration circuitry first detects the shift in operating conditions, and then dynamically adjusts the loop bandwidth back to its nominal range to guar... View full abstract»

• ### A 0.8-V 4.9-mW 1.2-GHz CMOS Fractional-N Frequency Synthesizer for UHF RFID Readers

Publication Year: 2008, Page(s):2505 - 2513
Cited by:  Papers (11)
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A fully integrated CMOS frequency synthesizer for UHF RFID reader is implemented in a 0.18-mum CMOS technology. Due to the large self-interference and the backscatter scheme of the passive tags, reader synthesizer's phase noise requirement is stringent to minimize the sensitivity degradation of the reader RX. The modified transformer feedback voltage-controlled oscillator (VCO) exhibits enhanced t... View full abstract»

• ### 10-Gb/s Inductorless CDRs With Digital Frequency Calibration

Publication Year: 2008, Page(s):2514 - 2524
Cited by:  Papers (12)  |  Patents (1)
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Two 10-Gb/s inductorless clock and data recovery (CDR) circuits using different gated digital-controlled oscillators (GDCO) are presented. A digital frequency calibration is adopted to save the power consumption and chip area. They have been fabricated in 0.18-mum CMOS process. By using the complementary gating technique, the first CDR circuit occupies an active area of 0.16 mm<sup>2</sup... View full abstract»

• ### Matrix Methods for the Dynamic Range Optimization of Continuous-Time$G_{m}$-$C$Filters

Publication Year: 2008, Page(s):2525 - 2538
Cited by:  Papers (6)
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This paper presents a synthesis procedure for the optimization of the dynamic range of continuous-time fully differentialGm-Cfilters. Such procedure builds up on a general extended state-space system representation which provides simple matrix algebra mechanisms to evaluate the noise and distortion performances of filters, as well as, the effect of amplitude and impedance ... View full abstract»

• ### Insights and Advances on the Design of CMOS <emphasis emphasistype="italic">Sinh</emphasis> Companding Filters

Publication Year: 2008, Page(s):2539 - 2550
Cited by:  Papers (27)
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The scope of this paper is to present certain insights and advances towards the synthesis and transistor-level implementation of high dynamic range (&gt; 120 dB), micropower, CMOS Sinh companding filters. In particular, we present detailed technical insights on a recently proposed Sinh integrator which may serve as the basic building block for higher-order filter structures. The particular int... View full abstract»

• ### Monolithic Resonant-Cantilever-Based CMOS Microsystem for Biochemical Sensing

Publication Year: 2008, Page(s):2551 - 2560
Cited by:  Papers (63)
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A resonant cantilever-based microsystem aimed at biochemical sensing is presented. The sensor system comprises a magnetically actuated resonant cantilever sensor array integrated with the feedback circuitry, digital control circuitry and a serial interface on a single chip in 0.8 mum CMOS technology. The sensor system shows a frequency stability of better than 3 Hz in water corresponding to a dete... View full abstract»

• ### A CMOS Image Sensor for Multi-Level Focal Plane Image Decomposition

Publication Year: 2008, Page(s):2561 - 2572
Cited by:  Papers (30)  |  Patents (1)
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An alternative image decomposition method that exploits prediction via nearby pixels has been integrated on the CMOS image sensor focal plane. The proposed focal plane decomposition is compared to the 2-D discrete wavelet transform (DWT) decomposition commonly used in state of the art compression schemes such as SPIHT and JPEG2000. The method achieves comparable compression performance with much l... View full abstract»

• ### An Electronically Tunable Linear or Nonlinear MOS Resistor

Publication Year: 2008, Page(s):2573 - 2583
Cited by:  Papers (18)  |  Patents (1)
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We present a bidirectional MOS resistor circuit that is electronically tunable and has zero dc offset. For a given I-V characteristic, the circuit senses the source-to-drain potential across an MOS device and automatically generates an appropriate bias for the gate terminal to implement the characteristic via negative feedback. We show that the I-V characteristic of the resistor can be designed to... View full abstract»

• ### A 1.2-GHz comparator with adaptable offset in 0.35-μm CMOS

Publication Year: 2008, Page(s):2584 - 2594
Cited by:  Papers (30)  |  Patents (1)
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We apply the technique of floating-gate differential injection to a 1.2-GHz CMOS comparator to achieve arbitrary, accurate, and adaptable offsets. The comparator uses nonvolatile charge storage on floating-gate nodes for either offset nulling or automatic programming of a desired offset. We utilize impact-ionized pFET hot-electron injection to achieve fully automatic offset programming. The design... View full abstract»

• ### Analysis and Design of an Efficient Irreversible Energy Recovery Logic in 0.18-$\mu$m CMOS

Publication Year: 2008, Page(s):2595 - 2607
Cited by:  Papers (25)
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This paper presents the design and experimental evaluation of a new type of irreversible energy recovery logic (ERL) families called complementary energy path adiabatic logic (CEPAL). It inherits the advantages of quasi-static ERL (QSERL) family, but is with improved driving ability and circuit robustness. The proposed logic style features no hold phase compared to its QSERL counterpart under the ... View full abstract»

• ### A Comprehensive Delay Model for CMOS CML Circuits

Publication Year: 2008, Page(s):2608 - 2618
Cited by:  Papers (24)
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MOS-transistor-based current-mode logic (CML)-type (MCML) circuits in high-speed circuit applications often operate as low-swing analog circuits rather than fully switched digital circuits. At these high-speed operations, the effect of the finite input signal slope on the delay of MCML gates significantly increases mainly due to incomplete current steering. Hence, for such cases, the conventional ... View full abstract»

• ### An overcomplete stitching algorithm for time decoding machines

Publication Year: 2008, Page(s):2619 - 2630
Cited by:  Papers (18)  |  Patents (4)
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We investigate a class of finite-dimensional time decoding algorithms that: (1) is insensitive with respect to the time-encoding parameters; (2) is highly efficient and stable; and (3) can be implemented in real time. These algorithms are based on the observation that the recovery of time encoded signals given a finite number of observations has the property that the quality of signal recovery is ... View full abstract»

• ### Post-Nonlinear Blind Extraction in the Presence of Ill-Conditioned Mixing

Publication Year: 2008, Page(s):2631 - 2638
Cited by:  Papers (9)
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An extension of blind source extraction (BSE) of one or a group of sources to the case of ill-conditioned and post-nonlinear (PNL) mixing is introduced. This is achieved by a ldquomixed objectiverdquo type of cost function which jointly maximizes the kurtosis of a recovered source and estimates a measure of nonlinearity within the mixing system. This helps to circumvent problems with existing BSE ... View full abstract»

• ### Acoustic Echo Cancellation Using a Pseudocoherence Function in the Presence of Memoryless Nonlinearity

Publication Year: 2008, Page(s):2639 - 2649
Cited by:  Papers (9)  |  Patents (1)
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Acoustic echo cancellation (AEC) is critical for telecommunication applications involving two or more locations such as teleconferencing. It is also challenging because of loudspeaker's nonlinearity, real-time implementation requirement, and multipath effects of indoor environments. This paper addresses the nonlinear AEC problem. We use a Hammerstein model to describe the memoryless nonlinearity o... View full abstract»

• ### Generalized Pascal Matrices, Inverses, Computations and Properties Using One-to-One Rational Polynomial <emphasis>s</emphasis>-<emphasis>z</emphasis> Transformations

Publication Year: 2008, Page(s):2650 - 2663
Cited by:  Papers (3)
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This paper proposes a one-to-one mapping between the coefficients of continuous-time (<i>s</i>-domain) and discrete-time (<i>z</i>-domain) IIR transfer functions such that the <i>s</i> -domain numerator/denominator coefficients can be uniquely mapped to the <i>z</i>-domain numerator/denominator coefficients. The one-to-one mapping provides a firm bas... View full abstract»

• ### Reduction in Sampling-Point Numbers for 2-D Discrete Fourier Transform Used in Harmonic Balance Method

Publication Year: 2008, Page(s):2664 - 2672
Cited by:  Papers (3)
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This paper discusses how to reduce the numbers of sampling points to obtain the 2-D discrete Fourier transform used in harmonic balance method. A method of embedding a 2-D Fourier transform into a 1-D one has already been proposed. This paper proposes a method of reducing the numbers of sampling points in a 1-D Fourier transform, by using bandpass sampling. A 2-D Fourier transform for harmonic bal... View full abstract»

• ### Eigenvalues and Singular Value Decompositions of Reduced Biquaternion Matrices

Publication Year: 2008, Page(s):2673 - 2685
Cited by:  Papers (4)
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In this paper, the algorithms for calculating the eigenvalues, the eigenvectors, and the singular value decompositions (SVD) of a reduced biquaternion (RB) matrix are developed. We use the SVD to approximate an RB matrix in the least square sense and define the pseudoinverse matrix of an RB matrix. Moreover, the RB SVD is employed to implement the SVD of a color image. The computational complexity... View full abstract»

• ### Computational Schemes for Warped DFT and Its Inverse

Publication Year: 2008, Page(s):2686 - 2695
Cited by:  Papers (4)
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Unlike discrete Fourier transform (DFT), warped DFT (WDFT) obtains nonuniformly spaced frequency samples based on an all-pass warping. WDFT finds applications in diverse fields, the most notable being audio processing. An explicit structure for the realization of WDFT and its generalized form, the overcomplete WDFT, is proposed in this work which leads to savings in the computational requirements ... View full abstract»

• ### A Generalized Window Approach for Designing Transmultiplexers

Publication Year: 2008, Page(s):2696 - 2706
Cited by:  Papers (20)
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This paper proposes a computational, very efficient, approach for designing a novel family of M-channel maximally decimated nearly perfect-reconstruction cosine-modulated transmultiplexers. This approach is referred to as the generalized windowing method for transmultiplexers because after knowing the transmission channel a proper weighted sum of the inter-channel and inter-symbol interferences ca... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK