# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 25 of 25

Publication Year: 2008, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems&mdash;I: Regular Papers publication information

Publication Year: 2008, Page(s): C2
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• ### Time-Domain Modeling of Low-Frequency Noise in Deep-Submicrometer MOSFET

Publication Year: 2008, Page(s):245 - 257
Cited by:  Papers (10)
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1/f noise and random telegraph signal (RTS) noise are increasingly dominant sources of low-frequency noise as the MOSFET enters the nanoscale regime. In this study, 1/f noise and RTS noise in the n-channel MOSFET are modelled in the time domain for efficient implementation in transient circuit simulation. A technique based on sum-of-sinusoids models 1/f noise while a Monte Carlo based technique is... View full abstract»

• ### A 40-MHz Double Differential-Pair CMOS OTA With$-{\hbox{60-dB}}$IM3

Publication Year: 2008, Page(s):258 - 265
Cited by:  Papers (22)
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A configuration of a linearized operational transconductance amplifier (OTA) for low-voltage and high-frequency applications is proposed. By using double pseudodifferential pairs and the source-degeneration structure under nano-scale CMOS technology, the nonlinearity caused by short channel effect from a small feature size can be minimized. A robust common-mode control system is designed for input... View full abstract»

• ### A Modified CFOA and Its Applications to Simulated Inductors, Capacitance Multipliers, and Analog Filters

Publication Year: 2008, Page(s):266 - 275
Cited by:  Papers (45)
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In this paper, using a minimum number of passive components, i.e., new grounded and floating inductance simulators, grounded capacitance multipliers, and frequency-dependent negative resistors (FDNRs) based on one/two modified current-feedback operational amplifiers (MCFOAs), are proposed. The type of the simulators depends on the passive element selection used in the structure of the circuit with... View full abstract»

• ### Negative Impedance Converter With Reduced Nonideal Gain and Parasitic Impedance Effects

Publication Year: 2008, Page(s):276 - 283
Cited by:  Papers (18)
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In this paper, two novel negative impedance converter (NIC) structures are proposed. One of the introduced NICs exhibits the property of both simultaneously reduced nonideal gain and parasitic impedance effects. Also, the other one shows the property of reducing only parasitic impedance effects and employs only second-generation current conveyors; accordingly, it can be realized with commercially ... View full abstract»

• ### On Analog Networks and Mixed-Domain Spatio-Temporal Frequency Response

Publication Year: 2008, Page(s):284 - 297
Cited by:  Papers (6)
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In this paper, we extend the linear cellular neural network (CNN) paradigm by introducing temporal derivative diffusion connections between neighboring cells. Our proposal results in an analog network topology for implementing general continuous-time discrete-space mixed-domain 3-D rational transfer functions for linear filtering. The network connections correspond one-to-one to the transfer funct... View full abstract»

• ### Synthesis of Nonseparable 3-D Spatiotemporal Bandpass Filters on Analog Networks

Publication Year: 2008, Page(s):298 - 310
Cited by:  Papers (6)
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Linear cellular neural networks (CNNs) are capable of performing efficient spatiotemporal filtering operations as recursive infinite impulse response (IIR) filters. Particularly, linear CNNs can be characterized as a spatial frequency-dependent recursive temporal filter with complex coefficients. Based on a modified version of the CNN paradigm recently proposed by the authors, nonseparable spatiot... View full abstract»

• ### Background Calibration With Piecewise Linearized Error Model for CMOS Pipeline A/D Converter

Publication Year: 2008, Page(s):311 - 321
Cited by:  Papers (18)  |  Patents (2)
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A new all-digital background calibration method, using a piecewise linear model to estimate the stage error pattern, is presented. The method corrects both linear and nonlinear errors. The proposed procedure converges in a few milliseconds and requires low hardware overhead, without the need of a high-capacity ROM or RAM. The calibration procedure is tested on a 0.6-mum CMOS pipeline analog-to-dig... View full abstract»

• ### On Modeling of Parallel Repeater-Insertion Methodologies for SoC Interconnects

Publication Year: 2008, Page(s):322 - 335
Cited by:  Papers (10)
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Parallel repeaters are proven to outperform serial repeaters in terms of delay, power and silicon area when regenerating signals in system-on-chip (SoC) interconnects. In order to avoid fundamental weaknesses associated with previously published parallel repeater-insertion models, this paper presents a new mathematical modeling for parallel repeater-insertion methodologies in SoC interconnects. Th... View full abstract»

• ### A Power-Delay Efficient Hybrid Carry-Lookahead/Carry-Select Based Redundant Binary to Two's Complement Converter

Publication Year: 2008, Page(s):336 - 346
Cited by:  Papers (14)
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This paper presents an efficient reverse converter for transforming the redundant binary (RB) representation into two's complement form. The hierarchical expansion of the carry equation for the reverse conversion algorithm creates a regular multilevel structure, from which a high-speed hybrid carry-lookahead/carry-select (CLA/CSL) architecture is proposed to fully exploit the redundancy of RB enco... View full abstract»

• ### Algorithms for a Sparse Reconfigurable Adaptive Filter and a Photonic Switch Architecture

Publication Year: 2008, Page(s):347 - 360
Cited by:  Papers (3)
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A nonblocking photonic switch can be used to implement a tapped delay line with a large number of adaptive weights and a wide range of time delays. An advantage of using optical tapped delay lines for adaptive filtering is that the operating frequency can be quite high, in the 10-100 GHz range. We present a sparse reconfigurable adaptive filter (SRAF) based on a photonic switch with an input/outpu... View full abstract»

• ### An All-Digital Fast-Locking Programmable DLL-Based Clock Generator

Publication Year: 2008, Page(s):361 - 369
Cited by:  Papers (24)  |  Patents (1)
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An all-digital fast-locking programmable DLL-based clock generator is presented. By resetting the output clock every two input clock periods, the initial minimal delay constraint in the conventional architecture is eliminated. Compared with the previous work, the short locking time is also achieved. The proposed circuit has been fabricated in 0.35-mum CMOS process and occupies the active area of 0... View full abstract»

• ### Analysis of Genomics and Proteomics Using DSP Techniques

Publication Year: 2008, Page(s):370 - 378
Cited by:  Papers (19)
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With the enormous amount of data that is available in the public domain, signal processing concepts are playing an important role in genomic and proteomic data processing. The binary sequence method is well known in the literature for genomic signal processing. As an alternative to the binary sequence method, this paper presents a new view to the genomic sequence processing with the electron-ion i... View full abstract»

• ### Optimized address assignment with array and loop transformations for minimizing schedule length

Publication Year: 2008, Page(s):379 - 389
Cited by:  Papers (5)
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Reducing address arithmetic operations by optimization of address offset assignment greatly improves the performance of digital signal processor (DSP) applications. However, minimizing address operations alone may not directly reduce code size and schedule length for DSPs with multiple functional units. Little research work has been conducted on loop optimization with address offset assignment pro... View full abstract»

• ### Compensation of Frequency-Dependent Gain/Phase Imbalance in Predistortion Linearization Systems

Publication Year: 2008, Page(s):390 - 397
Cited by:  Papers (62)  |  Patents (2)
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Impairments in the analog quadrature modulator can adversely impact the performance of a digital predistortion linearization system. In this paper, we focus on modeling and compensation of frequency-dependent gain/phase imbalance and dc offset when the input and output of the direct upconverter are available. We first propose channel models to describe the effects of these impairments on transmitt... View full abstract»

• ### Performance Analysis of Blind Adaptive MOE Multiuser Receivers Using Inverse QRD-RLS Algorithm

Publication Year: 2008, Page(s):398 - 411
Cited by:  Papers (11)
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The inverse QR (IQRD) recursive least-squares (RLS) algorithm (IQRD-RLS) is very popular because it has good numerical stability and can be mapped onto COordinate Rotation DIgital Computer (CORDIC) processor-based systolic arrays, which are suitable for very large-scale integrated circuits (VLSI) architecture and real-time applications. In this paper, the blind optimal minimum output energy (MOE) ... View full abstract»

• ### An Optimality-Based Repetitive Control Algorithm for Discrete-Time Systems

Publication Year: 2008, Page(s):412 - 423
Cited by:  Papers (13)
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In this paper, we first demonstrate that the zeroth-order hold discretization of a class of well-known continuous-time repetitive control algorithms can result in instability. Having highlighted the potential problem that discretization can pose to controller structures of this form, a new optimality-based repetitive control algorithm is developed for discrete-time systems. Under mild technical co... View full abstract»

• ### A Matrix Pseudo-Inversion Lemma for Positive Semidefinite Hermitian Matrices and Its Application to Adaptive Blind Deconvolution of MIMO Systems

Publication Year: 2008, Page(s):424 - 435
Cited by:  Papers (7)
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In the simplest case, the matrix inversion Lemma gives an explicit formula of the inverse of a positive-definite matrix A added to a rank-one matrix bb<sup>H</sup> as follows:(A + bb<sup>H</sup> )<sup>-1</sup> = A<sup>-1</sup>-A<sup>-1</sup> b(1 + b<sup>H</sup> A<sup>-1</sup>b)<sup>-1</sup>b<sup>H... View full abstract»

• ### Projection Operator-Based Factorization Procedure for FIR Paraunitary Matrices

Publication Year: 2008, Page(s):436 - 444
Cited by:  Papers (3)
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A constructive procedure for factoring a polynomial paraunitary matrix as a product of atomic paraunitary matrices is considered. The generic form of the paraunitary factors results from the use of projection matrices. In the univariate case, the factorization carried out in the -transform domain collapses to other univariate paraunitary matrix factorization methods. In the multivariate case, the ... View full abstract»

• ### A Tutorial on GrÖbner Bases With Applications in Signals and Systems

Publication Year: 2008, Page(s):445 - 461
Cited by:  Papers (34)
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This paper is a tutorial on Grobner bases and a survey on the applications of Grobner bases in the broad field of signals and systems. A reasonably detailed review is given of several fundamental theoretical issues that occur in the use of Grobner bases in multidimensional signals and systems applications. These topics include the primeness of multivariate polynomial matrices, multivariate unimodu... View full abstract»

• ### Available Transfer Capability Calculation Using a Smoothing Pointwise Maximum Function

Publication Year: 2008, Page(s):462 - 474
Cited by:  Papers (8)
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The determination of the available transfer capability (ATC) is formulated as a problem of finding the solution of a system of equations using the pointwise maximum function, which collapses all operating constraints of the system into one equation. The resulting equations are semismooth. The semismooth equations are solved by the use of a smoothing function. Two solution algorithms are presented.... View full abstract»

• ### IEEE Transactions on Circuits and Systems&mdash;I: Regular Papers Information for authors

Publication Year: 2008, Page(s): 475
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Publication Year: 2008, Page(s): 476
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• ### IEEE Circuits and Systems Society Information

Publication Year: 2008, Page(s): C3
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## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK