# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 25 of 32

Publication Year: 2007, Page(s):C1 - C4
| PDF (102 KB)
• ### IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

Publication Year: 2007, Page(s): C2
| PDF (37 KB)
• ### A Low-Power Programmable Bandpass Filter Section for Higher Order Filter Applications

Publication Year: 2007, Page(s):1165 - 1176
Cited by:  Papers (29)  |  Patents (1)
| | PDF (2348 KB) | HTML

We present a programmable, continuous-time bandpass filter that is extremely compact, power efficient, and can cover a wide range of frequencies (10 Hz-10 MHz). This capacitively coupled current conveyor (<i>C</i> <sup>4</sup>) has a second-order bandpass transfer function and is capable of being used as a basic bandpass-filter element to create high-order filters. The use ... View full abstract»

• ### Low-Power CMOS Rectifier Design for RFID Applications

Publication Year: 2007, Page(s):1177 - 1188
Cited by:  Papers (179)  |  Patents (3)
| | PDF (975 KB) | HTML

We investigate theoretical and practical aspects of the design of far-field RF power extraction systems consisting of antennas, impedance matching networks and rectifiers. Fundamental physical relationships that link the operating bandwidth and range are related to technology dependent quantities like threshold voltage and parasitic capacitances. This allows us to design efficient planar antennas,... View full abstract»

• ### Performance Analysis and Design of Triple-Resonance Interstage Peaking for Wide-Band Cascaded CMOS Amplifiers

Publication Year: 2007, Page(s):1189 - 1203
Cited by:  Papers (12)
| | PDF (1656 KB) | HTML

The analysis and design of the two promising candidates for interstage bandwidth enhancement of integrated wide-band cascaded amplifiers (CAs), namely series-shunt (SH) and shunt-series (HS) triple-resonance peaking, are presented. The principal operation of both peaking networks is described qualitatively in time-domain where the inherent bandwidth superiority of SH peaking is revealed. With the ... View full abstract»

• ### A Novel CMOS OTA Based on Body-Driven MOSFETs and its Applications in OTA-C Filters

Publication Year: 2007, Page(s):1204 - 1212
Cited by:  Papers (39)
| | PDF (1036 KB) | HTML

The operational transconductance amplifier (OTA) is one of the most significant building-blocks in integrated continuous-time filters. Traditional OTAs suffer linearity reduction as a result of the MOSFET scaling trend. In this paper, a body-driven (BD) CMOS triode-based fully balanced OTA is proposed to achieve low distortion and linear frequency tuning. In contrast to the gate-driven based OTAs ... View full abstract»

• ### A Robust and Fast Digital Background Calibration Technique for Pipelined ADCs

Publication Year: 2007, Page(s):1213 - 1223
Cited by:  Papers (23)  |  Patents (1)
| | PDF (524 KB) | HTML

This paper presents a background calibration scheme for pipelined analog-to-digital converters (ADCs) that is robust and has short calibration time. For a switched-capacitor (SC) pipeline stage, by splitting its input sampling capacitor, a random sequence can be injected into the ADC's signal path, and then calibration data can be extracted from the ADC's digital output without interrupting its no... View full abstract»

• ### Phase-Error Measurement and Compensation in PLL Frequency Synthesizers for FMCW Sensors—II: Theory

Publication Year: 2007, Page(s):1224 - 1235
Cited by:  Papers (8)  |  Patents (1)
| | PDF (1194 KB) | HTML

Synthesizers for the generation of frequency- or phase-modulated signals are required in communications, sensing, and many other fields and applications. The widespread use of phase-locked loops (PLLs) as major building blocks in current systems requires accurate models and methods for eliminating the influence of statistical and deterministic errors in the synthesized signals. We propose a novel ... View full abstract»

• ### Behavioral Modeling Methods for Switched-Capacitor $\Sigma \Delta$ Modulators

Publication Year: 2007, Page(s):1236 - 1244
Cited by:  Papers (28)
| | PDF (1130 KB) | HTML

Sigma-delta Modulators (SigmaDeltaMs) are cornerstone elements in oversampled analog-to-digital converters and digital-to-analog converters (DAC). Although transistor-level simulation is the most accurate approach known for these components, this method becomes impractical for complex systems due to its long computational time requirements. Behavioral modeling has become a viable solution to this ... View full abstract»

• ### RNS-to-Binary Converters for Two Four-Moduli Sets$\{2^{n}-1,2^{n},2^{n}+1,2^{{n}+1}-1\}$and$\{2^{n}-1,2^{n},2^{n}+1,2^{{n}+1}+1\}$

Publication Year: 2007, Page(s):1245 - 1254
Cited by:  Papers (64)
| | PDF (504 KB) | HTML

In this paper, reverse converters for two recently proposed four-moduli sets {2n- 1,2n,2n+ 1,2n+1 - 1} and {2n- 1, 2n, 2n+ 1, 2n+1 + 1} are described. The reverse conversion in the three-moduli set {2n- 1,2n,2n+ 1} has been optimized in literature. Hence, the proposed converters... View full abstract»

• ### Medium-Grain Cells for Reconfigurable DSP Hardware

Publication Year: 2007, Page(s):1255 - 1265
Cited by:  Papers (6)
| | PDF (472 KB) | HTML

Reconfigurable hardware contains an array of programmable cells and interconnection structures. Field-programmable gate arrays use fine-grain cells that implement simple logic functions. Some proposed reconfigurable architectures for digital signal processing (DSP) use coarse-grain cells that perform 16-b or 32-b operations. A third alternative is to use medium-grain cells with a word length of 4 ... View full abstract»

• ### A Scalable Wavelet Transform VLSI Architecture for Real-Time Signal Processing in High-Density Intra-Cortical Implants

Publication Year: 2007, Page(s):1266 - 1278
Cited by:  Papers (80)  |  Patents (12)
| | PDF (3458 KB) | HTML

This paper describes an area and power-efficient VLSI approach for implementing the discrete wavelet transform on streaming multielectrode neurophysiological data in real time. The VLSI implementation is based on the lifting scheme for wavelet computation using the symmlet4 basis with quantized coefficients and integer fixed-point data precision to minimize hardware demands. The proposed design is... View full abstract»

• ### Novel Power-Delay-Area-Efficient Approach to Generic Modular Addition

Publication Year: 2007, Page(s):1279 - 1292
Cited by:  Papers (21)
| | PDF (1333 KB) | HTML

Modular adders are fundamental arithmetic components typically employed in residue number system (RNS)-based digital signal processing (DSP) systems. They are widely used in modular multipliers and residue-to-binary converters and in implementing other residue arithmetic operations such as scaling. In this paper, a methodology for designing power-delay-area-efficient modular adders based on carry ... View full abstract»

• ### Simulation and Design of Nanocircuits With Resonant Tunneling Devices

Publication Year: 2007, Page(s):1293 - 1304
Cited by:  Papers (4)
| | PDF (1294 KB) | HTML

New nanotechnology-based devices are being researched to replace CMOS devices in order to overcome CMOS technology's scaling limitations. However, many such devices exhibit nonmonotonic I-V characteristics and uncertain properties which lead to the negative differential resistance (NDR) problem and the chaotic performance. This paper proposes two new circuit simulation approaches that can effectiv... View full abstract»

• ### Semi-Iterative Analog Turbo Decoding

Publication Year: 2007, Page(s):1305 - 1316
Cited by:  Papers (9)
| | PDF (1338 KB) | HTML

Based on multiple-slice turbo codes, a novel semi-iterative analog turbo decoding algorithm and its corresponding decoder architecture are presented. This work paves the way for integrating flexible analog decoders dealing with frame lengths over thousands of bits. The algorithm benefits from a partially continuous exchange of extrinsic information to improve decoding speed and correction performa... View full abstract»

• ### Pinning Complex Networks by a Single Controller

Publication Year: 2007, Page(s):1317 - 1326
Cited by:  Papers (647)
| | PDF (413 KB) | HTML

In this paper, without assuming symmetry, irreducibility, or linearity of the couplings, we prove that a single controller can pin a coupled complex network to a homogenous solution. Sufficient conditions are presented to guarantee the convergence of the pinning process locally and globally. An effective approach to adapt the coupling strength is proposed. Several numerical simulations are given t... View full abstract»

• ### Chaos-Based Spreading in DS-UWB Sensor Networks Increases Available Bit Rate

Publication Year: 2007, Page(s):1327 - 1339
Cited by:  Papers (47)
| | PDF (733 KB) | HTML

A chaos-based sequence generation method for reducing multiple access interference in direct sequence ultra-wide-band wireless-sensor networks (WSN) is presented. With this it is possible to increase the expected bit rate (BR) at which each user may transmit given a certain link quality, measured as the signal-to-interference ratio. When compared with traditional random sequences, chaos-based spre... View full abstract»

• ### A Systematic Approach to Bi-Directionally Nonlinearly Coupled Systems Design for the Generation of Complex Dynamical Behaviours

Publication Year: 2007, Page(s):1340 - 1347
Cited by:  Papers (4)
| | PDF (777 KB) | HTML

In this paper, a procedure to design a class of coupled systems that exhibit complex behaviours is presented. The proposed method is rigorously and systematically applicable to any dynamic system with nonlinear polynomial elements. Starting from two identical nonlinear algebraic systems, the proposed approach determines a proper bidirectional coupling that is able to force the coupled systems to e... View full abstract»

• ### FIR Variable Digital Filter With Signed Power-of-Two Coefficients

Publication Year: 2007, Page(s):1348 - 1357
Cited by:  Papers (16)
| | PDF (704 KB) | HTML

Variable digital filters (VDFs) are useful for various signal processing and communication applications where the frequency characteristics, such as fractional delays and cutoff frequencies, can be varied online. In this paper, we investigate the design of VDFs with discrete coefficients as a means of achieving low complexity and efficient hardware implementation. The filter coefficients are expre... View full abstract»

• ### A Discrete-Time Technique for the Steady-State Analysis of Nonlinear Class-E Amplifiers

Publication Year: 2007, Page(s):1358 - 1366
Cited by:  Papers (13)
| | PDF (584 KB) | HTML

Switched circuits are widely used, particularly for power electronic applications in which efficiency is important. Of these applications, the class-E amplifier has been given particular attention, since it is theoretically a 100%-efficient switched circuit that has been successfully demonstrated in applications such as ballasts, converters, frequency multipliers, and communication amplifiers at f... View full abstract»

• ### Characterization of Forced Vibration for Difference Inclusions: A Lyapunov Approach

Publication Year: 2007, Page(s):1367 - 1379
Cited by:  Papers (4)
| | PDF (569 KB) | HTML

A Lyapunov approach to the characterization of forced vibration for continuous-time systems was recently proposed in. The objective of this paper is to derive counterpart results for discrete-time systems. The class of oscillatory input signals to be considered include sinusoidal signals, multitone signals, and periodic signals which can be described as the output of an autonomous system. The Lyap... View full abstract»

• ### A Recursive Blind Adaptive Identification Algorithm and Its Almost Sure Convergence

Publication Year: 2007, Page(s):1380 - 1388
Cited by:  Papers (4)
| | PDF (561 KB) | HTML

This paper presents a novel blind adaptive identification algorithm based on least-squares type arguments. Parameter estimates are recursively updated with each output measurement, without resorting to any matrix inversion operation. It is proved that the parameter estimates converge almost surely (a.s.) toward a scalar multiple of the true parameters. Possible application of this algorithm to the... View full abstract»

• ### Off-Nominal Operation of Class-E Amplifier at Any Duty Ratio

Publication Year: 2007, Page(s):1389 - 1397
Cited by:  Papers (32)  |  Patents (1)
| | PDF (1836 KB) | HTML

Design equations for satisfying the suboptimum operating condition, i.e., only the zero-voltage switching (ZVS) condition, of a class-E amplifier with a linear shunt capacitance at any duty ratio are derived. By exploiting the suboptimum class-E operation, various amplifier parameters such as operating frequency, output power, load resistance, and component values can vary, while the ZVS operation... View full abstract»

• ### On Factor Prime Factorizations for $n$-D Polynomial Matrices

Publication Year: 2007, Page(s):1398 - 1405
Cited by:  Papers (10)
| | PDF (321 KB) | HTML

This paper investigates the problem of factor prime factorizations for n-D polynomial matrices and presents a criterion for the existence of factor prime factorizations for an important class of n-D polynomial matrices. As a by-product, we also obtain an algebraic algorithm to check n-D factor primeness in some important cases which partially solves the long-standing open problem of recognizing n-... View full abstract»

• ### Corrections to “Analysis and Design Strategy of UHF Micro-Power CMOS Rectifiers for Micro-Sensor and RFID Applications” [Jan 07 153-166]

Publication Year: 2007, Page(s): 1406
Cited by:  Papers (2)
| | PDF (57 KB) | HTML

In the above titled paper (ibid., vol. 54, no. 1, pp. 153-166, Jan 07), there were several errors in equations and a caption. The corrections are presented here. View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK