# IEEE Transactions on Circuits and Systems I: Regular Papers

Includes the top 50 most frequently accessed documents for this publication according to the usage statistics for the month of

• ### Full On-Chip CMOS Low-Dropout Voltage Regulator

Publication Year: 2007, Page(s):1879 - 1890
Cited by:  Papers (242)  |  Patents (14)
| | PDF (1617 KB) | HTML

This paper proposes a solution to the present bulky external capacitor low-dropout (LDO) voltage regulators with an external capacitorless LDO architecture. The large external capacitor used in typical LDOs is removed allowing for greater power system integration for system-on-chip (SoC) applications. A compensation scheme is presented that provides both a fast transient response and full range al... View full abstract»

• ### The flipped voltage follower: a useful cell for low-voltage low-power circuit design

Publication Year: 2005, Page(s):1276 - 1291
Cited by:  Papers (259)  |  Patents (3)
| | PDF (1168 KB) | HTML

In this paper, a basic cell for low-power and/or low-voltage operation is identified. It is evidenced how different versions of this cell, coined as "flipped voltage follower (FVF)" have been used in the past for many applications. A detailed classification of basic topologies derived from the FVF is given. In addition, a comprehensive list of recently proposed low-voltage/low-power CMOS circuits ... View full abstract»

• ### Time Domain Processing Techniques Using Ring Oscillator-Based Filter Structures

Publication Year: 2017, Page(s):3003 - 3012
| | PDF (2197 KB) | HTML

The ability to process time-encoded signals with high fidelity is becoming increasingly important for the time domain (TD) circuit techniques that are used at the advanced nanometer technology nodes. This paper proposes a compact oscillator-based subsystem that performs precise filtering of asynchronous pulse-width modulation encoded signals and makes extensive use of digital logic, enabling low-v... View full abstract»

• ### Simplified Unified Analysis of Switched-RC Passive Mixers, Samplers, and $N$ -Path Filters Using the Adjoint Network

Publication Year: 2017, Page(s):2714 - 2725
| | PDF (2173 KB) | HTML

Recent innovations in software defined CMOS radio transceiver architectures heavily rely on high-linearity switched-RC sampler and passive-mixer circuits, driven by digitally programmable multiphase clocks. Although seemingly simple, the frequency domain analysis of these linear periodically time variant (LPTV) circuits is often deceptively complex. This paper uses the properties of sampled LPTV s... View full abstract»

• ### Efficient Hardware Architectures for Deep Convolutional Neural Network

Publication Year: 2018, Page(s):1941 - 1953
| | PDF (1975 KB) | HTML

Convolutional neural network (CNN) is the state-of-the-art deep learning approach employed in various applications. Real-time CNN implementations in resource limited embedded systems are becoming highly desired recently. To ensure the programmable flexibility and shorten the development period, field programmable gate array is appropriate to implement the CNN models. However, the limited bandwidth... View full abstract»

• ### Consensus of Multiagent Systems and Synchronization of Complex Networks: A Unified Viewpoint

Publication Year: 2010, Page(s):213 - 224
Cited by:  Papers (891)
| | PDF (1045 KB) | HTML

This paper addresses the consensus problem of multiagent systems with a time-invariant communication topology consisting of general linear node dynamics. A distributed observer-type consensus protocol based on relative output measurements is proposed. A new framework is introduced to address in a unified way the consensus of multiagent systems and the synchronization of complex networks. Under thi... View full abstract»

• ### Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures

Publication Year: 2008, Page(s):1441 - 1454
Cited by:  Papers (103)  |  Patents (2)
| | PDF (1188 KB) | HTML

The need for highly integrable and programmable analog-to-digital converters (ADCs) is pushing towards the use of dynamic regenerative comparators to maximize speed, power efficiency and reconfigurability. Comparator thermal noise is, however, a limiting factor for the achievable resolution of several ADC architectures with scaled supply voltages. While mismatch in these comparators can be compens... View full abstract»

• ### Switched-Capacitor/Switched-Inductor Structures for Getting Transformerless Hybrid DC–DC PWM Converters

Publication Year: 2008, Page(s):687 - 696
Cited by:  Papers (417)  |  Patents (1)
| | PDF (1294 KB) | HTML

A few simple switching structures, formed by either two capacitors and two-three diodes (C-switching), or two inductors and two-three diodes (L-switching) are proposed. These structures can be of two types: ldquostep-downrdquo and ldquostep-up.rdquo These blocks are inserted in classical converters: buck, boost, buck-boost, Cuk, Zeta, Sepic. The ldquostep-downrdquo C- or L-switching structures can... View full abstract»

• ### A Pulse Frequency Modulation Interpretation of VCOs Enabling VCO-ADC Architectures With Extended Noise Shaping

Publication Year: 2018, Page(s):444 - 457
| | PDF (3643 KB) | HTML

In this paper, we propose to study voltage controlled oscillators (VCOs) based on the equivalence with pulse frequency modulators (PFMs). This approach is applied to the analysis of VCO-based analog-to-digital converters (VCO-ADCs) and deviates significantly from the conventional interpretation, where VCO-ADCs have been described as the first-order ΔΣ modulators. A first advantage of... View full abstract»

• ### Analysis and Background Self-Calibration of Comparator Offset in Loop-Unrolled SAR ADCs

Publication Year: 2018, Page(s):458 - 470
| | PDF (2811 KB) | HTML

In conventional charge redistribution successive approximation register (SAR) ADCs that use a single comparator, the comparator offset causes no distortion but a dc shift in the transfer curve. In loop-unrolled (LU) SAR ADCs, on the other hand, mismatched comparator offset voltages introduce input-level-dependent errors to the conversion result, which deteriorates the linearity and limits the reso... View full abstract»

• ### A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS

Publication Year: 2018, Page(s):2109 - 2117
| | PDF (3261 KB) | HTML

This paper presents a PLL supporting diverse low-power clocking needs including wide input (6-200 MHz) and output (0.15-5 GHz) frequency ranges and SSC operation. Fabricated in 14nm FinFET CMOS, a low-power switched-cap loop filter is employed to enable high -3dB PLL bandwidth (>40% of fREF = 19.2 MHz), and the proposed reference current generator (IrefGen) provides accurate current ... View full abstract»

• ### Homeostatic Fault Tolerance in Spiking Neural Networks: A Dynamic Hardware Perspective

Publication Year: 2018, Page(s):687 - 699
| | PDF (2824 KB) | HTML

Fault tolerance is a remarkable feature of biological systems and their self-repair capability influence modern electronic systems. In this paper, we propose a novel plastic neural network model, which establishes homeostasis in a spiking neural network. Combined with this plasticity and the inspiration from inhibitory interneurons, we develop a fault-resilient robotic controller implemented on an... View full abstract»

• ### Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey

Publication Year: 2011, Page(s):1 - 21
Cited by:  Papers (95)  |  Patents (7)
| | PDF (1691 KB) | HTML

This paper presents a tutorial overview of ΣΔ modulators, their operating principles and architectures, circuit errors and models, design methods, and practical issues. A review of the state of the art on nanometer CMOS implementations is described, giving a survey of cutting-edge ΣΔ architectures, with emphasis on their application to the next generation of wireless te... View full abstract»

• ### Low $1/f^{3}$ Phase Noise Quadrature LC VCOs

Publication Year: 2018, Page(s):2127 - 2138
| | PDF (2475 KB) | HTML

Series-coupled quadrature LC voltage-controlled oscillators(SQVCOs) perform robustly over a wide tuning range, but have a higher 1/f3 phase noise than their single-phase counterparts. Switching transistors inject noise into the tank only once per cycle leading to an asymmetric impulse sensitivity function(ISF) and large flicker noise upconversion. Circuit topologies with additional capa... View full abstract»

• ### A 2.1-GHz Third-Order Cascaded PLL With Sub-Sampling DLL and Clock-Skew-Sampling Phase Detector

Publication Year: 2018, Page(s):2118 - 2126
| | PDF (2502 KB) | HTML

A high-order cascaded phase-locked loop (PLL) architecture using a sub-sampling delay-locked loop (DLL) is proposed to break the tradeoff between the loop bandwidth and the number of integrator in the feedback loop without significantly degrading the settling time or reference spur. A clock-skew-sampling phase detector is also proposed to extend the stable detection range of the sub-sampling phase... View full abstract»

• ### A Low-Power NB-IoT Transceiver With Digital-Polar Transmitter in 180-nm CMOS

Publication Year: 2017, Page(s):2569 - 2581
| | PDF (4584 KB) | HTML

A fully integrated 750~960 MHz wireless transceiver (TRX) is presented for single-tone NB-IoT applications. Effective design methodologies and techniques, from the system level to circuit level, are proposed to address various design challenges while achieving low-power consumption. The TRX consists of a low-IF receiver with 180-kHz signal bandwidth, a digital polar transmitter with 3.75-kHz signa... View full abstract»

• ### High-Efficiency Charge Pumps for Low-Power On-Chip Applications

Publication Year: 2018, Page(s):1143 - 1153
| | PDF (2501 KB) | HTML

This paper proposes charge pumps with improved power efficiency suitable for low-power on-chip applications. Undesired charge transfer, which has a direction opposite to that of the intended current flow, presents a significant source of power loss in charge pumps. The proposed charge pump circuit utilizes charge transfer switches with a complementary branch scheme to significantly reduce undesire... View full abstract»

• ### A High-Precision Resistor-Less CMOS Compensated Bandgap Reference Based on Successive Voltage-Step Compensation

Publication Year: 2018, Page(s):1 - 11
| | PDF (2548 KB)

A curvature-compensated resistor-less bandgap reference (BGR), which is fabricated in 0.5-μm CMOS process, is proposed in this paper. The BGR utilizes successive voltage-step compensation to produce a temperature-insensitive voltage reference (VR), including one ΔVGS step for first-order compensation and another one for higher order curvature correction. Moreover, a supply noise bypa... View full abstract»

• ### Kron Reduction of Graphs With Applications to Electrical Networks

Publication Year: 2013, Page(s):150 - 163
Cited by:  Papers (117)
| | PDF (3757 KB) | HTML

Consider a weighted undirected graph and its corresponding Laplacian matrix, possibly augmented with additional diagonal elements corresponding to self-loops. The Kron reduction of this graph is again a graph whose Laplacian matrix is obtained by the Schur complement of the original Laplacian matrix with respect to a specified subset of nodes. The Kron reduction process is ubiquitous in classic ci... View full abstract»

• ### An Architecture to Accelerate Convolution in Deep Neural Networks

Publication Year: 2018, Page(s):1349 - 1362
| | PDF (3035 KB) | HTML

In the past few years, the demand for real-time hardware implementations of deep neural networks (DNNs), especially convolutional neural networks (CNNs), has dramatically increased, thanks to their excellent performance on a wide range of recognition and classification tasks. When considering real-time action recognition and video/image classification systems, latency is of paramount importance. T... View full abstract»

• ### Memristor-Based Circuit Design for Multilayer Neural Networks

Publication Year: 2018, Page(s):677 - 686
| | PDF (2210 KB) | HTML

Memristors are promising components for applications in nonvolatile memory, logic circuits, and neuromorphic computing. In this paper, a novel circuit for memristor-based multilayer neural networks is presented, which can use a single memristor array to realize both the plus and minus weight of the neural synapses. In addition, memristor-based switches are utilized during the learning process to u... View full abstract»

• ### Analysis and Design of the Classical CMOS Schmitt Trigger in Subthreshold Operation

Publication Year: 2017, Page(s):869 - 878
Cited by:  Papers (1)
| | PDF (3050 KB) | HTML

In this paper, the classical CMOS Schmitt trigger (ST) operating in the subthreshold regime is analyzed. The complete DC voltage transfer characteristic of the CMOS ST is determined. The metastable segment of the characteristic is explained in terms of the negative resistance of the NMOS and PMOS subcircuits of the ST. Small-signal analysis is carried out to determine the minimum supply voltage at... View full abstract»

• ### The Circuit Theory Behind Coupled-Mode Magnetic Resonance-Based Wireless Power Transmission

Publication Year: 2012, Page(s):2065 - 2074
Cited by:  Papers (164)
| | PDF (2999 KB) | HTML

Inductive coupling is a viable scheme to wirelessly energize devices with a wide range of power requirements from nanowatts in radio frequency identification tags to milliwatts in implantable microelectronic devices, watts in mobile electronics, and kilowatts in electric cars. Several analytical methods for estimating the power transfer efficiency (PTE) across inductive power transmission links ha... View full abstract»

• ### Analysis and Design of Voltage-Controlled Oscillator Based Analog-to-Digital Converter

Publication Year: 2010, Page(s):18 - 30
Cited by:  Papers (94)  |  Patents (5)
| | PDF (1424 KB) | HTML

A voltage-controlled oscillator (VCO) based analog-to-digital converter (ADC) is a time-based architecture with a first-order noise-shaping property, which can be implemented using a VCO and digital circuits. This paper analyzes the performance of VCO-based ADCs in the presence of nonidealities such as jitter, nonlinearity, mismatch, and the metastability of D flip-flops. Based on this analysis, d... View full abstract»

• ### Consensus Tracking of Multi-Agent Systems With Lipschitz-Type Node Dynamics and Switching Topologies

Publication Year: 2014, Page(s):499 - 511
Cited by:  Papers (271)
| | PDF (3732 KB) | HTML

Distributed consensus tracking is addressed in this paper for multi-agent systems with Lipschitz-type node dynamics. The main contribution of this work is solving the consensus tracking problem without the assumption that the topology among followers is strongly connected and fixed. By using tools from M-matrix theory, a class of consensus tracking protocols based only on the relative states among... View full abstract»

• ### A Cost-Effective Adaptive Rectifier for Low Power Loosely Coupled Wireless Power Transfer Systems

Publication Year: 2018, Page(s):2318 - 2329
| | PDF (3679 KB) | HTML

This paper introduces an integrated receiver circuit based on a full-wave adaptive rectifier (AR). It achieves complex impedance matching and enables complexity and cost reduction in resonant wireless power transfer (WPT) systems. The conversion and system efficiency based on this AR receiver are theoretically compared with other receiver architectures by using a WPT system model including all con... View full abstract»

• ### A Novel Digital-Intensive Hybrid Polar-I/Q RF Transmitter Architecture

Publication Year: 2018, Page(s):1 - 14
| | PDF (4103 KB)

A novel digital-intensive hybrid transmitter (TX) architecture is presented, combining conventional inphase and quadrature (I/Q) with constrained phase modulation. The proposed architecture utilizes an RF-DAC with phase modulated RF clock and adjusted I/Q components. By incorporating phase modulation the quadrature component is kept small while the inphase component approaches the complex signal e... View full abstract»

• ### A frequency compensation scheme for LDO voltage regulators

Publication Year: 2004, Page(s):1041 - 1050
Cited by:  Papers (154)  |  Patents (7)
| | PDF (576 KB) | HTML

A stable low dropout (LDO) voltage regulator topology for low equivalent series resistance (ESR) capacitive loads is presented. The proposed scheme generates a zero internally instead of relying on the zero generated by the load capacitor and its ESR combination for stability. It is demonstrated that this scheme realizes robust frequency compensation, facilitates the use of multilayer ceramic capa... View full abstract»

• ### An Oversampling Stochastic ADC Using VCO-Based Quantizers

Publication Year: 2018, Page(s):1 - 14
| | PDF (7688 KB)

An oversampling stochastic analog-to-digital converter is presented. This stochastic converter spatially averages quantization errors in multiple voltage-controlled oscillator (VCO)-based quantizers. Unlike other stochastic converters, this proposed architecture does not require an inverse Gaussian cumulative density function estimator. The digital adder becomes an ideal estimator due to uncorrela... View full abstract»

• ### A 14-ENOB Delta-Sigma-Based Readout Architecture for ECoG Recording Systems

Publication Year: 2018, Page(s):1 - 11
| | PDF (2747 KB)

This paper presents a delta-sigma based readout architecture targeting electrocortical recording in brain stimulation applications. The proposed architecture can accurately record a peak input signal up to 240 mV in a power-efficient manner without saturating or employing offset rejection techniques. The readout architecture consists of a delta-sigma modulator with an embedded analog front-end. Th... View full abstract»

• ### Comprehensive Analysis of Distortion in the Passive FET Sample-and-Hold Circuit

Publication Year: 2018, Page(s):1157 - 1173
| | PDF (7127 KB) | HTML

Analysis simplified with circuit insights reveals the major sources of distortion in a passive FET-switch-based sampling circuit: 1) $R_{mathrm{scriptscriptstyle ON}}$ -modulation; 2) turn-OFF-time instant; and 3) signal-dependent charge-injection. Explicit expressions for second- and third-order distortions advance intuitive understanding of the processes of distortion. Circuit simulations and me... View full abstract»

• ### Design of an On-Silicon-Interposer Passive Equalizer for Next Generation High Bandwidth Memory With Data Rate Up To 8 Gb/s

Publication Year: 2018, Page(s):2293 - 2303
| | PDF (7874 KB) | HTML

In this paper, we propose a new on-silicon-interposer passive equalizer for next generation high bandwidth memory (HBM) with 1024 I/O lines and 8-Gb/s data transmission, which is four times higher than the data rate of HBM generation 2. The proposed equalizer meets the three requirements for the implementation of ultra-high bandwidth interface with wide I/O lines: 1) small area; 2) fine pitch; and... View full abstract»

• ### A Reconfigurable Streaming Deep Convolutional Neural Network Accelerator for Internet of Things

Publication Year: 2018, Page(s):198 - 208
| | PDF (2922 KB) | HTML

Convolutional neural network (CNN) offers significant accuracy in image detection. To implement image detection using CNN in the Internet of Things (IoT) devices, a streaming hardware accelerator is proposed. The proposed accelerator optimizes the energy efficiency by avoiding unnecessary data movement. With unique filter decomposition technique, the accelerator can support arbitrary convolution w... View full abstract»

• ### A Sub-1ppm/°C Current-Mode CMOS Bandgap Reference With Piecewise Curvature Compensation

Publication Year: 2018, Page(s):904 - 913
| | PDF (3669 KB) | HTML

This paper presents a low temperature coefficient (TC) CMOS BGR for high-performance multi-channel analog-to-digital converter (ADC) working under wide temperature range. Besides the logarithmic compensation, both leakage and piecewise curvature compensation are implemented to extend its operating temperature range and keep its low TC. A β-compensation technique is used to cancel the PTAT a... View full abstract»

• ### Degradation of Alias Rejection in Continuous-Time Delta-Sigma Modulators by Weak Loop-Filter Nonlinearities

Publication Year: 2018, Page(s):1 - 9
| | PDF (2023 KB)

Implicit anti-aliasing is a remarkable property of continuous-time delta-sigma modulators employing a time-invariant loop filter. It turns out that weak nonlinearity of the operational transconductance amplifier (OTA) used in the input integrator, in conjunction with the DAC pulse shape and OTA parasitics can greatly degrade the alias rejection of the modulator. The authors report and analyze this... View full abstract»

• ### Wideband Inductorless Low-Power LNAs with Gm Enhancement and Noise-Cancellation

Publication Year: 2018, Page(s):26 - 38
| | PDF (3641 KB) | HTML

Two inductorless low-power differential low-noise amplifiers (LNAs) are designed for multiband wireless communication applications. Both LNAs are based on the combination of common-gate (CG) and shunt feedback topologies. In the first LNA, the cross-coupled push-pull structure with separated bias for nMOS and pMOS CG transistors is utilized to realize gm enhancement, partial noise cancellation, an... View full abstract»

• ### A Two-Stage Fully Differential Inverter-Based Self-Biased CMOS Amplifier With High Efficiency

Publication Year: 2011, Page(s):1591 - 1603
Cited by:  Papers (36)  |  Patents (1)
| | PDF (1735 KB) | HTML

A two-stage fully differential CMOS amplifier comprising inverters as input structures and employing self-biasing techniques is presented. The proposed amplifier benefits from an optimum compensation through time-domain optimization which permits achieving high energy efficiency. Moreover, it achieves the highest efficiency of its class and although it relies on a quasi-class-A topology, it is com... View full abstract»

• ### An Efficient Bayesian Optimization Approach for Automated Optimization of Analog Circuits

Publication Year: 2018, Page(s):1954 - 1967
| | PDF (2849 KB) | HTML

The computation-intensive circuit simulation makes the analog circuit sizing challenging for large-scale/complicated analog/RF circuits. A Bayesian optimization approach has been proposed recently for the optimization problems involving the evaluations of black-box functions with high computational cost in either objective functions or constraints. In this paper, we propose a weighted expected imp... View full abstract»

• ### High-Efficiency Wireless Power Transfer for Biomedical Implants by Optimal Resonant Load Transformation

Publication Year: 2013, Page(s):867 - 874
Cited by:  Papers (82)
| | PDF (1382 KB) | HTML

Wireless power transfer provides a safe and robust way for powering biomedical implants, where high efficiency is of great importance. A new wireless power transfer technique using optimal resonant load transformation is presented with significantly improved efficiency at the cost of only one additional chip inductor component. The optimal resonant load condition for the maximized power transfer e... View full abstract»

• ### A 76–84 GHz CMOS $4times$ Subharmonic Mixer With Internal Phase Correction

Publication Year: 2018, Page(s):2083 - 2096
| | PDF (3513 KB) | HTML

A CMOS 4× subharmonic mixer (SHM) with an internal phase error correction mechanism operating at mm-wave frequencies is proposed in this paper. The SHM operates with a 81-GHz RF input signal and a 20-GHz local oscillator (LO) signal to produce a 1-GHz output. The single ended input is converted into octet-phase, through an active input balun, an active polyphase filter, and certain phase ad... View full abstract»

• ### A 0.55 V 1.1 mW Artificial Intelligence Processor With On-Chip PVT Compensation for Autonomous Mobile Robots

Publication Year: 2018, Page(s):567 - 580
| | PDF (7179 KB) | HTML

Autonomous mobile robots are receiving a lot of attention for many applications, such as package delivery and smart surveillance, however, the battery capacity is limited to implement intelligent decision making in robots because of the heavy computational costs. In this paper, an ultra-low-power artificial intelligence processor (AIP) is proposed for real-time decision making of autonomous mobile... View full abstract»

• ### A Fully-Integrated Low-Dropout Regulator With Full-Spectrum Power Supply Rejection

Publication Year: 2015, Page(s):707 - 716
Cited by:  Papers (25)
| | PDF (2674 KB) | HTML

A fully-integrated low-dropout regulator (LDO) with fast transient response and full spectrum power supply rejection (PSR) is proposed to provide a clean supply for noise-sensitive building blocks in wideband communication systems. With the proposed point-of-load LDO, chip-level high-frequency glitches are well attenuated, consequently the system performance is improved. A tri-loop LDO architectur... View full abstract»

• ### Generalized Analysis of High-Order Switch-RC N-Path Mixers/Filters Using the Adjoint Network

Publication Year: 2018, Page(s):1 - 12
| | PDF (2489 KB)

This paper presents a systematic method to analyze N-path mixers and filters consisting of periodically switched RC-networks of arbitrary order. It is assumed that each capacitor periodically exchanges charge with the rest of the network during the on-phase of the switching clock, then samples its charge, and holds it perfectly until the next on-phase. This assumption allows for using the adjoint ... View full abstract»

• ### Resistive RAM-Centric Computing: Design and Modeling Methodology

Publication Year: 2017, Page(s):2263 - 2273
| | PDF (22510 KB) | HTML

Memory-centric computing with on-chip nonvolatile memories provides unique opportunities for native and local information processing in an energy-efficient manner. Design and modeling methodology based on resistive random access memory (RRAM) is presented in this paper. A hierarchical RRAM SPICE model having different levels of physics realism is described, where the incorporated stochasticity pro... View full abstract»

• ### Exponential Consensus of Multiagent Systems With Lipschitz Nonlinearities Using Sampled-Data Information

Publication Year: 2018, Page(s):1 - 13
| | PDF (2590 KB)

In this paper, exponential consensus of general linear multiagent systems with Lipschitz nonlinear dynamics using sampled-data information is investigated. Both leaderless and leader-following consensuses are considered. Using input-delay approach, the resulting sampled-data closed-loop systems are first reformulated as continuous systems with time-varying delay in the control input. Then, decoupl... View full abstract»

• ### High-Speed Low-Complexity Guided Image Filtering-Based Disparity Estimation

Publication Year: 2018, Page(s):606 - 617
| | PDF (4232 KB) | HTML

Stereo vision is a methodology to obtain depth in a scene based on the stereo image pair. In this paper, we introduce a discrete wavelet transform (DWT)-based methodology for a state-of-the-art disparity estimation algorithm that resulted in significant performance improvement in terms of speed and computational complexity. In the initial stage of the proposed algorithm, we apply DWT to the input ... View full abstract»

• ### Loop-Filter Design and Analysis for Delta-Sigma Modulators and Oversampled IIR Filters

Publication Year: 2018, Page(s):1 - 12
| | PDF (3151 KB)

Delta-sigma modulators spectrally shape quantization noise in discrete systems and are used extensively in communications and signal-processing systems. They are implemented using a loop-filter that processes the input and feed-back signals such that the closed loop behavior has a separate signal transfer function (STF) and noise transfer function (NTF). Loop-filter design often relies on special ... View full abstract»

• ### An Ultra-Low-Voltage CMOS Process-Insensitive Self-Biased OTA With Rail-to-Rail Input Range

Publication Year: 2015, Page(s):2380 - 2390
Cited by:  Papers (13)
| | PDF (4390 KB) | HTML

An operational-transconductance-amplifier (OTA) design for ultra-low voltage ultra-low power applications is proposed. The input stage of the proposed OTA utilizes a bulk-driven pseudo-differential pair to allow minimum supply voltage while achieving a rail-to-rail input range. All the transistors in the proposed OTA operate in the subthreshold region. Using a novel self-biasing technique to bias ... View full abstract»

• ### $W$ -Band (92–100 GHz) Phased-Array Receive Channel With Quadrature-Hybrid-Based Vector Modulator

Publication Year: 2018, Page(s):2070 - 2082
| | PDF (3381 KB) | HTML

This paper presents a W-band (92-100 GHz) phased array receive channel adopting a power domain vector modulator (VM), which utilizes a 90° hybrid-coupler-based phase interpolator. The quadrature hybrid leverages its inherent functions of quadrature phase splitting and power combining to interpolate phases by combining the weighted signals from variable gain amplifiers in the power domain. C... View full abstract»

• ### A 1 pF-to-10 nF Generic Capacitance-to-Digital Converter Using Zero-Crossing $DeltaSigma$ Modulation

Publication Year: 2018, Page(s):2169 - 2182
| | PDF (4615 KB) | HTML

Conventional capacitance-to-digital converters (CDCs) suffer limitations either on narrow capacitance range or low resolution for jitter-induced noise and high power consumption. In order to avoid these limitations, a 13-b 1 pF-10 nF generic CDC is presented. In the proposed CDC with the oversampled ΔΣ modulation, the zero-crossing-based circuits (ZCBCs) are used to replace the opera... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK