IET Computers & Digital Techniques

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• High performance and energy efficient single-precision and double-precision merged floating-point adder on FPGA

Publication Year: 2018, Page(s):20 - 29
| | PDF (2327 KB)

A high performance and energy efficient single-precision and double-precision merged floating-point adder based on the two-path FP addition algorithm designed and implemented on field programmable gate array (FPGA) is presented. With a fully pipelined architecture, the proposed adder can accomplish one double-precision addition or two parallel single-precision additions in six clock cycles. The pr... View full abstract»

• 65-nm CMOS low-energy RNS modular multiplier for elliptic-curve cryptography

Publication Year: 2018, Page(s):62 - 67
| | PDF (2603 KB)

Modular multiplication (MM) is the main operation in cryptography algorithms such as elliptic-curve cryptography (ECC) and Rivest-Shamir-Adleman, where repeated MM is used to perform elliptic curve point multiplication and modular exponentiation, respectively. The algorithm for the proposed architecture is derived from the Chinese remainder theorem and performs MM completely within a residue numbe... View full abstract»

• Brain-inspired computing

Publication Year: 2016, Page(s):299 - 305
Cited by:  Papers (1)
| | PDF (536 KB)

The inner workings of the brain as a biological information processing system remain largely a mystery to science. Yet there is a growing interest in applying what is known about the brain to the design of novel computing systems, in part to explore hypotheses of brain function, but also to see if brain-inspired approaches can point to novel computational systems capable of circumventing the limit... View full abstract»

• Comparative analysis of network-on-chip simulation tools

Publication Year: 2018, Page(s):30 - 38
| | PDF (2508 KB)

Network-on-chip (NoC) is a reliable and scalable communication paradigm deemed as an alternative to classic bus systems in modern systems-on-chip designs. Consequently, one can observe extensive multidimensional research related to the design and implementation of NoC-based systems. A basic requirement for most of these activities is the availability of NoC simulators that enable the study and com... View full abstract»

• Sign detector for the extended four-moduli set $lcub 2^n - 1comma ; 2^n + 1comma ; 2^{2n} + 1comma ; 2^{n + k}rcub${2n−1,2n+1,22n+1,2n+k}

Publication Year: 2018, Page(s):39 - 43
| | PDF (1203 KB)

This work is an additional effort to improve the performance of a four-moduli set residue-based sign detector. The study proposes an arithmetic sign detector for the extended four-moduli set {2n-1,2n+1,22n+1,2n+k}, where n and k are positive integers such that 0≤k≤n. The proposed arithmetic unit is built using carry-save adder... View full abstract»

• Variable length mixed radix MDC FFT/IFFT processor for MIMO-OFDM application

Publication Year: 2018, Page(s):9 - 19
| | PDF (7824 KB)

This study presents a variable length multi-path delay commutator fast Fourier transform (FFT)/inverse FFT (IFFT) architecture for a multiple input multiple output orthogonal frequency division multiplexing system. It supports the FFT/ IFFT lengths of 512/256/128/64 samples to process each symbol carried by eight spatial streams and achieves a speed of 160 MHz to meet the IEEE 802.11ac timing requ... View full abstract»

• Online task scheduler in 3D-MCPs with TADVA

Publication Year: 2018, Page(s):44 - 52
| | PDF (3625 KB)

Hotspots occur frequently in three-dimensional (3D) multi-core processors (3D-MCPs), and they may adversely impact both the reliability and lifetime of a system. The authors present dynamic-voltage-assignment (DVA) strategies that reduce hotspots in and optimise the performance of 3D-MCPs by pre-emptively selecting voltages among low-power and high-performance operating modes. The proposed DVA str... View full abstract»

• FPGA accelerator for floating-point matrix multiplication

Publication Year: 2012, Page(s):249 - 256
Cited by:  Papers (19)
| | PDF (290 KB)

This study treats architecture and implementation of a field-programmable gate array (FPGA) accelerator for doubleprecision floating-point matrix multiplication. The architecture is oriented towards minimising resource utilisation and maximising clock frequency. It employs the block matrix multiplication algorithm which returns the result blocks to the host processor as soon as they are computed. ... View full abstract»

• FPGA implementation of hardware efficient adaptive filter robust to impulsive noise

Publication Year: 2017, Page(s):107 - 116
| | PDF (3927 KB)

Adaptive filters are prevalent in many real-time signal processing applications. Many adaptive algorithms already exist, but most of them assume white Gaussian noise as disturbance. However, for many applications such as electrocardiogram, foetus heart rate measurement, low frequency atmospheric noise, underwater acoustic noise and signal measurement in instrumentation, the impulsive noise is more... View full abstract»

• Moving towards grey-box predictive models at micro-architecture level by investigating inherent program characteristics

Publication Year: 2018, Page(s):53 - 61
| | PDF (2684 KB)

Predictive modelling has gained much attention in the last decade, aiming fast evaluation of different design points in design space exploration (DSE) process. However, predictive model construction still requires costly simulations for every unseen program. To reduce the number of simulations, several cross-program prediction schemes have been developed. This study proposes a cross-program predic... View full abstract»

• Area- and power-efficient iterative single/double-precision merged floating-point multiplier on FPGA

Publication Year: 2017, Page(s):149 - 158
| | PDF (3194 KB)

In this study, an area and power-efficient iterative floating-point (FP) multiplier architecture is designed and implemented on FPGA devices with pipelined architecture. The proposed multiplier supports both single-precision (SP) and double-precision (DP) operations. The operation mode can be switched during run time by changing the precision selection signal. The Karatsuba algorithm is applied wh... View full abstract»

• Reducing bypass-based network-on-chip latency using priority mechanism

Publication Year: 2018, Page(s):1 - 8
| | PDF (4651 KB)

In the movement from a multi-core to a many-core era, cores count on the chip increases quickly thus interconnect plays a large role in achieving the desired performance. Network-on-chip (NoC) is the most widely used interconnect as a scalable alternative for traditional shared bus in many-core chips. As the dimensions of mesh-based NoC increase, routers and links serve as a major part to achieve ... View full abstract»

• Dependability analysis of cyber physical systems

Publication Year: 2017, Page(s):231 - 236
| | PDF (2514 KB)

As cyber physical system (CPS) is often used in safety critical areas, dependability of the system is an important issue that needs to be analysed. Any failure on the components of the CPS could result in a degradation of the physical state, which then causes major harm to life and/or property. Since the concept of dependence leads to that of trust, the subsystems of the CPS should be dependable t... View full abstract»

• Efficient ASIC and FPGA implementation of cube architecture

Publication Year: 2017, Page(s):43 - 49
| | PDF (5169 KB)

This study presents a generalised architecture for cube operation based on Yavadunam sutra of Vedic mathematics. This algorithm converts the cube of a large magnitude number into smaller magnitude number and addition operation. The Vedic sutra for decimal numbers is extended to binary radix-2 number system considering digital platforms. The cubic architecture is synthesised and simulated using Xil... View full abstract»

• Built-in time measurement circuits -- a comparative design study

Publication Year: 2007, Page(s):87 - 97
Cited by:  Papers (11)  |  Patents (4)
| | PDF (1002 KB)

An increasingly important issue in the implementation of high-performance circuits using either System-on-Chip or System-in-Package technology is ensuring the correct timing performance at the input/output interfaces of cores or chips. These interfaces are not accessible to conventional Automatic Test Equipment (ATE). However, had these nodes been accessible the limitations of the ATE to make accu... View full abstract»

• Predicting future complementary metal–oxide–semiconductor technology – challenges and approaches

Publication Year: 2016, Page(s):315 - 322
| | PDF (686 KB)

Long timescales and complex design processes require that CPU architects and microarchitects have early access to information about future manufacturing processes. In some cases, this means that future technology must be predicted in advance of it actually being developed. In addition, close collaboration with the foundries, known as `Design-Technology Co-Optimisation', or DTCO, allows the mutual ... View full abstract»

• Design of flip-flops with clock-gating and pull-up control scheme for power-constrained and speed-insensitive applications

Publication Year: 2016, Page(s):193 - 201
| | PDF (863 KB)

In this study, a novel power efficient implicit pulsed-triggered flip-flop with embedded clock-gating and pull-up control scheme (IPFF-CGPC) is proposed. By applying an XOR-based clock-gating scheme in the pulse generating stage, which conditionally disables the inverter chain when the input keeps unchanged, IPFF-CGPC is able to gain low power efficiency by eliminating redundant transitions of int... View full abstract»

• Survey of hardware protection of design data for integrated circuits and intellectual properties

Publication Year: 2014, Page(s):274 - 287
Cited by:  Papers (12)
| | PDF (612 KB)

This study reviews the current situation regarding design protection in the microelectronics industry. Over the past 10 years, the designers of integrated circuits (IC) and intellectual properties (IP) have faced increasing threats including counterfeiting, reverse-engineering and theft. This is now a critical issue for the microelectronics industry, mainly for fabless designers and IP designers. ... View full abstract»

• Reconstruction of a functional test sequence for increased fault coverage

Publication Year: 2017, Page(s):91 - 97
| | PDF (929 KB)

Simulation-based sequential test generation procedures address the high computational complexity of sequential test generation by replacing the deterministic branch-and-bound process with lower-complexity processes. These processes introduce new primary input patterns into a functional test sequence in order to increase its fault coverage. This study observes that, even without introducing new pri... View full abstract»

• Image feature extraction algorithm based on CUDA architecture: case study GFD and GCFD

Publication Year: 2017, Page(s):125 - 132
| | PDF (4526 KB)

Optimising computing times of applications is an increasingly important task in many different areas such as scientific and industrial applications. Graphics processing unit (GPU) is considered as one of the powerful engines for computationally demanding applications since it proposes a highly parallel architecture. In this context, the authors introduce an algorithm to optimise the computing time... View full abstract»

• Three-factor control protocol based on elliptic curve cryptosystem for universal serial bus mass storage devices

Publication Year: 2013, Page(s):48 - 56
Cited by:  Papers (8)
| | PDF (299 KB)

This study proposes a three-factor control protocol for universal serial bus (USB) on an elliptic curve cryptosystem (ECC). USB is a universal interface used in an enormous number of devices. It has become the most popular interface standard for computer connections. However, since USB provides high transmission speed and is very convenient to carry, many workplace and commercial establishments ha... View full abstract»

• High throughput and secure advanced encryption standard on field programmable gate array with fine pipelining and enhanced key expansion

Publication Year: 2015, Page(s):175 - 184
Cited by:  Papers (4)
| | PDF (519 KB)

Aiming at protection of high speed data, field programmable gate array (FPGA)-based advanced encryption standard (AES) design is proposed here. Deep investigation into the logical operations of AES with regard to FPGA architectures leads to two efficient pipelining structures for the AES hardware implementation. The two design options allow users to make a trade-off among speed, resource usage and... View full abstract»

• Fighting stochastic variability in a D-type flip-flop with transistor-level reconfiguration

Publication Year: 2015, Page(s):190 - 196
Cited by:  Papers (3)
| | PDF (538 KB)

In this study, the authors present a design optimisation case study of D-type flip-flop timing characteristics that are degraded as a result of intrinsic stochastic variability in a 25 nm technology process. What makes this work unique is that the design is mapped onto a multi-reconfigurable architecture, which is, like a field programmable gate array (FPGA), configurable at the gate level but can... View full abstract»

• Low-cost security aware HLS methodology

Publication Year: 2017, Page(s):68 - 79
Cited by:  Papers (1)
| | PDF (3864 KB)

Owing to massive complexity of modern digital integrated circuits (ICs) disabling complete in-house development, globalisation of the design process establishes itself as an inevitable solution for faster and efficient design. However, globalisation incurs importing intellectual property (IP) cores from various third party vendors, rendering an IP susceptible to hardware threats. To provide trust ... View full abstract»

• Hardware Trojans: current challenges and approaches

Publication Year: 2014, Page(s):264 - 273
Cited by:  Papers (4)
| | PDF (267 KB)

More and more manufacturers outsource parts of the design and fabrication of integrated circuits (ICs) for cost reduction. Recent publications show that such outsourcing can pose serious threats to governments and corporations, as they lose control of the development process. Until now, the threat of hardware Trojans is mostly considered during fabrication. Third party intellectual properties (IPs... View full abstract»

• PSN-aware circuit test timing prediction using machine learning

Publication Year: 2017, Page(s):60 - 67
| | PDF (2997 KB)

Excessive power supply noise (PSN) such as IR drop can cause yield loss when testing very large scale integration chips. However, simulation of circuit timing with PSN is not an easy task. In this study, the authors predict circuit timing for all test patterns using three machine learning techniques, neural network (NN), support vector regression (SVR), and least-square boosting (LSBoost). To redu... View full abstract»

• Quadruple throughput fixed point quarter precision multiply accumulate circuit design

Publication Year: 2017, Page(s):183 - 189
| | PDF (3183 KB)

This study proposes an efficient very large scale integration (VLSI) architecture for quadruple throughput fixed point multiply accumulate circuit (MAC). The proposed n × n bits MAC is used to perform one n × n bits or two n × (n/2) bits or ... View full abstract»

• Fault model and test procedure for phase change memory

Publication Year: 2011, Page(s):263 - 270
Cited by:  Papers (6)
| | PDF (324 KB)

Chalcogenide-based phase change memory (PCM) is a type of non-volatile memory that will most likely replace the currently widespread flash memory. Current research on PCM targets the integration feasibility, as well as the reliability of such memory technology into the currently used complementary metal oxide semiconductor (CMOS) process. Such studies identified special failure modes, known as dis... View full abstract»

• A New Squarer design with reduced area and delay

Publication Year: 2016, Page(s):205 - 214
| | PDF (1034 KB)

Digital multiplier and squarer circuits are indispensable in digital signal processing and cryptography. Using multiplier, the partial products of the squarer are generated which are added to achieve the final output. But the implementation of squaring has the advantage that we can avoid the generation of many partial products by eliminating the redundant bits, thus resulting the circuit to be sim... View full abstract»

• Fully adaptive routing algorithms and region-based approaches for two-dimensional and three-dimensional networks-on-chip

Publication Year: 2013, Page(s):264 - 273
Cited by:  Papers (2)
| | PDF (823 KB)

Network congestion has negative impact on the performance of networks-on-chip (NoC). In traditional congestion-aware techniques, congestion is measured at a router level and delivered to other routers, either local or non-local. One of the contributions of this study is to show that performance can be improved if the congestion level is measured for a group of routers, called cluster, and propagat... View full abstract»

• Simulation-based method for optimum microfluidic sample dilution using weighted mix-split of droplets

Publication Year: 2016, Page(s):119 - 127
Cited by:  Papers (1)
| | PDF (761 KB)

Digital microfluidics has recently emerged as an effective technology in providing inexpensive but reliable solutions to various biomedical and healthcare applications. On-chip dilution of a fluid sample to achieve a desired concentration is an important problem in the context of droplet-based microfluidic systems. Existing dilution algorithms deploy a sequence of balanced mix-split steps, where t... View full abstract»

• Analysis and design of moderate inversion based low power low-noise amplifier

Publication Year: 2016, Page(s):254 - 260
| | PDF (630 KB)

A fully integrated, low power low-noise amplifier (LNA) is implemented for 2.14 GHz band using 65-nm radio frequency CMOS technology. By taking advantage of higher transition frequencies of recent technologies, transistors are biased in the moderate inversion region thus permitting scaling down the supply voltage to 0.7 V. Further, the exploration of design spaces from strong to weak inversions as... View full abstract»

• High-performance elliptic curve cryptography processor over NIST prime fields

Publication Year: 2017, Page(s):33 - 42
Cited by:  Papers (1)
| | PDF (3125 KB)

This study presents a description of an efficient hardware implementation of an elliptic curve cryptography processor (ECP) for modern security applications. A high-performance elliptic curve scalar multiplication (ECSM), which is the key operation of an ECP, is developed both in affine and Jacobian coordinates over a prime field of size p using the National Institute of Standards... View full abstract»

• Optimising the SHA-512 cryptographic hash function on FPGAs

Publication Year: 2014, Page(s):70 - 82
| | PDF (1176 KB)

In this study, novel pipelined architectures, optimised in terms of throughput and throughput/area factors, for the SHA-512 cryptographic hash function, are proposed. To achieve this, algorithmic- and circuit-level optimisation techniques such as loop unrolling, re-timing, temporal pre-computation, resource re-ordering and pipeline are applied. All the techniques, except pipeline are applied in th... View full abstract»

• Impact of spintronic memory on multicore cache hierarchy design

Publication Year: 2017, Page(s):51 - 59
| | PDF (5169 KB)

Spintronic memory [spin-transfer torque-magnetic random access memory (STT-MRAM)] is an attractive alternative technology to CMOS since it offers higher density and virtually no leakage current. Spintronic memory continues to require higher write energy, however, presenting a challenge to memory hierarchy design when energy consumption is a concern. This study motivates the use of STT-MRAM for the... View full abstract»

• Low-cost digital signature architecture suitable for radio frequency identification tags

Publication Year: 2010, Page(s):14 - 26
Cited by:  Papers (4)
| | PDF (569 KB)

Continuing achievements in hardware technology are bringing ubiquitous computing closer to reality. The notion of a connected, interactive and autonomous environment is common to all sensor networks, bio-systems and radio frequency identification (RFID) devices, and the emergence of significant deployments and sophisticated applications can be expected. However, as more information is collected an... View full abstract»

• Automatic management of Software Programmable Memories in Many-core Architectures

Publication Year: 2016, Page(s):288 - 298
| | PDF (817 KB)

Software Programmable Memories, or SPMs, are raw on-chip memories that are not implicitly managed by the processor hardware, but explicitly by software. For example, while caches fetch data from memories automatically and maintain coherence with other caches, SPMs explicitly manage data movement between memories and other SPMs through software instructions. SPMs make the design of on-chip memories... View full abstract»

• Co-scheduling tasks on multi-core heterogeneous systems: An energy-aware perspective

Publication Year: 2016, Page(s):77 - 84
| | PDF (341 KB)

Single-ISA heterogeneous multi-core processors trade-off power with performance; however, threads that co-run on shared resources suffer from resource contention, which induces performance degradation and energy inefficiency. The authors introduce a novel approach to optimise the co-scheduling of multi-threaded applications on heterogeneous processors. The approach is based on the concept of st... View full abstract»

• Formal verification methodology for real-time Field Programmable Gate Array

Publication Year: 2017, Page(s):197 - 203
| | PDF (2256 KB)

A formal verification methodology for checking both functional and timing requirements of real-time digital controllers targeted at field programmable gate array technology is proposed. Timed transition systems (TTSs) are used to model both the digital controller circuit and the high-level specification requirements. Timed well-founded simulation (TWFS) refinement is used as the notion of correctn... View full abstract»

• Evaluation of simulator tools and power-aware scheduling model for wireless sensor networks

Publication Year: 2017, Page(s):173 - 182
| | PDF (2990 KB)

The sharp increase of the wireless sensor networks (WSNs) performance has increased their power requirements. However, with a limited battery lifetime it is more and more difficult to deploy many more sensors with today's solutions. Therefore, the authors need to implement autonomous WSNs without any human intervention or external power supply. To this end, this study proposes an effective strateg... View full abstract»

• High-throughput multi-key elliptic curve cryptosystem based on residue number system

Publication Year: 2017, Page(s):165 - 172
| | PDF (2662 KB)

Public-key cryptosystems such as elliptic curve cryptography (ECC) and Rivest–Shamir–Adleman (RSA) are widely used for data security in computing systems. ECC provides a high level of security with a much smaller key than RSA, which makes ECC a preferred choice in many applications. This study proposes a multi-key ECC based on the residue number system. The proposed architecture empl... View full abstract»

• Extending multi-level STT-MRAM cell lifetime by minimising two-step and hard state transitions in hot bits

Publication Year: 2017, Page(s):214 - 220
| | PDF (2004 KB)

Shifting market trends towards mobile, Internet of things, and data-centric applications create opportunities for emerging low-power non-volatile memories. The attractive features of spin-torque-transfer magnetic-RAM (STT-MRAM) make it a promising candidate for future on-chip cache memory. Two-bit multiple-level cell (MLC) STT-MRAMs suffer from higher write energy, performance overhead, and lower ... View full abstract»

• Low-power dual-edge triggered state-retention scan flip-flop

Publication Year: 2010, Page(s):410 - 419
Cited by:  Papers (1)
| | PDF (1042 KB)

This study presents a dual-edge triggered static scanable flip-flop suitable for low-power applications. The proposed circuit deploys reduced swing-clock and swing-data to manage dynamic power. Furthermore, it employs clock- and power-gating during idle mode to eliminate dynamic power and reduce static power, while retaining its state. The static structure of the circuit makes it feasible to be us... View full abstract»

• Application modelling and hardware description for network-on-chip benchmarking

Publication Year: 2009, Page(s):539 - 550
Cited by:  Papers (4)
| | PDF (385 KB)

Measuring and comparing performance, cost and other features of advanced communication architectures for complex multicore/multiprocessor systems on chip is a significant challenge which has hardly been addressed so far. This article presents a modelling concept for applications running on multicore systems and defines an extensible markup language (XML) format for documenting and distributing net... View full abstract»

• Self-reconfigurable secure file system for embedded Linux

Publication Year: 2008, Page(s):461 - 470
Cited by:  Papers (3)
| | PDF (573 KB)

With the growth of the portable electronic devices market, not only the protection of the data for the users but also the security of the designs themselves has grown significantly in importance. A solution is presented where a Linux kernel running on a PowerPC processor included in the Virtex-II Pro FPGA family is upgraded to support hardware acceleration on the ciphering tasks. In this way all t... View full abstract»

• Hardware platform for software-defined WCDMA/OFDM baseband receiver implementation

Publication Year: 2007, Page(s):640 - 652
Cited by:  Papers (4)
| | PDF (568 KB)

Wireless communications are evolving towards multi-standard systems. As multiple radio technologies need to be integrated into a single mobile terminal, the complexity of the transceiver increases considerably. Programmable architectures and re-use of hardware and software are good methods for tackling this complexity. A programmable hardware platform is presented that enables software-defined imp... View full abstract»

• Cluster-based approach for improving graphics processing unit performance by inter streaming multiprocessors locality

Publication Year: 2015, Page(s):275 - 282
Cited by:  Papers (1)
| | PDF (885 KB)

Owing to a new platform for high performance and general-purpose computing, graphics processing unit (GPU) is one of the most promising candidates for faster improvement in peak processing speed, low latency and high performance. As GPUs employ multithreading to hide latency, there is a small private data cache in each single instruction multiple thread (SIMT) core. Hence, these cores communicate ... View full abstract»

• Low complexity and area efficient reconfigurable multimode interleaver address generator for multistandard radios

Publication Year: 2016, Page(s):59 - 68
| | PDF (738 KB)

Developing a reconfigurable transceiver to support multiple protocols seamlessly and efficiently is an extremely tough task. Wireless standards such as wireless local area network (IEEE 802.11a/g) and WiMAX (IEEE 802.16e) incorporate block interleaving technique to overcome the occurrence of burst errors during transmission. Field Programmable Gate Array (FPGA) implementation of floor and modulus ... View full abstract»

• Two-phase colour-aware multicore real-time scheduler

Publication Year: 2017, Page(s):133 - 139
| | PDF (2634 KB)

A two-phase colour-aware real-time scheduler to reduce the contention caused by the cache coherence protocol due to accesses to shared cache partitions in a multicore processor is proposed. The first phase is a colour-aware task partitioning (CAP) algorithm that assigns tasks that share colours to a common processor whenever possible. The second phase is a dynamic colour-aware scheduler that detec... View full abstract»

• Dual-edge triggered sense amplifier flip-flop for resonant clock distribution networks

Publication Year: 2010, Page(s):499 - 514
Cited by:  Papers (7)
| | PDF (1207 KB)

A dual-edge sense amplifier flip-flop (DE-SAFF) for resonant clock distribution networks (CDNs) is proposed. The clocking scheme used to enable dual-edge triggering in the proposed SAFF reduces short circuit power by allowing the precharging transistors to be switched on only for a portion of the clock period. The extracted circuit layout of the proposed DE-SAFF has been simulated in STMicroelectr... View full abstract»

Aims & Scope

IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems.

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