# IEEE Transactions on Circuits and Systems I: Regular Papers

Includes the top 50 most frequently accessed documents for this publication according to the usage statistics for the month of

• ### Time Domain Processing Techniques Using Ring Oscillator-Based Filter Structures

Publication Year: 2017, Page(s):3003 - 3012
| | PDF (2197 KB) | HTML

The ability to process time-encoded signals with high fidelity is becoming increasingly important for the time domain (TD) circuit techniques that are used at the advanced nanometer technology nodes. This paper proposes a compact oscillator-based subsystem that performs precise filtering of asynchronous pulse-width modulation encoded signals and makes extensive use of digital logic, enabling low-v... View full abstract»

• ### Comprehensive Analysis of Distortion in the Passive FET Sample-and-Hold Circuit

Publication Year: 2018, Page(s):1157 - 1173
| | PDF (7128 KB) | HTML

Analysis simplified with circuit insights reveals the major sources of distortion in a passive FET-switch-based sampling circuit: 1) $R_{mathrm{scriptscriptstyle ON}}$ -modulation; 2) turn-OFF-time instant; and 3) signal-dependent charge-injection. Explicit expressions for second- and third-order distortions advance intuitive understanding of the processes of distortion. Circuit simulations and me... View full abstract»

• ### High-Efficiency Charge Pumps for Low-Power On-Chip Applications

Publication Year: 2018, Page(s):1143 - 1153
| | PDF (2501 KB) | HTML

This paper proposes charge pumps with improved power efficiency suitable for low-power on-chip applications. Undesired charge transfer, which has a direction opposite to that of the intended current flow, presents a significant source of power loss in charge pumps. The proposed charge pump circuit utilizes charge transfer switches with a complementary branch scheme to significantly reduce undesire... View full abstract»

• ### Switched-Capacitor/Switched-Inductor Structures for Getting Transformerless Hybrid DC–DC PWM Converters

Publication Year: 2008, Page(s):687 - 696
Cited by:  Papers (417)  |  Patents (1)
| | PDF (1294 KB) | HTML

A few simple switching structures, formed by either two capacitors and two-three diodes (C-switching), or two inductors and two-three diodes (L-switching) are proposed. These structures can be of two types: ldquostep-downrdquo and ldquostep-up.rdquo These blocks are inserted in classical converters: buck, boost, buck-boost, Cuk, Zeta, Sepic. The ldquostep-downrdquo C- or L-switching structures can... View full abstract»

• ### A Pulse Frequency Modulation Interpretation of VCOs Enabling VCO-ADC Architectures With Extended Noise Shaping

Publication Year: 2018, Page(s):444 - 457
| | PDF (3643 KB) | HTML

In this paper, we propose to study voltage controlled oscillators (VCOs) based on the equivalence with pulse frequency modulators (PFMs). This approach is applied to the analysis of VCO-based analog-to-digital converters (VCO-ADCs) and deviates significantly from the conventional interpretation, where VCO-ADCs have been described as the first-order ΔΣ modulators. A first advantage of... View full abstract»

• ### Factoring Integers With a Brain-Inspired Computer

Publication Year: 2018, Page(s):1051 - 1062
| | PDF (7710 KB) | HTML

The bound to factor large integers is dominated by the computational effort to discover numbers that are B-smooth, i.e., integers whose largest prime factor does not exceed B. Smooth numbers are traditionally discovered by sieving a polynomial sequence, whereby the logarithmic sum of prime factors of each polynomial value is compared to a threshold. On a von Neumann architecture, this requires a l... View full abstract»

• ### Full On-Chip CMOS Low-Dropout Voltage Regulator

Publication Year: 2007, Page(s):1879 - 1890
Cited by:  Papers (242)  |  Patents (14)
| | PDF (1617 KB) | HTML

This paper proposes a solution to the present bulky external capacitor low-dropout (LDO) voltage regulators with an external capacitorless LDO architecture. The large external capacitor used in typical LDOs is removed allowing for greater power system integration for system-on-chip (SoC) applications. A compensation scheme is presented that provides both a fast transient response and full range al... View full abstract»

• ### Memristor-Based Circuit Design for Multilayer Neural Networks

Publication Year: 2018, Page(s):677 - 686
| | PDF (2210 KB) | HTML

Memristors are promising components for applications in nonvolatile memory, logic circuits, and neuromorphic computing. In this paper, a novel circuit for memristor-based multilayer neural networks is presented, which can use a single memristor array to realize both the plus and minus weight of the neural synapses. In addition, memristor-based switches are utilized during the learning process to u... View full abstract»

• ### A Reconfigurable Streaming Deep Convolutional Neural Network Accelerator for Internet of Things

Publication Year: 2018, Page(s):198 - 208
| | PDF (2922 KB) | HTML

Convolutional neural network (CNN) offers significant accuracy in image detection. To implement image detection using CNN in the Internet of Things (IoT) devices, a streaming hardware accelerator is proposed. The proposed accelerator optimizes the energy efficiency by avoiding unnecessary data movement. With unique filter decomposition technique, the accelerator can support arbitrary convolution w... View full abstract»

• ### Consensus of Multiagent Systems and Synchronization of Complex Networks: A Unified Viewpoint

Publication Year: 2010, Page(s):213 - 224
Cited by:  Papers (891)
| | PDF (1045 KB) | HTML

This paper addresses the consensus problem of multiagent systems with a time-invariant communication topology consisting of general linear node dynamics. A distributed observer-type consensus protocol based on relative output measurements is proposed. A new framework is introduced to address in a unified way the consensus of multiagent systems and the synchronization of complex networks. Under thi... View full abstract»

• ### The flipped voltage follower: a useful cell for low-voltage low-power circuit design

Publication Year: 2005, Page(s):1276 - 1291
Cited by:  Papers (259)  |  Patents (3)
| | PDF (1168 KB) | HTML

In this paper, a basic cell for low-power and/or low-voltage operation is identified. It is evidenced how different versions of this cell, coined as "flipped voltage follower (FVF)" have been used in the past for many applications. A detailed classification of basic topologies derived from the FVF is given. In addition, a comprehensive list of recently proposed low-voltage/low-power CMOS circuits ... View full abstract»

• ### Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures

Publication Year: 2008, Page(s):1441 - 1454
Cited by:  Papers (103)  |  Patents (2)
| | PDF (1188 KB) | HTML

The need for highly integrable and programmable analog-to-digital converters (ADCs) is pushing towards the use of dynamic regenerative comparators to maximize speed, power efficiency and reconfigurability. Comparator thermal noise is, however, a limiting factor for the achievable resolution of several ADC architectures with scaled supply voltages. While mismatch in these comparators can be compens... View full abstract»

• ### A Sub-1ppm/°C Current-Mode CMOS Bandgap Reference With Piecewise Curvature Compensation

Publication Year: 2018, Page(s):904 - 913
| | PDF (3669 KB) | HTML

This paper presents a low temperature coefficient (TC) CMOS BGR for high-performance multi-channel analog-to-digital converter (ADC) working under wide temperature range. Besides the logarithmic compensation, both leakage and piecewise curvature compensation are implemented to extend its operating temperature range and keep its low TC. A β-compensation technique is used to cancel the PTAT a... View full abstract»

• ### A Millimeter-Wave Fully Integrated Passive Reflection-Type Phase Shifter With Transformer-Based Multi-Resonance Loads for 360° Phase Shifting

Publication Year: 2018, Page(s):1406 - 1419
| | PDF (8192 KB) | HTML

This paper presents a millimeter-wave fully differential transformer-based passive reflection-type phase shifter (RTPS) capable of performing full span 360° continuous phase shift from 58 to 64 GHz. It consists of two transformerbased 90° couplers and two transformer-based multi-resonance reflective loads to provide 360° phase shift with low loss and ultra-compact chip size. O... View full abstract»

• ### Analysis and Demonstration of an IIP3 Improvement Technique for Low-Power RF Low-Noise Amplifiers

Publication Year: 2018, Page(s):859 - 869
| | PDF (2601 KB) | HTML

This paper describes a linearization method to enhance the third-order distortion performance of a subthreshold common-source cascode low-noise amplifier (LNA) without extra power consumption by using passive components. An inductor between the gate of the cascode transistor and the power supply in combination with a digitally programmable capacitor between the gate and the drain of the cascode tr... View full abstract»

• ### A Low-Power NB-IoT Transceiver With Digital-Polar Transmitter in 180-nm CMOS

Publication Year: 2017, Page(s):2569 - 2581
| | PDF (4584 KB) | HTML

A fully integrated 750~960 MHz wireless transceiver (TRX) is presented for single-tone NB-IoT applications. Effective design methodologies and techniques, from the system level to circuit level, are proposed to address various design challenges while achieving low-power consumption. The TRX consists of a low-IF receiver with 180-kHz signal bandwidth, a digital polar transmitter with 3.75-kHz signa... View full abstract»

• ### An Architecture to Accelerate Convolution in Deep Neural Networks

Publication Year: 2018, Page(s):1349 - 1362
| | PDF (3035 KB) | HTML

In the past few years, the demand for real-time hardware implementations of deep neural networks (DNNs), especially convolutional neural networks (CNNs), has dramatically increased, thanks to their excellent performance on a wide range of recognition and classification tasks. When considering real-time action recognition and video/image classification systems, latency is of paramount importance. T... View full abstract»

• ### A 0.55 V 1.1 mW Artificial Intelligence Processor With On-Chip PVT Compensation for Autonomous Mobile Robots

Publication Year: 2018, Page(s):567 - 580
| | PDF (7179 KB) | HTML

Autonomous mobile robots are receiving a lot of attention for many applications, such as package delivery and smart surveillance, however, the battery capacity is limited to implement intelligent decision making in robots because of the heavy computational costs. In this paper, an ultra-low-power artificial intelligence processor (AIP) is proposed for real-time decision making of autonomous mobile... View full abstract»

• ### Analysis and Design of a Ripple Reduction Chopper Bandpass Amplifier

Publication Year: 2018, Page(s):1185 - 1195
| | PDF (3425 KB) | HTML

A low-power low-noise chopper amplifier for biosensor applications is proposed. To tackle the inherent ripple artifacts, it employs a simple ripple reduction method using a bandpass amplifier. The chopper amplifier is a linear periodic time-varying system. The method of harmonic transfer matrix is used to derive the signal and the noise harmonic transfer functions, and the theoretical results are ... View full abstract»

• ### Continuous-Time Delta-Sigma Modulators With Time-Interleaved FIR Feedback

Publication Year: 2018, Page(s):434 - 443
| | PDF (2906 KB) | HTML

The use of a single-bit quantizer in a wideband CTΔΣM is attractive, as the quantizer can be implemented in a power and area-efficient manner. Unfortunately, 1-bit CTΔΣMs are plagued by a host of difficulties. Clock jitter and quantizer metastability are particularly problematic, and the higher loop filter linearity needed to process the full-scale feedback waveform res... View full abstract»

• ### Analysis and Background Self-Calibration of Comparator Offset in Loop-Unrolled SAR ADCs

Publication Year: 2018, Page(s):458 - 470
| | PDF (2811 KB) | HTML

In conventional charge redistribution successive approximation register (SAR) ADCs that use a single comparator, the comparator offset causes no distortion but a dc shift in the transfer curve. In loop-unrolled (LU) SAR ADCs, on the other hand, mismatched comparator offset voltages introduce input-level-dependent errors to the conversion result, which deteriorates the linearity and limits the reso... View full abstract»

• ### A 12-b 40-MS/s Calibration-Free SAR ADC

Publication Year: 2018, Page(s):881 - 890
| | PDF (3686 KB) | HTML

This paper presents a new circuit technique named residue oversampling, which is suitable for high-resolution analog-to-digital converters (ADCs). By adopting this technique and simplifying the dynamic element matching, the impacts of capacitor mismatch and noise upon the successive-approximation register ADCs are reduced significantly without calibrations. The proof-of-concept prototype was fabri... View full abstract»

• ### A Gm-C Delta-Sigma Modulator With a Merged Input-Feedback Gm Circuit for Nonlinearity Cancellation and Power Efficiency Enhancement

Publication Year: 2018, Page(s):1196 - 1209
| | PDF (3355 KB) | HTML

Traditionally, a transconductor-C (Gm-C)-based delta sigma modulator (DSM) has its performance limited by the nonlinearity of its Gm circuits. To achieve sufficient linearity, source degeneration is typically applied to a Gm circuit, which inevitably reduces the Gm circuit's transconductance and thermal noise efficiencies. This paper presents new ways to change this paradigm. First, a DSM topology... View full abstract»

• ### An 11-Bit 250-nW 10-kS/s SAR ADC With Doubled Input Range for Biomedical Applications

Publication Year: 2018, Page(s):61 - 73
Cited by:  Papers (1)
| | PDF (2856 KB) | HTML

This paper presents a low-power, area-efficient 11-b single-ended successive-approximation-register (SAR) analog-todigital converter (ADC) targeted for biomedical applications. The design features an energy-efficient switching technique with an error cancelling capacitor network. The input range is twice the reference voltage. The ADC's loading of the previous stage is reduced by using a single-en... View full abstract»

• ### The Circuit Theory Behind Coupled-Mode Magnetic Resonance-Based Wireless Power Transmission

Publication Year: 2012, Page(s):2065 - 2074
Cited by:  Papers (164)
| | PDF (2999 KB) | HTML

Inductive coupling is a viable scheme to wirelessly energize devices with a wide range of power requirements from nanowatts in radio frequency identification tags to milliwatts in implantable microelectronic devices, watts in mobile electronics, and kilowatts in electric cars. Several analytical methods for estimating the power transfer efficiency (PTE) across inductive power transmission links ha... View full abstract»

• ### BiCMOS-Based Compensation: Toward Fully Curvature-Corrected Bandgap Reference Circuits

Publication Year: 2018, Page(s):1210 - 1223
| | PDF (3807 KB) | HTML

We present a novel BiCMOS-based temperature compensation technique aiming at complete correction of the curvature in the temperature response of bandgap references. The source of the appearance of this curvature is because the well-known nonlinear term T ln(T) in the base-emitter voltage (VBE) is not completely canceled across all temperature points. Here, we show that the gate-source v... View full abstract»

• ### Unified Digital Modulation Techniques for DC–DC Converters Over a Wide Operating Range: Implementation, Modeling, and Design Guidelines

Publication Year: 2018, Page(s):1442 - 1453
| | PDF (4005 KB) | HTML

It is essential to retain improved efficiency in a dc-dc converter over a wide load current range to extend the battery-life in portable devices. This requires a multi-mode controller, consisting of pulse-width-modulation (PWM) and pulse-frequency-modulation (PFM) schemes. However, existing approaches attempt to integrate structurally different controllers; thus it is difficult to achieve a seamle... View full abstract»

• ### A Two-Stage Fully Differential Inverter-Based Self-Biased CMOS Amplifier With High Efficiency

Publication Year: 2011, Page(s):1591 - 1603
Cited by:  Papers (36)  |  Patents (1)
| | PDF (1735 KB) | HTML

A two-stage fully differential CMOS amplifier comprising inverters as input structures and employing self-biasing techniques is presented. The proposed amplifier benefits from an optimum compensation through time-domain optimization which permits achieving high energy efficiency. Moreover, it achieves the highest efficiency of its class and although it relies on a quasi-class-A topology, it is com... View full abstract»

• ### Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey

Publication Year: 2011, Page(s):1 - 21
Cited by:  Papers (95)  |  Patents (7)
| | PDF (1691 KB) | HTML

This paper presents a tutorial overview of ΣΔ modulators, their operating principles and architectures, circuit errors and models, design methods, and practical issues. A review of the state of the art on nanometer CMOS implementations is described, giving a survey of cutting-edge ΣΔ architectures, with emphasis on their application to the next generation of wireless te... View full abstract»

• ### An Analogue Neuromorphic Co-Processor That Utilizes Device Mismatch for Learning Applications

Publication Year: 2018, Page(s):1174 - 1184
| | PDF (2896 KB) | HTML Media

As the integrated circuit (IC) technology advances into smaller nanometre feature sizes, a fixed-error noise known as device mismatch is introduced owing to the dissimilarity between transistors, and this degrades the accuracy of analog circuits. In this paper, we present an analog co-processor that uses this fixed-pattern noise to its advantage to perform complex computation. This circuit is an e... View full abstract»

• ### Analysis and Design of Voltage-Controlled Oscillator Based Analog-to-Digital Converter

Publication Year: 2010, Page(s):18 - 30
Cited by:  Papers (94)  |  Patents (5)
| | PDF (1424 KB) | HTML

A voltage-controlled oscillator (VCO) based analog-to-digital converter (ADC) is a time-based architecture with a first-order noise-shaping property, which can be implemented using a VCO and digital circuits. This paper analyzes the performance of VCO-based ADCs in the presence of nonidealities such as jitter, nonlinearity, mismatch, and the metastability of D flip-flops. Based on this analysis, d... View full abstract»

• ### High-Dimensional Computing as a Nanoscalable Paradigm

Publication Year: 2017, Page(s):2508 - 2521
| | PDF (3494 KB) | HTML

We outline a model of computing with high-dimensional (HD) vectors-where the dimensionality is in the thousands. It is built on ideas from traditional (symbolic) computing and artificial neural nets/deep learning, and complements them with ideas from probability theory, statistics, and abstract algebra. Key properties of HD computing include a well-defined set of arithmetic operations on vectors, ... View full abstract»

• ### A 0.55-V, 28-ppm/°C, 83-nW CMOS Sub-BGR With UltraLow Power Curvature Compensation

Publication Year: 2018, Page(s):95 - 106
| | PDF (2685 KB) | HTML

This paper proposes an ultralow power, high precision sub bandgap voltage reference (sub-BGR) for low-voltage self-powered devices. A novel ultralow power curvature compensation circuit is proposed to improve the temperature coefficient over a wide temperature range. A switch capacitor voltage divider with improved leakage current reduction switches is used to obtain a high accuracy and a low powe... View full abstract»

• ### Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial

Publication Year: 2012, Page(s):3 - 29
Cited by:  Papers (138)
| | PDF (1561 KB) | HTML

In this paper, the state of the art in ultra-low power (ULP) VLSI design is presented within a unitary framework for the first time. A few general principles are first introduced to gain an insight into the design issues and the approaches that are specific to ULP systems, as well as to better understand the challenges that have to be faced in the foreseeable future. Intuitive understanding is acc... View full abstract»

• ### A Reconfigurable 10-to-12-b 80-to-20-MS/s Bandwidth Scalable SAR ADC

Publication Year: 2018, Page(s):51 - 60
| | PDF (2552 KB) | HTML

An asynchronous successive approximation register analog-to-digital converter (ADC) for wideband multi-standard systems is presented. The ADC can be configured as an 80-MS/s 10-b, 40-MS/s 11-b, or 20-MS/s 12-b converter. Time-interleaved technique is applied to expand sampling bandwidth exponentially while resolution scales down. The channel mismatches are cancelled by the digital calibration tech... View full abstract»

• ### Linearization Techniques for CMOS Low Noise Amplifiers: A Tutorial

Publication Year: 2011, Page(s):22 - 36
Cited by:  Papers (124)  |  Patents (4)
| | PDF (1569 KB) | HTML

This tutorial catalogues and analyzes previously reported CMOS low noise amplifier (LNA) linearization techniques. These techniques comprise eight categories: a) feedback; b) harmonic termination; c) optimum biasing; d) feedforward; e) derivative superposition (DS); f) IM2 injection; g) noise/distortion cancellation; and h) post-distortion. This paper also addresses broadband-LNA-linearization iss... View full abstract»

• ### Analysis and Optimization of Direct-Conversion Receivers With 25% Duty-Cycle Current-Driven Passive Mixers

Publication Year: 2010, Page(s):2353 - 2366
Cited by:  Papers (92)  |  Patents (5)
| | PDF (2929 KB) | HTML

The performance of zero-IF receivers with current-driven passive mixers driven by 25% duty-cycle quadrature clocks is studied and analyzed. It is shown that, in general, these receivers outperform the ones that utilize passive mixers with 50% duty-cycle clocks. The known problems in receivers with 50% duty-cycle mixers, such as having unequal high- and low-side conversion gains, unexpected IIP2 an... View full abstract»

• ### Matching Properties of Femtofarad and Sub-Femtofarad MOM Capacitors

Publication Year: 2016, Page(s):763 - 772
Cited by:  Papers (2)
| | PDF (1936 KB) | HTML

Small metal-oxide-metal (MOM) capacitors are essential to energy-efficient mixed-signal integrated circuit design. However, only few reports discuss their matching properties based on large sets of measured data. In this paper, we report matching properties of femtofarad and sub-femtofarad MOM vertical-field parallel-plate capacitors and lateral-field fringing capacitors. We study the effect of bo... View full abstract»

• ### Current Mirror Array: A Novel Circuit Topology for Combining Physical Unclonable Function and Machine Learning

Publication Year: 2018, Page(s):1314 - 1326
| | PDF (3696 KB) | HTML

Edge analytics support industrial Internet of Things by pushing some data processing capacity to the edge of the network instead of sending the streaming data captured by the sensor nodes directly to the cloud. It is advantageous to endow machine learners for data reduction with suitable security primitives for privacy protection in edge computing devices to conserve area and power consumption. In... View full abstract»

• ### Picowatt, 0.45–0.6 V Self-Biased Subthreshold CMOS Voltage Reference

Publication Year: 2017, Page(s):3036 - 3046
| | PDF (2408 KB) | HTML

In this paper, a self-biased temperature compensated CMOS voltage reference operating at picowatt-level power consumption is presented. The core of the proposed circuit is the self-cascode MOSFET (SCM) and two variants are explored: a self-biased SCM (SBSCM) and a self-biased NMOS (SBNMOS) voltage reference. Power consumption and silicon area are remarkably reduced by combining subthreshold operat... View full abstract»

• ### Wideband Inductorless Low-Power LNAs with Gm Enhancement and Noise-Cancellation

Publication Year: 2018, Page(s):26 - 38
| | PDF (3641 KB) | HTML

Two inductorless low-power differential low-noise amplifiers (LNAs) are designed for multiband wireless communication applications. Both LNAs are based on the combination of common-gate (CG) and shunt feedback topologies. In the first LNA, the cross-coupled push-pull structure with separated bias for nMOS and pMOS CG transistors is utilized to realize gm enhancement, partial noise cancellation, an... View full abstract»

• ### A Silicon-Based Low-Power Broadband Transimpedance Amplifier

Publication Year: 2018, Page(s):498 - 509
| | PDF (4947 KB) | HTML

The analysis, design, and implementation of a 50-Gb/s transimpedance amplifier (TIA) in a 0.13-μm SiGe BiCMOS process are presented. The proposed TIA, designed for use in a single-channel optical communication network, is comprised of three stages including: 1) a shunt-peaked, shunt-series feedback stage incorporating a transformer-based positive feedback; 2) an RC-degenerated common-emitte... View full abstract»

• ### Digitally Assisted On-Chip Body Bias Tuning Scheme for Ultra Low-Power VLSI Systems

Publication Year: 2018, Page(s):1 - 14
| | PDF (3219 KB)

Body bias control is one of the most efficient means to reduce leakage power, adjust process variation, and apply performance boost. However, such control incurs a certain power overhead that has to be reduced, especially in ultra low-power systems. In order to exploit the advantages of body bias control while guaranteeing power efficiency, an on-chip control scheme is required. Conventionally, on... View full abstract»

• ### Consensus Tracking of Multi-Agent Systems With Lipschitz-Type Node Dynamics and Switching Topologies

Publication Year: 2014, Page(s):499 - 511
Cited by:  Papers (271)
| | PDF (3732 KB) | HTML

Distributed consensus tracking is addressed in this paper for multi-agent systems with Lipschitz-type node dynamics. The main contribution of this work is solving the consensus tracking problem without the assumption that the topology among followers is strongly connected and fixed. By using tools from M-matrix theory, a class of consensus tracking protocols based only on the relative states among... View full abstract»

• ### 1.5–3.3 GHz, 0.0077 mm2, 7 mW All-Digital Delay-Locked Loop With Dead-Zone Free Phase Detector in $0.13~mu text{m}$ CMOS

Publication Year: 2018, Page(s):39 - 50
| | PDF (4633 KB) | HTML

A 1.5-3.3 GHz, 7 mW, all-digital delay-locked loop (ADDLL) designed in a UMC 130-nm CMOS technology is presented in this paper. The proposed ADDLL uses the modified successive approximation register to control a NAND-based coarse delay line, which enables wider operating frequency range and small intrinsic delay. The inverter-based fine delay line is controlled by an XOR-based up/down counter with... View full abstract»

• ### Homeostatic Fault Tolerance in Spiking Neural Networks: A Dynamic Hardware Perspective

Publication Year: 2018, Page(s):687 - 699
| | PDF (2824 KB) | HTML

Fault tolerance is a remarkable feature of biological systems and their self-repair capability influence modern electronic systems. In this paper, we propose a novel plastic neural network model, which establishes homeostasis in a spiking neural network. Combined with this plasticity and the inspiration from inhibitory interneurons, we develop a fault-resilient robotic controller implemented on an... View full abstract»

• ### Efficient Hardware Architectures for Deep Convolutional Neural Network

Publication Year: 2017, Page(s):1 - 13
| | PDF (2109 KB)

Convolutional neural network (CNN) is the state-of-the-art deep learning approach employed in various applications. Real-time CNN implementations in resource limited embedded systems are becoming highly desired recently. To ensure the programmable flexibility and shorten the development period, field programmable gate array is appropriate to implement the CNN models. However, the limited bandwidth... View full abstract»

• ### A 3.9 mW Bluetooth Low-Energy Transmitter Using All-Digital PLL-Based Direct FSK Modulation in 55 nm CMOS

Publication Year: 2018, Page(s):1 - 12
| | PDF (4863 KB)

This paper presents a low-power frequency-shift keying (FSK) transmitter (TX) with an all-digital phase locked loop (ADPLL) based on direct modulation for use in Bluetooth low energy application. A low power ADPLL with a Retimer, 2-stage time to digital converter, and gain estimation technique is proposed to achieve low-power direct FSK modulation at 1 Mbps data rate. A high-efficiency class-D pow... View full abstract»

• ### Design Procedure for Two-Stage CMOS Opamp With Flexible Noise-Power Balancing Scheme

Publication Year: 2005, Page(s):1508 - 1514
Cited by:  Papers (43)
| | PDF (368 KB) | HTML

This paper presents a basic two-stage CMOS opamp design procedure that provides the circuit designer with a means to strike a balance between two important characteristics in electronic circuit design, namely noise performance and power consumption. It is shown in this paper that, unlike the previously reported design procedures, the proposed design step allows opamp designers to trade between noi... View full abstract»

• ### Adaptive Matrix Design for Boosting Compressed Sensing

Publication Year: 2018, Page(s):1016 - 1027
| | PDF (1656 KB) | HTML

Compressed sensing (CS) has been proposed to reduce operating cost (e.g., energy requirements) of acquisition devices by leveraging its capability of sampling and compressing an input signal at the same time. This paper aims at increasing CS performance (i.e., either achieving a better compression or allowing a higher signal reconstruction quality) and proposes two novel methods. Our first approac... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK