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Circuits and Systems I: Regular Papers, IEEE Transactions on

Popular Articles (February 2015)

Includes the top 50 most frequently downloaded documents for this publication according to the most recent monthly usage statistics.
  • 1. Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial

    Publication Year: 2012 , Page(s): 3 - 29
    Cited by:  Papers (45)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1561 KB) |  | HTML iconHTML  

    In this paper, the state of the art in ultra-low power (ULP) VLSI design is presented within a unitary framework for the first time. A few general principles are first introduced to gain an insight into the design issues and the approaches that are specific to ULP systems, as well as to better understand the challenges that have to be faced in the foreseeable future. Intuitive understanding is accompanied by rigorous analysis for each key concept. The analysis ranges from the circuit to the micro-architectural level, and reference is given to process, physical and system levels when necessary. Among the main goals of this paper, it is shown that many paradigms and approaches borrowed from traditional above-threshold low-power VLSI design are actually incorrect. Accordingly, common misconceptions in the ULP domain are debunked and replaced with technically sound explanations. View full abstract»

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  • 2. The flipped voltage follower: a useful cell for low-voltage low-power circuit design

    Publication Year: 2005 , Page(s): 1276 - 1291
    Cited by:  Papers (145)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1168 KB) |  | HTML iconHTML  

    In this paper, a basic cell for low-power and/or low-voltage operation is identified. It is evidenced how different versions of this cell, coined as "flipped voltage follower (FVF)" have been used in the past for many applications. A detailed classification of basic topologies derived from the FVF is given. In addition, a comprehensive list of recently proposed low-voltage/low-power CMOS circuits based on the FVF is given. Although the paper has a tutorial taste, some new applications of the FVF are also presented and supported by a set of simulated and experimental results. Finally, a design example showing the application of the FVF to build systems based on translinear loops is described which shows the potential of this cell for the design of high-performance low-power/low-voltage analog and mixed-signal circuits. View full abstract»

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  • 3. A Closed-Loop Reconfigurable Switched-Capacitor DC-DC Converter for Sub-mW Energy Harvesting Applications

    Publication Year: 2015 , Page(s): 385 - 394
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2107 KB) |  | HTML iconHTML  

    Energy harvesting is an emerging technology for powering wireless sensor nodes, enabling battery-free operation of these devices. In an energy harvesting sensor, a power management circuit is required to regulate the variable harvested voltage to provide a constant supply rail for the sensor circuits. The power management circuit needs to be compact, efficient, and robust to the variations of the input voltage and load current. A closed-form power expression and custom control algorithm for regulation of a switched-capacitor DC-DC converter with optimal conversion efficiency are proposed in this paper. The proposed regulation algorithm automatically adjusts both the voltage gain and switching frequency of a switched-capacitor DC-DC converter based on its input voltage and load current, increasing the power efficiency across a wide input voltage range. The design and simulation of a fully integrated circuit based on the proposed power managing approach is presented. This power management circuit has been simulated in a 0.25 μm standard CMOS process and simulation results confirm that with an input voltage ranging from 0.5 V to 2.5 V, the converter can generate a regulated 1.2 V output rail and deliver a maximum load current of 100 μA. The power conversion efficiency is higher than 74% across a wide range of the input voltage with a maximum efficiency of 83%. View full abstract»

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  • 4. On the Minimum Number of States for Switchable Matching Networks

    Publication Year: 2015 , Page(s): 433 - 440
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2211 KB) |  | HTML iconHTML  

    The impedance of an antenna changes heavily with changing EM environments, while RF power amplifiers (PAs) are optimized for driving a well-defined load impedance. As a solution, switchable matching networks are used in automatic antenna tuners to match the antenna impedance to (about) the desired PA load impedance. This paper presents a theoretical treaty of the minimum number of required states for switchable matching networks to achieve sufficient matching from a certain load VSWR to a sufficiently low input VSWR. First for an arbitrary passive lossless switchable matching network, the mathematical minimum required number of states as a function of the required input VSWR and of the required load VSWR is derived. Several variants are analyzed and benchmarked: single-stage one-ring configuration, single-stage two-ring configuration, two-stage one-ring configuration and three-stage one-ring configuration showing that single-ring configurations are optimum. An extension towards the required number of states for lossy matching networks is also provided. View full abstract»

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  • 5. An adaptive impedance tuning CMOS circuit for ISM 2.4-GHz band

    Publication Year: 2005 , Page(s): 1115 - 1124
    Cited by:  Papers (30)  |  Patents (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (784 KB) |  | HTML iconHTML  

    The difficulties encountered in matching an antenna to its optimal impedance are reduced with an adaptive 0.35-μm CMOS circuit based on several switched shunt capacitors arranged in capacitor banks and on a few external series inductors. As high-quality inductors are difficult to obtain in CMOS, the inductors are placed either in an low-temperature cofired ceramic (LTCC) substrate or is a lumped component outside the core circuit. The circuits, presented here through a range of simulations, are optimized to function within the ISM 2.4-GHz band, but the general approach employed to improve matching can be used for other frequency bands as well. The circuits discussed provide a VSWR≤2 match for every impedance with VSWR≤5. There is a 1-dB power loss for a perfect 50 Ω→50 Ω transformation, a break-even point at VSWR=1.5, and a 3-dB increase in delivered power for VSWR= 4.3. View full abstract»

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  • 6. Full On-Chip CMOS Low-Dropout Voltage Regulator

    Publication Year: 2007 , Page(s): 1879 - 1890
    Cited by:  Papers (130)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1617 KB) |  | HTML iconHTML  

    This paper proposes a solution to the present bulky external capacitor low-dropout (LDO) voltage regulators with an external capacitorless LDO architecture. The large external capacitor used in typical LDOs is removed allowing for greater power system integration for system-on-chip (SoC) applications. A compensation scheme is presented that provides both a fast transient response and full range alternating current (AC) stability from 0- to 50-mA load current even if the output load is as high as 100 pF. The 2.8-V capacitorless LDO voltage regulator with a power supply of 3 V was fabricated in a commercial 0.35-mum CMOS technology, consuming only 65 muA of ground current with a dropout voltage of 200 mV. Experimental results demonstrate that the proposed capacitorless LDO architecture overcomes the typical load transient and ac stability issues encountered in previous architectures. View full abstract»

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  • 7. Low-Distortion Wideband Delta-Sigma ADCs With Shifted Loop Delays

    Publication Year: 2015 , Page(s): 376 - 384
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1994 KB) |  | HTML iconHTML  

    This paper presents several novel low-power low-distortion ΔΣ modulator topologies with shifted loop delays. Both single-sampled and double-sampled modulators are discussed. The proposed architectures can relax the critical timing for quantization and for dynamic element matching. A delay-free integrator in the last stage is used to perform the active summation, hence eliminating the active adder. The reduced input swing of the last integrator relaxes the OTA's requirements. The proposed topology simplifies the feed-forward paths, and saves power consumption and capacitor area. Noise-coupled technique can also be utilized to enhance the noise shaping. To verify the effect of the proposed topology, single- and double-sampled third-order ΔΣ modulators with and without noise coupling were analyzed and simulated. View full abstract»

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  • 8. A Charge Recycling SAR ADC With a LSB-Down Switching Scheme

    Publication Year: 2015 , Page(s): 356 - 365
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2699 KB) |  | HTML iconHTML  

    This paper presents a new energy efficient successive approximation analog-to-digital converter (ADC) using a charge recycling and LSB-down switching scheme for the capacitive digital-to-analog converter (CDAC). Compared to the conventional binary weighed CDAC, the proposed technique exhibits a 95% reduction in switching energy, a 50% reduction in capacitor area, and with 30% reduction in nonlinearity under the same unit capacitor size and matching condition. The improvement on the switching energy consumption is the best among reported CDAC switching techniques. To validate the technique, a prototype of 10-bit ADC is fabricated in a 0.13 μm CMOS technology using standard capacitors. With a unit capacitor size of 30 fF, the ADC consumes 15.6 μW from a 0.5 V digital supply and a 1 V analog supply. The measured signal-to-noise-plus- distortion ratio is 54.6 dB (ENOB=8.8) at 1.1 MS/s. The FOM is 31.8 fJ/conv.-step, which is among the best when normalized to the same unit capacitor size. View full abstract»

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  • 9. A frequency compensation scheme for LDO voltage regulators

    Publication Year: 2004 , Page(s): 1041 - 1050
    Cited by:  Papers (93)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (576 KB) |  | HTML iconHTML  

    A stable low dropout (LDO) voltage regulator topology for low equivalent series resistance (ESR) capacitive loads is presented. The proposed scheme generates a zero internally instead of relying on the zero generated by the load capacitor and its ESR combination for stability. It is demonstrated that this scheme realizes robust frequency compensation, facilitates the use of multilayer ceramic capacitors for the load of LDO regulators, and improves transient response and noise performance. Test results from a prototype fabricated in AMI 0.5-μm CMOS technology provide the most important parameters of the regulator viz., ground current, load regulation, line regulation, output noise, and start-up time. View full abstract»

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  • 10. A 2.2 mW, 40 dB Automatic Gain Controllable Low Noise Amplifier for FM Receiver

    Publication Year: 2015 , Page(s): 600 - 606
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2024 KB) |  | HTML iconHTML  

    This paper presents an automatic gain controllable low noise amplifier (AGC-LNA) for FM receiver (FMRx). The proposed LNA adopts current reused dual gm-boosting technique for the power saving. And, a simple analog type automatic gain control (AGC) loop is proposed that provides high resolution gain control. Implemented in a 65 nm CMOS technology, measurements show power regulation range of 40 dB with ±1 dB error, less than -11 dB of S11, variable voltage gain range of -12 to 30 dB over the frequency range of 88 ~ 108 MHz, noise figure (NF) of less than 2.9 dB, P1dB of higher than -24.2 dBm, and IIP3 of higher than -12.7 dBm in the high gain (HG) mode, while dissipating only 1.8 mA from a 1.2 V supply, respectively. View full abstract»

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  • 11. Analysis and Modeling of the Phase Detector Hysteresis in Bang-Bang PLLs

    Publication Year: 2015 , Page(s): 347 - 355
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2568 KB) |  | HTML iconHTML  

    All-digital bang-bang phase-locked-loops suffer from unwanted output spurs due to their non-linear behavior. The digital implementation of these PLLs often introduces extra delay which affects the performance of BBPLLs. This comes from the retiming and resampling of the digital data in the loop. In this work the phase detector hysteresis is investigated as a source for additional performance degradation. The jitter dependency on the loop parameters in the presence of hysteresis is analyzed, providing a new insight to be considered when designing for minimum jitter. This analysis provides a quick estimation of the deterministic jitter and the location of the spurious tones thus allowing the timing resolution of the PD to be determined. A new model for the BBPLL is also introduced that considers the non-ideality of the PD and its effect on the loop. To evaluate the performance, a time-amplifier is used to improve the resolution of the PD. Jitter and spurious tone of the BBPLL with TA assisted PD are then compared with those of a loop with a regular PD. The results show that the TAPD improves the performance by a factor of 3. The design and simulations have been done in a 32-nm CMOS technology. View full abstract»

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  • 12. Complex signal processing is not complex

    Publication Year: 2004 , Page(s): 1823 - 1836
    Cited by:  Papers (53)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (528 KB) |  | HTML iconHTML  

    Wireless systems often make use of the quadrature relationship between pairs of signals to effectively cancel out-of-band and interfering in-band signal components. The understanding of these systems is often simplified by considering both the signals and system transfer functions as "complex" quantities. The complex approach is especially useful in highly integrated multistandard receivers where the use of narrow-band fixed-coefficient filters at the RF and high IF must be minimized. This paper first presents a tutorial review of complex signal processing for wireless applications. The review emphasizes a graphical and pictorial description rather than an equation-based approach. Next, a number of classical modulation architectures are described using this formulation. Finally, more recent developments such as complex filters, image-reject mixers, low-IF receivers, and oversampling analog-digital converters are discussed. View full abstract»

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  • 13. A Fully-Integrated Low-Dropout Regulator With Full-Spectrum Power Supply Rejection

    Publication Year: 2015 , Page(s): 707 - 716
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2674 KB) |  | HTML iconHTML  

    A fully-integrated low-dropout regulator (LDO) with fast transient response and full spectrum power supply rejection (PSR) is proposed to provide a clean supply for noise-sensitive building blocks in wideband communication systems. With the proposed point-of-load LDO, chip-level high-frequency glitches are well attenuated, consequently the system performance is improved. A tri-loop LDO architecture is proposed and verified in a 65 nm CMOS process. In comparison to other fully-integrated designs, the output pole is set to be the dominant pole, and the internal poles are pushed to higher frequencies with only 50 μA of total quiescent current. For a 1.2 V input voltage and 1 V output voltage, the measured undershoot and overshoot is only 43 mV and 82 mV, respectively, for load transient of 0 μA to 10 mA within edge times of 200 ps. It achieves a transient response time of 1.15 ns and the figure-of-merit (FOM) of 5.74 ps. PSR is measured to be better than -12 dB over the whole spectrum (DC to 20 GHz tested). The prototype chip measures 260×90 μm2, including 140 pF of stacked on-chip capacitors. View full abstract»

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  • 14. An All-Digital Delay-Locked Loop Using an In-Time Phase Maintenance Scheme for Low-Jitter Gigahertz Operations

    Publication Year: 2015 , Page(s): 395 - 404
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3490 KB) |  | HTML iconHTML  

    Traditional all-digital delay-locked loops (ADDLLs) have a long control loop, and false skew compensation may occur due to late code adjustment. To avoid this problem, the ADDLLs either simply sacrifice the maximum operating frequency or adopt a lower code adjustment rate to achieve a higher maximum operating frequency. However, lowering the code adjustment rate not only increases the number of the locking cycles but also results in large output jitter because the clock skew induced by run-time variations cannot be compensated in time. This paper presents a 55 nm 1.0 V 0.1-to-2.5 GHz ADDLL, which is constructed on a previously proposed half-delay-line skew-compensation circuit with several new circuit design techniques developed to achieve low jitter, small area, low power, fast lock-in, and high PVT- variation tolerance across a large operating frequency range. The key design feature is a ping-pong phase maintenance scheme that allows the code adjustment to be performed in time in each clock cycle, even for gigahertz operations. The measurement results show that the ADDLL achieves a peak-to-peak (p-p) jitter of 3 ps with 1.96 mW power consumption and 8 lock-in cycles when operated at 2.5 GHz. View full abstract»

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  • 15. An Ultra-Low Voltage Level Shifter Using Revised Wilson Current Mirror for Fast and Energy-Efficient Wide-Range Voltage Conversion from Sub-Threshold to I/O Voltage

    Publication Year: 2015 , Page(s): 697 - 706
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1827 KB) |  | HTML iconHTML  

    This paper presents a novel ultra-low voltage level shifter for fast and energy-efficient wide-range voltage conversion from sub-threshold to I/O voltage. By addressing the voltage drop and non-optimal feedback control in a state-of-the-art level shifter based on Wilson current mirror, the proposed level shifter with revised Wilson current mirror significantly improves the delay and power consumption while achieving a wide voltage conversion range. It also employs mixed-Vt device and device sizing aware of inverse narrow width effect to further improve the delay and power consumption. Measurement results at 0.18 μm show that compared with the Wilson current mirror based level shifter, the proposed level shifter improves the delay, switching energy and leakage power by up to 3×, 19×, 29× respectively, when converting 0.3 V to a voltage between 0.6 V and 3.3 V. More specifically, it achieves 1.03 (or 1.15) FO4 delay, 39 (or 954) fJ/transition and 160 (or 970) pW leakage power, when converting 0.3 V to 1.8 V (or 3.3 V), which is better than several state-of-the-art level shifters for similar range voltage conversion. The measurement results also show that the proposed level shifter has good delay scalability with supply voltage scaling and low sensitivity to process and temperature variations. View full abstract»

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  • 16. A 0.8-V, 1-MS/s, 10-bit SAR ADC for Multi-Channel Neural Recording

    Publication Year: 2015 , Page(s): 366 - 375
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1753 KB) |  | HTML iconHTML  

    This paper presents a 10-bit single-ended SAR ADC suitable for multi-channel neural recording. The proposed ADC introduces several power saving techniques to boost the energy efficiency. The ADC is built with on-chip common-mode buffer for input tracking, which is reused as the pre-amplifier of a current-mode comparator during conversion. A small capacitor is inserted between the amplifier and the capacitive DAC array in order to reduce the capacitive load on the amplifier. A split capacitor array with dual thermometer decoders is proposed to reduce the switching energy. Implemented in 0.13-μm CMOS technology, the ADC achieved a maximum differential nonlinearity (DNL) of -0.33/+0.56 LSB, maximum integral nonlinearity (INL) of -0.61/+0.55 LSB, effective number-of-bits (ENOB) of 8.8, and a power consumption of 9-μW. View full abstract»

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  • 17. A Low Phase Noise and Wide Tuning Range Millimeter-Wave VCO Using Switchable Coupled VCO-Cores

    Publication Year: 2015 , Page(s): 554 - 563
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2588 KB) |  | HTML iconHTML  

    This work presents a millimeter-wave (mm-wave) dual-mode voltage-controlled oscillator (VCO) topology with switchable coupled VCO-cores for wide frequency tuning range and low phase noise application. By taking advantage of the different parasitic capacitance of cross-coupled pair when the VCO-core operates in ON and OFF states, the dual-mode operation of VCO can be realized, and the oscillations for both modes can be excited at the lower resonant frequency of tank, such that tank Q and phase noise performance could be improved for both modes. Strongly coupled transformer with large coupling coefficient (k) is utilized to increase the oscillation stability at the desired resonant frequency for both modes. The large k transformer will also facilitate the enhancement of tank Q at the lower resonant frequency. Frequency tuning range of the VCO is increased by properly designing the VCO-cores and combining the frequency bands of the two modes. In addition, the cross-coupled pair of VCO-core at OFF state is able to act as high Q active capacitor, which can further increase the tank Q and thus reduce the phase noise. Fabricated in a 0.18 μm BiCMOS process, the VCO exhibits a wide tuning range of 17.2% from 55.7 GHz to 66 GHz, and low phase noise from -87.5 dBc/Hz to -93.5 dBc/Hz at 1 MHz offset over the entire tuning range. View full abstract»

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  • 18. Trigger-Wave Asynchronous Cellular Logic Array for Fast Binary Image Processing

    Publication Year: 2015 , Page(s): 497 - 506
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2444 KB) |  | HTML iconHTML  

    This paper presents the design and the VLSI implementation of an asynchronous cellular logic array for fast binary image processing. The proposed processor array employs trigger-wave propagation and collision detection mechanisms for binary image skeletonization, and Voronoi tessellation. Low power, low area, and high processing speed are achieved using full custom dynamic logic design. The prototype array consisting of 64 × 96 cells is fabricated in a standard 90 nm CMOS technology. The experimental results confirm the fast operation of the array, capable of extracting up to 2.78×106 skeletons per second, consuming less than 1 nJ/skeleton. The asynchronous operation enables circular wave contours, which improves the quality of the extracted skeletons. The proposed asynchronous processing module consists of 24 MOS transistors and occupies 5.5 μm×7.4 μm area. Such array can be used as a co-processing unit aiding global binary image processing in standard pixel-parallel SIMD architectures in vision chips. View full abstract»

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  • 19. A 1.2-V 4.2- \hbox {p\pm}/^{\circ}\hbox {C} High-Order Curvature-Compensated CMOS Bandgap Reference

    Publication Year: 2015 , Page(s): 662 - 670
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2150 KB) |  | HTML iconHTML  

    This study presents a high-precision CMOS bandgap reference (BGR) circuit with low supply voltage. The proposed BGR circuit consists of two BGR cores and a curvature correction circuit, which includes a current mirror and a summing circuit. Two BGR cores adopt conventional structures with the curvature-down characteristics. A current-mirror circuit is proposed to implement one of the BGR cores to have the curvature-up characteristic. Selection of the appropriate resistances in the BGR cores results in one reference voltage with a well balanced curvature-down characteristic and another reference voltage with an evenly balanced curvature-up characteristic. The summation of these reference voltages is proposed to achieve a high-order curvature compensation. This curvature correction circuit causes the proposed BGR circuit without any trimming to show a measured temperature coefficient (TC) as low as 4.2 ppm/°C over a wide temperature range of 160 °C (-40 ~ 120 °C) at a power supply voltage of 1.2 V. The average TC for 8 random samples is approximately 9.3 ppm/°C. The measured power-supply rejection ratio (PSRR) of -30 dB is achieved at the frequency of 100 kHz. The total chip size is 0.063 mm2 with a standard 0.13-μm CMOS process. View full abstract»

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  • 20. Switched-Capacitor/Switched-Inductor Structures for Getting Transformerless Hybrid DC–DC PWM Converters

    Publication Year: 2008 , Page(s): 687 - 696
    Cited by:  Papers (164)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1294 KB) |  | HTML iconHTML  

    A few simple switching structures, formed by either two capacitors and two-three diodes (C-switching), or two inductors and two-three diodes (L-switching) are proposed. These structures can be of two types: ldquostep-downrdquo and ldquostep-up.rdquo These blocks are inserted in classical converters: buck, boost, buck-boost, Cuk, Zeta, Sepic. The ldquostep-downrdquo C- or L-switching structures can be combined with the buck, buck-boost, Cuk, Zeta, Sepic converters in order to get a step-down function. When the active switch of the converter is on, the inductors in the L-switching blocks are charged in series or the capacitors in the C-switching blocks are discharged in parallel. When the active switch is off, the inductors in the L-switching blocks are discharged in parallel or the capacitors in the C-switching blocks are charged in series. The ldquostep-uprdquo C- or L-switching structures are combined with the boost, buck-boost, Cuk, Zeta, Sepic converters, to get a step-up function. The steady-state analysis of the new hybrid converters allows for determing their DC line-to-output voltage ratio. The gain formula shows that the hybrid converters are able to reduce/increase the line voltage more times than the original, classical converters. The proposed hybrid converters contain the same number of elements as the quadratic converters. Their performances (DC gain, voltage and current stresses on the active switch and diodes, currents through the inductors) are compared to those of the available quadratic converters. The superiority of the new, hybrid converters is mainly based on less energy in the magnetic field, leading to saving in the size and cost of the inductors, and less current stresses in the switching elements, leading to smaller conduction losses. Experimental results confirm the theoretical analysis. View full abstract»

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  • 21. A 12-bit 8.47-fJ/Conversion-Step Capacitor-Swapping SAR ADC in 110-nm CMOS

    Publication Year: 2015 , Page(s): 10 - 18
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2496 KB) |  | HTML iconHTML  

    This paper presents a 12-bit energy-efficient successive approximation register analog-to-digital converter (ADC). By incorporating the proposed capacitor-swapping technique, which eliminates the problematic MSB mismatch transition of a binary-weighted capacitor digital-to-analog converter, the 12-bit linearity of the ADC is achieved without increasing the capacitor size for improved matching. The small capacitor size results in low power consumption. In addition, an on-the-fly programmable dynamic comparator is used for quick comparisons with low noise contributions within the limited power budget. The ADC is fabricated using a 110-nm CMOS process. It consumes 16.47 μW from a 0.9-V supply at a conversion-rate of 1 MS/s. The measured DNL and INL are within 0.3 LSB and 0.56 LSB, respectively. The measured SNDR and SFDR are at 67.3 dB and 87 dB, respectively. The ENOB performance is 10.92 b, which is equivalent to a figure-of-merit of 8.47 fJ/conversion-step. View full abstract»

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  • 22. Variations in Nanometer CMOS Flip-Flops: Part I—Impact of Process Variations on Timing

    Publication Year: 2015 , Page(s): 1 - 9
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1922 KB)  

    In this paper, split into Part I and II, the impact of variations on single-edge triggered flip-flops (FFs) is comparatively evaluated across a wide range of state-of-the-art topologies. The analysis explicitly considers fundamental sources of variations such as process/voltage/temperature (PVT), as well as the clock network (clock slope variations). For each topology, the variations of performance, robustness against hold violations, energy and leakage are statistically evaluated and compared. The impact of layout parasitics is explicitly included in the circuit design loop. The presented results provide well-defined guidelines for variation-aware selection of the flip-flop topologies, and estimates for early budgeting of variations before detailed circuit design. Also, the analysis enables a deeper understanding of the sensitivity to variations of existing topologies across a wide range of sizes and loads. In particular, this Part I introduces the methodology, the targeted flip-flop topologies and investigates the impact of process variations on flip-flop timing. View full abstract»

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  • 23. A Circuit-Based Learning Architecture for Multilayer Neural Networks With Memristor Bridge Synapses

    Publication Year: 2015 , Page(s): 215 - 223
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2415 KB) |  | HTML iconHTML  

    Memristor-based circuit architecture for multilayer neural networks is proposed. It is a first of its kind demonstrating successful circuit-based learning for multilayer neural network built with memristors. Though back-propagation algorithm is a powerful learning scheme for multilayer neural networks, its hardware implementation is very difficult due to complexities of the neural synapses and the operations involved in the learning algorithm. In this paper, the circuit of a multilayer neural network is designed with memristor bridge synapses and the learning is realized with a simple learning algorithm called Random Weight Change (RWC). Though RWC algorithm requires more iterations than back-propagation algorithm, we show that a circuit-based learning using RWC is two orders faster than its software counterpart. The method to build a multilayer neural network using memristor bridge synapses and a circuit-based learning architecture of RWC algorithm is proposed. Comparison between software-based and memristor circuit-based learning are presented via simulations. View full abstract»

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  • 24. Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures

    Publication Year: 2008 , Page(s): 1441 - 1454
    Cited by:  Papers (53)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1188 KB) |  | HTML iconHTML  

    The need for highly integrable and programmable analog-to-digital converters (ADCs) is pushing towards the use of dynamic regenerative comparators to maximize speed, power efficiency and reconfigurability. Comparator thermal noise is, however, a limiting factor for the achievable resolution of several ADC architectures with scaled supply voltages. While mismatch in these comparators can be compensated for by calibration, noise can irreparably hinder performance and is less straightforward to be accounted for at design time. This paper presents a method to estimate the input referred noise in fully dynamic regenerative comparators leveraging a reference architecture. A time-domain analysis is proposed that accounts for the time varying nature of the circuit exploiting some basic results from the solution of stochastic differential equations. The resulting symbolic expressions allow focusing designers' attention on the most influential noise contributors. Analysis results are validated by comparison with electrical simulations and measurement results from two ADC prototypes based on the reference comparator architecture, implemented in 0.18-mum and 90-nm CMOS technologies. View full abstract»

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  • 25. An 83.4% Peak Efficiency Single-Inductor Multiple-Output Based Adaptive Gate Biasing DC-DC Converter for Thermoelectric Energy Harvesting

    Publication Year: 2015 , Page(s): 405 - 412
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2161 KB) |  | HTML iconHTML  

    This paper presents a 100 mV input, 500 mV output single-inductor multiple-output (SIMO) based step-up dc-dc converter with adaptive gate biasing (AGB) technique implemented in 0.18 μm CMOS technology for thermoelectric energy harvesting. The proposed AGB technique and near-threshold voltage (near- VTH) energy redistribution control (ERC) ensure high conversion efficiency over a wide range of load currents. The proposed method automatically reduces conduction and switching losses of power MOSFETs without the need for auxiliary power converters or additional off-chip inductors. The AGB technique reduces conduction and switching losses under heavy-load and light-load conditions, respectively. The experimental results show that the efficiency of the proposed converter is enhanced by 25.5% and 18% at output load currents of 1500 μA and 50 μA, respectively. The proposed step-up dc-dc converter achieves the lowest output voltage and provides the highest conversion efficiency of 83.4% to date in standard CMOS process for thermoelectric energy harvesting. View full abstract»

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  • 26. An Ultra-Low-Power Energy-Efficient Dual-Mode Wake-Up Receiver

    Publication Year: 2015 , Page(s): 517 - 526
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2015 KB) |  | HTML iconHTML  

    An ultra-low-power wake-up receiver is proposed to reduce the energy consumption through adoption of two wake-up modes of operation with different power dissipations and detection bandwidths. During the Monitoring (MO) mode, the start frame bits are received at a data rate of 10 kbps, while during the Identifier (ID) mode the remaining wake-up pattern is transmitted at 200 kbps. By lowering the gain of the front-end amplifier in the MO mode the power dissipation is reduced, which in turn causes an increase in the overall noise figure of the receiver. However, adequate sensitivity is maintained by intentionally lowering the data rate as well as the detection bandwidth of the receiver. The proposed wake-up receiver is designed and fabricated in IBM 130 nm technology with a core size of about 0.2 mm2 for the target frequency range of 902-928 MHz. The measured results show that the proposed dual-mode receiver achieves a sensitivity of -78.5 dBm and -75 dBm while dissipating an average power of 16.4 μW and 22.9 μW during MO and ID modes, respectively. View full abstract»

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  • 27. Theory and Design of a Quadrature Analog-to-Information Converter for Energy-Efficient Wideband Spectrum Sensing

    Publication Year: 2015 , Page(s): 527 - 535
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2274 KB) |  | HTML iconHTML  

    A flexible bandwidth, blind sub-Nyquist sampling approach referred to as the quadrature analog-to-information converter (QAIC) is proposed. The QAIC relaxes the analog front-end bandwidth requirements at the cost of some added complexity compared to the modulated wideband converter (MWC) for an overall improvement in sensitivity and energy consumption. An approach for detailed frequency domain analysis of the proposed system with linear impairments is developed. A process for selecting QAIC parameter values is illustrated through examples. The benefits of the QAIC are highlighted with cognitive radio use cases where a wide range of spectrum is observed at various resolution bandwidth settings. We demonstrate that the energy consumption of the QAIC is potentially two orders of magnitude lower than the swept-tuned spectrum analyzer (STSA) and an order of magnitude lower than the MWC. We also demonstrate that the QAIC significantly improves upon the sensitivity performance delivered by the MWC. View full abstract»

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  • 28. Design of Low-Noise K -Band SiGe Bipolar VCOs: Theory and Implementation

    Publication Year: 2015 , Page(s): 607 - 615
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1701 KB) |  | HTML iconHTML  

    A study of K-band SiGe bipolar VCOs is reported in this paper. The design challenges related to the operation in the K-band and the use of a pure bipolar technology are discussed with particular emphasis to achieving low phase noise while using varactor diodes. Two different VCOs have been designed and fabricated. In the designs, the varactor is coupled to the active element by means of a magnetic transformer to avoid the use of tuning voltages exceeding the supply voltage. All the VCOs are operated in class-C. One of the designs features dynamic biasing to ensure robust start-up conditions. The VCOs feature a phase noise as low as -137 dBc/Hz at 10 MHz offset from the carrier. The VCOs show a state-of-the-art FOM of -189 dBc/Hz, and an excellent FOMT of -193 dB/Hz. View full abstract»

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  • 29. A Sub- \mu{\rm W} Bandgap Reference Circuit With an Inherent Curvature-Compensation Property

    Publication Year: 2015 , Page(s): 1 - 9
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1515 KB) |  | HTML iconHTML  

    A new current-mode bandgap reference circuit (BGR) which is capable of generating sub-1-V output voltage is presented. It has not only the lowest theoretical minimum current consumption among published current-mode BGRs, but also additional advantages of an inherent curvature-compensation function and not requiring NPN BJTs. The curvature-compensation is achieved by utilizing the exponential behavior of sub-threshold CMOS transistors to compensate the BJT base-emitter voltage high-order temperature dependence. By taking advantages of the continuing development of CMOS technology, sub- μW power consumption is achieved with a reasonable core area. Related design considerations and challenges are discussed and analyzed. The proposed BGR is realized in a TSMC 90 nm process. Measurement results shows a temperature coefficient without trimming as low as 10.1 ppm/°C over a temperature range of 70 °C because of the proposed curvature-compensation technique. The average value is 32.6 ppm/°C which could be improved by trimming resistor ratios. The average power consumption at room temperature is 576 nW, with a core area of only 0.028 mm2. View full abstract»

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  • 30. A 0.3 V 10-bit 1.17 f SAR ADC With Merge and Split Switching in 90 nm CMOS

    Publication Year: 2015 , Page(s): 70 - 79
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2839 KB) |  | HTML iconHTML  

    This paper presents a 10-bit ultra-low voltage energy-efficient SAR ADC. The proposed merge-and-split (MS) switching effectively reduces DAC switching energy by 83% compared with conventional one without the need of extra reference voltage (Vcm) and the issue of common-mode voltage variation. To maintain good input linearity, a new double-bootstrapped sample-and-hold (S/H) circuit is proposed under an ultra-low voltage of 0.3 V. In addition, by employing asymmetric logic in SAR control, the leakage power is reduced with the penalty of slight conversion speed degradation. The test chip fabricated in 90 nm CMOS occupied a core area of 0.03 mm2. With a single 0.3 V supply and a Nyquist rate input, the prototype consumes 35 nW at 90 kS/s and achieves an ENOB of 8.38 bit and a SFDR of 78.2 dB, respectively. The operation frequency is scalable up to 2 MS/s and power supply range from 0.3 V to 0.5 V. The resultant FOMs are 1.17-to-1.78 fJ/conv.-step. View full abstract»

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  • 31. Comparative Analysis of Simulation-Based Methods for Deriving the Phase- and Gain-Margins of Feedback Circuits With Op-Amps

    Publication Year: 2015 , Page(s): 625 - 634
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2040 KB) |  | HTML iconHTML  

    Ten methods for finding through simulations the small-signal phase and gain margins of feedback circuits based on op-amps are described and analyzed in this mostly tutorial paper. The testbenches employed by these methods are presented and the corresponding analytical expressions of the return ratio are derived and compared against their “ideal” counterpart, obtained with standard circuit analysis; the requirement that the return ratio should not depend on the point it was measured at is also verified. These analyses are performed on a fairly general case: a generic reciprocal two-port network that closes a feedback loop around an op-amp acting as the forward amplifier. The four main types of op-amps were considered. The limitations of some of the tested methods are then highlighted by simulations. Besides the detailed analysis of previously reported methods, the paper proposes a novel method for deriving the return ratio of feedback circuits, that employs only current stimuli; it is demonstrated analytically that this method can be used for bilateral circuits, not only for op-amp-based (unilateral) ones. Also, a recent method for deriving directly the phase margin of a circuit is extended to estimating the gain margin, too. Conclusions on the accuracy and suitability of the analyzed methods for practical circuit cases are drawn. These results are then extended to other circuit topologies. View full abstract»

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  • 32. Analog Circuit Design Using Tunnel-FETs

    Publication Year: 2015 , Page(s): 39 - 48
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2382 KB) |  | HTML iconHTML  

    Tunnel-FET (TFET) is a major candidate for beyond-CMOS technologies. In this paper, the properties of the TFETs that affect analog circuit design are studied. To demonstrate how TFETs can enhance the performance or change the topology of the analog circuits, several building blocks such as operational transconductance amplifiers (OTAs), current mirrors, and track-and-hold circuits are examined. It is shown that TFETs are promising for low-power and low-voltage designs, wherein transistors are biased at low-to-moderate current densities. Comparing 14-nm III-V TFET-based OTAs with Si-MOSFET-based designs demonstrates up to 5 times reduction in the power dissipation of the amplifiers and more than an order of magnitude increase in their DC voltage gain. The challenges and opportunities that come with the special characteristics of TFETs, namely asymmetry, ambipolar behavior, negative differential resistance, and superlinear operation are discussed in detail. View full abstract»

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  • 33. Tunable Duplexer With Passive Feed-Forward Cancellation to Improve the RX-TX Isolation

    Publication Year: 2015 , Page(s): 536 - 544
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2529 KB) |  | HTML iconHTML  

    The paper presents an approach that enables trading off the insertion loss versus isolation in the duplexer design. Specifically, the Insertion Loss (IL) of the duplexer filters is reduced by using low-order Bandpass Filters (BPF), while the transmitter (TX) to receiver (RX) isolation is improved using a feed-forward, passive, wideband, cancellation scheme. The proposed cancellation scheme is fully passive and hence the duplexer does not incur power consumption and noise penalties. The linearity of the proposed duplexer is very high limited only by the tunable passive components used in the design. A tunable duplexer prototype is demonstrated with TX-RX isolation better than 50 dB in both TX and RX bands (high band TX: 860-890 MHz, RX: 948-984 MHz; low band TX: 700-718 MHz, RX: 780-801 MHz). Tuning is achieved using digitally controlled switched capacitors with silicon on sapphire (SOS) switches resulting in high linearity. View full abstract»

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  • 34. Envelope Tracked Pulse Gate Modulated GaN HEMT Power Amplifier for Wireless Transmitters

    Publication Year: 2015 , Page(s): 571 - 579
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1821 KB) |  | HTML iconHTML  

    This paper proposes a complete transmitter prototype for wireless applications using envelope tracked pulsed gate modulated power amplifier (PA). The proposed transmitter architecture is developed using two high power 10 W gate modulated PAs combined in a fashion to operate as a switched voltage source for the range of duty cycles of pulses driving the gates of power amplifiers. These PAs are designed and implemented using packaged GaN HEMT transistors from CREE to operate at the carrier frequency of 2.35 GHz. For a 5 MHz bandwidth WiMAX 802.16e down-link signal with the PAPR of 7.9 dB and the oversampling ratio of 100, the average drain efficiency of 46.2% is achieved at the average output power of 35.8 dBm. Using a 5 MHz bandwidth LTE down-link signal with 11 dB PAPR and centered at 2.35 GHz, the power amplifier delivers the average output power of 33.2 dBm with the average drain efficiency of 46%. The adjacent channel leakage ratio (ACLR) measured for this signal is less than -36.85 dBc at 10 MHz offset from the center frequency of 2.35 GHz. View full abstract»

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  • 35. Consensus of Multiagent Systems and Synchronization of Complex Networks: A Unified Viewpoint

    Publication Year: 2010 , Page(s): 213 - 224
    Cited by:  Papers (252)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1045 KB) |  | HTML iconHTML  

    This paper addresses the consensus problem of multiagent systems with a time-invariant communication topology consisting of general linear node dynamics. A distributed observer-type consensus protocol based on relative output measurements is proposed. A new framework is introduced to address in a unified way the consensus of multiagent systems and the synchronization of complex networks. Under this framework, the consensus of multiagent systems with a communication topology having a spanning tree can be cast into the stability of a set of matrices of the same low dimension. The notion of consensus region is then introduced and analyzed. It is shown that there exists an observer-type protocol solving the consensus problem and meanwhile yielding an unbounded consensus region if and only if each agent is both stabilizable and detectable. A multistep consensus protocol design procedure is further presented. The consensus with respect to a time-varying state and the robustness of the consensus protocol to external disturbances are finally discussed. The effectiveness of the theoretical results is demonstrated through numerical simulations, with an application to low-Earth-orbit satellite formation flying. View full abstract»

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  • 36. Multicarrier Faster-Than-Nyquist Transceivers: Hardware Architecture and Performance Analysis

    Publication Year: 2011 , Page(s): 827 - 838
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2090 KB) |  | HTML iconHTML  

    This paper evaluates the hardware aspects of multicarrier faster-than-Nyquist (FTN) signaling transceivers. The choice of time-frequency spacing of the symbols in an FTN system for improved bandwidth efficiency is targeted towards efficient hardware implementation. This work proposes a hardware architecture for the realization of iterative decoding of FTN multicarrier modulated signals. Compatibility with existing systems has been considered for smooth switching between the faster-than-Nyquist and orthogonal signaling schemes. One such being the use of fast Fourier transforms (FFTs) for multicarrier modulation. The performance of the fixed point model is very close to that of the floating point representation. The impact of system parameters such as number of projection points, time-frequency spacing, finite wordlengths and their design tradeoffs for reduced complexity iterative decoders in FTN systems have been investigated. The FTN decoder has been designed and synthesized in both 65 nm CMOS and FPGA. From the hardware resource usage numbers it can be concluded that FTN signaling can be used to achieve higher bandwidth efficiency with acceptable complexity overhead. View full abstract»

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  • 37. Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits

    Publication Year: 2015 , Page(s): 458 - 467
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1968 KB) |  | HTML iconHTML  

    This article explores the effect of device parameter variations on the performance of subthreshold source-coupled logic (STSCL) circuits. A test chip has been fabricated in a standard CMOS 90 nm technology to study the matching properties of STSCL circuits. Both process variations and device mismatch have been included in this study. The performed analysis shows that while the STSCL topology is very robust against global variations mainly thanks to the adoption of an on-chip bias generator circuit, special design techniques are required to compensate for the effect of device mismatch. Proper device sizing as well as creating intentional mismatch in the biasing condition of STSCL gates are two effective approaches that have been investigated to overcome the variation related issues. Both die-to-die (D2D) and within-die (WID) variations in the delay of STSCL gates have been characterized and validated through measurements. A comprehensive analysis of timing jitter in STSCL-based ring oscillators is also presented. View full abstract»

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  • 38. Analysis and Design of a Core-Size-Scalable Low Phase Noise LC -VCO for Multi-Standard Cellular Transceivers

    Publication Year: 2015 , Page(s): 781 - 790
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2673 KB) |  | HTML iconHTML  

    A core-size-scalable LC-voltage-controlled oscillator (VCO) for multi-standard cellular transceivers was fabricated in a 65-nm CMOS process. Theoretical analysis showed that when core current is small a VCO with a larger core-size can achieve lower phase noise. However, when core current is large, a VCO with a smaller core-size can lower phase noise. Based on the analysis, the effective core-size of the VCO was designed to be scalable according to the core current, by switching the secondary core-transistors on or off. Thus, the proposed VCO becomes adaptive to multi-standard cellular transceivers. By turning on the switch, the VCO can operate in the low power (LP) mode for standards that require moderate phase noise in a tight power budget. On the other hand, by turning off the switch, the VCO can operate in the low noise (LN) mode for standards that demand stringent phase noise in a relaxed power budget. When the core current is set to 4 mA, the VCO in the LP mode achieved the phase noise of -127.9 dBc/Hz at the 3 MHz offset from 3.3-GHz signals. When the core current was set to 15 mA, phase noise of the VCO in the LN mode was minimized to -137.5 dBc/Hz at the same offset. The figure of merit (FOM) was -184.8 and -186.5 dB, respectively. View full abstract»

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  • 39. Improved 8-Point Approximate DCT for Image and Video Compression Requiring Only 14 Additions

    Publication Year: 2014 , Page(s): 1727 - 1740
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3132 KB) |  | HTML iconHTML  

    Video processing systems such as HEVC requiring low energy consumption needed for the multimedia market has lead to extensive development in fast algorithms for the efficient approximation of 2-D DCT transforms. The DCT is employed in a multitude of compression standards due to its remarkable energy compaction properties. Multiplier-free approximate DCT transforms have been proposed that offer superior compression performance at very low circuit complexity. Such approximations can be realized in digital VLSI hardware using additions and subtractions only, leading to significant reductions in chip area and power consumption compared to conventional DCTs and integer transforms. In this paper, we introduce a novel 8-point DCT approximation that requires only 14 addition operations and no multiplications. The proposed transform possesses low computational complexity and is compared to state-of-the-art DCT approximations in terms of both algorithm complexity and peak signal-to-noise ratio. The proposed DCT approximation is a candidate for reconfigurable video standards such as HEVC. The proposed transform and several other DCT approximations are mapped to systolic-array digital architectures and physically realized as digital prototype circuits using FPGA technology and mapped to 45 nm CMOS technology. View full abstract»

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  • 40. Linearization Techniques for CMOS Low Noise Amplifiers: A Tutorial

    Publication Year: 2011 , Page(s): 22 - 36
    Cited by:  Papers (39)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1569 KB) |  | HTML iconHTML  

    This tutorial catalogues and analyzes previously reported CMOS low noise amplifier (LNA) linearization techniques. These techniques comprise eight categories: a) feedback; b) harmonic termination; c) optimum biasing; d) feedforward; e) derivative superposition (DS); f) IM2 injection; g) noise/distortion cancellation; and h) post-distortion. This paper also addresses broadband-LNA-linearization issues for emerging reconfigurable multiband/multistandard and wideband transceivers. Furthermore, we highlight the impact of CMOS technology scaling on linearity and outline how to design a linear LNA in a deep submicrometer process. Finally, general design guidelines for high-linearity LNAs are provided. View full abstract»

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  • 41. A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT

    Publication Year: 2015 , Page(s): 449 - 457
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2339 KB) |  | HTML iconHTML  

    Approximation of discrete cosine transform (DCT) is useful for reducing its computational complexity without significant impact on its coding performance. Most of the existing algorithms for approximation of the DCT target only the DCT of small transform lengths, and some of them are non-orthogonal. This paper presents a generalized recursive algorithm to obtain orthogonal approximation of DCT where an approximate DCT of length N could be derived from a pair of DCTs of length (N/2) at the cost of N additions for input preprocessing. We perform recursive sparse matrix decomposition and make use of the symmetries of DCT basis vectors for deriving the proposed approximation algorithm. Proposed algorithm is highly scalable for hardware as well as software implementation of DCT of higher lengths, and it can make use of the existing approximation of 8-point DCT to obtain approximate DCT of any power of two length, N > 8. We demonstrate that the proposed approximation of DCT provides comparable or better image and video compression performance than the existing approximation methods. It is shown that proposed algorithm involves lower arithmetic complexity compared with the other existing approximation algorithms. We have presented a fully scalable reconfigurable parallel architecture for the computation of approximate DCT based on the proposed algorithm. One uniquely interesting feature of the proposed design is that it could be configured for the computation of a 32-point DCT or for parallel computation of two 16-point DCTs or four 8-point DCTs with a marginal control overhead. The proposed architecture is found to offer many advantages in terms of hardware complexity, regularity and modularity. Experimental results obtained from FPGA implementation show the advantage of the proposed method. View full abstract»

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  • 42. An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis

    Publication Year: 2015 , Page(s): 1071 - 1080
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1233 KB)  

    This paper proposes an efficient constant multiplier architecture based on vertical-horizontal binary common sub-expression elimination (VHBCSE) algorithm for designing a reconfigurable finite impulse response (FIR) filter whose coefficients can dynamically change in real time. To design an efficient reconfigurable FIR filter, according to the proposed VHBCSE algorithm, 2-bit binary common sub-expression elimination (BCSE) algorithm has been applied vertically across adjacent coefficients on the 2-D space of the coefficient matrix initially, followed by applying variable-bit BCSE algorithm horizontally within each coefficient. This technique is capable of reducing the average probability of use or the switching activity of the multiplier block adders by 6.2% and 19.6% as compared to that of two existing 2-bit and 3-bit BCSE algorithms respectively. ASIC implementation results of FIR filters using this multiplier show that the proposed VHBCSE algorithm is also successful in reducing the average power consumption by 32% and 52% along with an improvement in the area power product (APP) by 25% and 66% compared to those of the 2-bit and 3-bit BCSE algorithms respectively. As regards the implementation of FIR filter, improvements of 13% and 28% in area delay product (ADP) and 76.1% and 77.8% in power delay product (PDP) for the proposed VHBCSE algorithm have been achieved over those of the earlier multiple constant multiplication (MCM) algorithms, viz. faithfully rounded truncated multiple constant multiplication/accumulation (MCMAT) and multi-root binary partition graph (MBPG) respectively. Efficiency shown by the results of comparing the FPGA and ASIC implementations of the reconfigurable FIR filter designed using VHBCSE algorithm based constant multiplier establishes the suitability of the proposed algorithm for efficient fixed point reconfigurable FIR filter synthesis. View full abstract»

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  • 43. Hybrid CMOS Rectifier Based on Synergistic RF-Piezoelectric Energy Scavenging

    Publication Year: 2014 , Page(s): 3330 - 3338
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2288 KB) |  | HTML iconHTML  

    This paper presents a novel CMOS hybrid rectifier that can simultaneously and efficiently scavenge energy from a low-amplitude radio-frequency (RF) signal and a low-frequency, low-energy signal from a piezoelectric (PZT) transducer. The piezoelectric signal is used for biasing a complimentary, cross-coupled rectifier (CCCR) chain to an operating point such that the RF signal energy can be efficiently harvested, even if its amplitude is well below the threshold voltage (VTH) of the rectifier transistors. The device sizes for the proposed design have been optimized to achieve the maximum DC output voltage and the proposed design is shown to effectively eliminate dead-zones in the rectifier response. The measurement results show that a 6-stage hybrid rectifier (HR) can generate up to 1 V DC output voltage at a load current of 3 μA when a 300 mV peak-to-peak, 13.56 MHz RF signal is applied in conjunction with a 10 KHz, 2 V piezoelectric signal. Using measured results from prototypes fabricated in a 90 nm CMOS process, the proposed HR is shown to yield a significant improvement in power conversion efficiency (PCE) for low levels of input power when compared to a conventional CCCR that has been implemented on the same die. View full abstract»

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  • 44. Power Management System for Online Low Power RF Energy Harvesting Optimization

    Publication Year: 2010 , Page(s): 1802 - 1811
    Cited by:  Papers (36)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1787 KB) |  | HTML iconHTML  

    For many years, wireless RF power transmission has been investigated as a viable method of power delivery in a wide array of applications, from high-power space solar power satellites to low-power wireless sensors. However, until recently, efficient application at the low sub-milliwatt power levels has not been realized due to limitations in available control circuitry. This paper presents a “smart” microcontroller-based power management system with online power stage efficiency optimization and maximum power point tracking (MPPT). The system is experimentally evaluated using a new, more accurate four-quadrant rectenna model and circuit realization that enables rigorous testing of the power management system for a wide range of rectenna arrays and power characteristics. Hardware results are presented with online optimization over a converter input power range from 10 μW to 1 mW. Results are also shown based on the application of harvesting RF power from a nearby cellular tower, where the power management system collects up to seven times more energy when compared to a direct battery connection. View full abstract»

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  • 45. Weakly-Coupled Resonators in Capacitive Readout Circuits

    Publication Year: 2015 , Page(s): 337 - 346
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2412 KB) |  | HTML iconHTML  

    Low energy consumption and wide operating temperature range of capacitors made them common in sensor designs, e.g., MEMS accelerometers, and hence increased the popularity of capacitive readout circuits. Their main challenges, in either discrete or integrated implementations, are sensitivity, noise, energy consumption, and parasitic components at the analog front end. Compared to conventional “frequency-shift monitoring” which is one of the most accurate and common methods for capacitance measurements, weakly-coupled resonators (well-known in mechanical systems) can offer up to three orders of magnitude increase in sensitivity. Therefore, this concept has been recently applied to the design of micromechanical sensors, e.g., for sensitive mass sensing. This paper applies, for the first time in the electrical domain, the concept of monitoring the eigenstates variations in weakly-coupled resonators as a generic readout circuit technique for measuring very small capacitance changes. The outstanding sensitivity of this method is verified analytically and demonstrated using both extensive circuit simulations and experimental measurements. View full abstract»

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  • 46. A High-Efficiency 24 GHz Rectenna Development Towards Millimeter-Wave Energy Harvesting and Wireless Power Transmission

    Publication Year: 2014 , Page(s): 3358 - 3366
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1862 KB) |  | HTML iconHTML  

    This work addresses design and implementation issues of a 24 GHz rectenna, which is developed to demonstrate the feasibility of wireless power harvesting and transmission (WPT) techniques towards millimeter-wave regime. The proposed structure includes a compact circularly polarized substrate integrated waveguide (SIW) cavity-backed antenna array integrated with a self-biased rectifier using commercial Schottky diodes. The antenna and the rectifier are individually designed, optimized, fabricated and measured. Then they are integrated into one circuit in order to validate the studied rectenna architecture. The maximum measured conversion efficiency and DC voltage are respectively equal to 24% and 0.6 V for an input power density of 10 mW/cm2. View full abstract»

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  • 47. Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey

    Publication Year: 2011 , Page(s): 1 - 21
    Cited by:  Papers (35)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1691 KB) |  | HTML iconHTML  

    This paper presents a tutorial overview of ΣΔ modulators, their operating principles and architectures, circuit errors and models, design methods, and practical issues. A review of the state of the art on nanometer CMOS implementations is described, giving a survey of cutting-edge ΣΔ architectures, with emphasis on their application to the next generation of wireless telecom systems. View full abstract»

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  • 48. The Circuit Theory Behind Coupled-Mode Magnetic Resonance-Based Wireless Power Transmission

    Publication Year: 2012 , Page(s): 2065 - 2074
    Cited by:  Papers (43)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2999 KB) |  | HTML iconHTML  

    Inductive coupling is a viable scheme to wirelessly energize devices with a wide range of power requirements from nanowatts in radio frequency identification tags to milliwatts in implantable microelectronic devices, watts in mobile electronics, and kilowatts in electric cars. Several analytical methods for estimating the power transfer efficiency (PTE) across inductive power transmission links have been devised based on circuit and electromagnetic theories by electrical engineers and physicists, respectively. However, a direct side-by-side comparison between these two approaches is lacking. Here, we have analyzed the PTE of a pair of capacitively loaded inductors via reflected load theory (RLT) and compared it with a method known as coupled-mode theory (CMT). We have also derived PTE equations for multiple capacitively loaded inductors based on both RLT and CMT. We have proven that both methods basically result in the same set of equations in steady state and either method can be applied for short- or midrange coupling conditions. We have verified the accuracy of both methods through measurements, and also analyzed the transient response of a pair of capacitively loaded inductors. Our analysis shows that the CMT is only applicable to coils with high quality factor (Q) and large coupling distance. It simplifies the analysis by reducing the order of the differential equations by half compared to the circuit theory. View full abstract»

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  • 49. A Low Phase Noise Injection-Locked Programmable Reference Clock Multiplier With a Two-Phase PVT-Calibrator for \Delta \Sigma PLLs

    Publication Year: 2015 , Page(s): 635 - 644
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    A low phase noise injection-locked reference clock multiplier that can suppress the delta-sigma (ΔΣ) noise of ΔΣ phase-locked loops (PLLs) is proposed. By adopting a two-phase PVT-calibrator that switches the calibration resolution, the clock multiplier can reduce the frequency-acquisition time, as well as tightly regulate the real-time degradation of the phase noise. To improve the performance of the calibration method utilizing two identical oscillators, the self-injection pulse generator that balances the loadings of two oscillators is proposed. In addition, this work presents a systematic design methodology that minimizes the degradation of the phase noise over the PVT variations, based on the phase noise analysis of injection-locking. The clock multiplier was designed with the prototype ΔΣ PLL in the 65-nm CMOS process. It can provide five reference frequencies, i.e., 19.2, 28.8, 48, 57.6, and 96 MHz. The phase noise of the 96-MHz signal was -130.0 and -131.8 dBc/Hz at 100 kHz and 1 MHz offsets, respectively; the performance of low phase noise was confirmed over temperature variations. The total active area was 0.062 mm2, and the power consumption was 1.6-1.9 mW. By switching the reference frequency from 19.2 to 96 MHz, the phase noise of the prototype PLL at the 10-MHz offset from the 4.4-GHz signal was improved from -120.1 to -138.6 dBc/Hz. View full abstract»

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  • 50. A 0.9-/spl mu/A Quiescent Current Output-Capacitorless LDO Regulator With Adaptive Power Transistors in 65-nm CMOS

    Publication Year: 2013 , Page(s): 1072 - 1081
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2451 KB) |  | HTML iconHTML  

    An ultra-low quiescent current output-capacitorless low-dropout (OCL-LDO) regulator with adaptive power transistors technique is presented in this paper. The proposed technique permits the regulator to transform itself between 2-stage and 3-stage cascaded topologies with respective power transistor, depending on the load current condition. As such, it enables the OCL-LDO regulator to achieve ultra-low power consumption, high stability and good transient response without the need of off-chip capacitor at the output. The proposed LDO regulator has been implemented and fabricated in a UMC 65-nm CMOS process. It occupies an active area of 0.017 mm2 . The measured results have shown that the proposed circuit consumes a quiescent current of 0.9 μA at no load, regulating the output at 1 V from a voltage supply of 1.2 V. It achieves full range stability from 0 to 100 mA load current at a maximum 100 pF parasitic capacitance load. The measured transient output voltage is 68.8 mV when load current is stepped from 0 to 100 mA in 300 ns with CL = 100 pF. The recovery time is about 6 μs. Compared to previously reported counterparts, the proposed OCL-LDO regulator shows a significant improvement in term of OCL-LDO transient figure-of-merit (FOM) as well as balanced performance parameters in terms of PSR, line regulation and load regulation. View full abstract»

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The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Shanthi Pavan
Indian Institute of Technology, Madras