# IEEE Transactions on Circuits and Systems I: Regular Papers

Includes the top 50 most frequently accessed documents for this publication according to the usage statistics for the month of

• ### Efficient Hardware Architectures for Deep Convolutional Neural Network

Publication Year: 2018, Page(s):1941 - 1953
Cited by:  Papers (1)
| | PDF (1975 KB) | HTML

Convolutional neural network (CNN) is the state-of-the-art deep learning approach employed in various applications. Real-time CNN implementations in resource limited embedded systems are becoming highly desired recently. To ensure the programmable flexibility and shorten the development period, field programmable gate array is appropriate to implement the CNN models. However, the limited bandwidth... View full abstract»

• ### The flipped voltage follower: a useful cell for low-voltage low-power circuit design

Publication Year: 2005, Page(s):1276 - 1291
Cited by:  Papers (289)  |  Patents (3)
| | PDF (1159 KB) | HTML

In this paper, a basic cell for low-power and/or low-voltage operation is identified. It is evidenced how different versions of this cell, coined as "flipped voltage follower (FVF)" have been used in the past for many applications. A detailed classification of basic topologies derived from the FVF is given. In addition, a comprehensive list of recently proposed low-voltage/low-power CMOS circuits ... View full abstract»

• ### Full On-Chip CMOS Low-Dropout Voltage Regulator

Publication Year: 2007, Page(s):1879 - 1890
Cited by:  Papers (267)  |  Patents (14)
| | PDF (1617 KB) | HTML

This paper proposes a solution to the present bulky external capacitor low-dropout (LDO) voltage regulators with an external capacitorless LDO architecture. The large external capacitor used in typical LDOs is removed allowing for greater power system integration for system-on-chip (SoC) applications. A compensation scheme is presented that provides both a fast transient response and full range al... View full abstract»

• ### Switched-Capacitor/Switched-Inductor Structures for Getting Transformerless Hybrid DC–DC PWM Converters

Publication Year: 2008, Page(s):687 - 696
Cited by:  Papers (487)  |  Patents (1)
| | PDF (1294 KB) | HTML

A few simple switching structures, formed by either two capacitors and two-three diodes (C-switching), or two inductors and two-three diodes (L-switching) are proposed. These structures can be of two types: ldquostep-downrdquo and ldquostep-up.rdquo These blocks are inserted in classical converters: buck, boost, buck-boost, Cuk, Zeta, Sepic. The ldquostep-downrdquo C- or L-switching structures can... View full abstract»

• ### Multi-Rate DEM With Mismatch-Noise Cancellation for DCOs in Digital PLLs

Publication Year: 2018, Page(s):3125 - 3137
| | PDF (2048 KB) | HTML

Mismatches among frequency control elements in digitally-controlled oscillators can be a significant source of phase error in digital phase-locked loops (PLLs). This paper presents a multi-rate dynamic element matching technique and an adaptive mismatch-noise cancellation (MNC) technique that work together to address this problem. The two techniques operate in background during normal PLL operatio... View full abstract»

• ### A Fully Integrated Low-Dropout Regulator With Differentiator-Based Active Zero Compensation

Publication Year: 2018, Page(s):3578 - 3591
| | PDF (4484 KB) | HTML

An area-efficient low-power fully integrated output-capacitorless low-dropout regulator (OCL-LDO) is presented in this paper. The three-stage OCL-LDO utilizes an embedded differentiator-based active zero compensation technique together with adaptive biasing. The proposed active zero compensation helps enhance the unity-gain bandwidth (UGB) of the regulator with very small silicon area and almost n... View full abstract»

• ### A Low-Voltage Low-Phase-Noise 25-GHz Two-Tank Transformer-Feedback VCO

Publication Year: 2018, Page(s):3162 - 3173
| | PDF (3603 KB) | HTML

This paper presents a low-voltage low-phase-noise LC voltage-controlled-oscillator (VCO) with a novel two-tank transformer-feedback topology. The flicker noise up-conversion is suppressed by making the drain impedance of the cross-coupled transistors to be a real number at the second harmonic of the oscillation. The loaded quality factor is boosted and the noise contribution from the transconducto... View full abstract»

• ### A Seven-Octave Broadband LNA MMIC Using Bandwidth Extension Techniques and Improved Active Load

Publication Year: 2018, Page(s):3150 - 3161
| | PDF (3242 KB) | HTML

This paper presents the analysis and design of a novel broadband low-noise amplifier (LNA) with larger than seven-octave bandwidth. To achieve good impedance matching, flat gain, and low noise over larger than seven-octave bandwidth, the combination technique of shunt-resistive feedback, dual inductive-peaking techniques as well as a compact improved active load supporting broadband RF biasing fro... View full abstract»

• ### Consensus of Multiagent Systems and Synchronization of Complex Networks: A Unified Viewpoint

Publication Year: 2010, Page(s):213 - 224
Cited by:  Papers (1037)
| | PDF (1045 KB) | HTML

This paper addresses the consensus problem of multiagent systems with a time-invariant communication topology consisting of general linear node dynamics. A distributed observer-type consensus protocol based on relative output measurements is proposed. A new framework is introduced to address in a unified way the consensus of multiagent systems and the synchronization of complex networks. Under thi... View full abstract»

• ### Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey

Publication Year: 2011, Page(s):1 - 21
Cited by:  Papers (109)  |  Patents (7)
| | PDF (1691 KB) | HTML

This paper presents a tutorial overview of ΣΔ modulators, their operating principles and architectures, circuit errors and models, design methods, and practical issues. A review of the state of the art on nanometer CMOS implementations is described, giving a survey of cutting-edge ΣΔ architectures, with emphasis on their application to the next generation of wireless telecom systems. View full abstract»

• ### Time Domain Processing Techniques Using Ring Oscillator-Based Filter Structures

Publication Year: 2017, Page(s):3003 - 3012
Cited by:  Papers (3)
| | PDF (2197 KB) | HTML

The ability to process time-encoded signals with high fidelity is becoming increasingly important for the time domain (TD) circuit techniques that are used at the advanced nanometer technology nodes. This paper proposes a compact oscillator-based subsystem that performs precise filtering of asynchronous pulse-width modulation encoded signals and makes extensive use of digital logic, enabling low-v... View full abstract»

• ### A Low-Power NB-IoT Transceiver With Digital-Polar Transmitter in 180-nm CMOS

Publication Year: 2017, Page(s):2569 - 2581
Cited by:  Papers (4)
| | PDF (4584 KB) | HTML

A fully integrated 750~960 MHz wireless transceiver (TRX) is presented for single-tone NB-IoT applications. Effective design methodologies and techniques, from the system level to circuit level, are proposed to address various design challenges while achieving low-power consumption. The TRX consists of a low-IF receiver with 180-kHz signal bandwidth, a digital polar transmitter with 3.75-kHz signa... View full abstract»

• ### Event-Triggered Control for Consensus Problem in Multi-Agent Systems With Quantized Relative State Measurements and External Disturbance

Publication Year: 2018, Page(s):2232 - 2242
Cited by:  Papers (3)
| | PDF (3683 KB) | HTML

For decreasing communication load and overcoming network constrains, such as the limited bandwidth and data loss in multi-agent networks, this paper integrates the two control strategies to investigate the bounded consensus problem of multi-agent systems (MASs) with external disturbance on the basis of an undirected graph, namely, the quantized control and the event-triggered control. In the exist... View full abstract»

• ### Understanding Phase Error and Jitter: Definitions, Implications, Simulations, and Measurement

Publication Year: 2018, Page(s):1 - 19
| | PDF (1732 KB)

Precision oscillators are ubiquitous in modern electronic systems, and their accuracy often limits the performance of such systems. Hence, a deep understanding of how oscillator performance is quantified, simulated, and measured, and how it affects the system performance is essential for designers. Unfortunately, the necessary information is spread thinly across the published literature and textbo... View full abstract»

• ### Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures

Publication Year: 2008, Page(s):1441 - 1454
Cited by:  Papers (114)  |  Patents (2)
| | PDF (1188 KB) | HTML

The need for highly integrable and programmable analog-to-digital converters (ADCs) is pushing towards the use of dynamic regenerative comparators to maximize speed, power efficiency and reconfigurability. Comparator thermal noise is, however, a limiting factor for the achievable resolution of several ADC architectures with scaled supply voltages. While mismatch in these comparators can be compens... View full abstract»

• ### A Low-Power, Wireless, Capacitive Sensing Frontend Based on a Self-Oscillating Inductive Link

Publication Year: 2018, Page(s):2645 - 2656
| | PDF (3512 KB) | HTML

Wireless sensing systems are becoming popular in a range of applications, particularly in the case of biomedical circuits and food monitoring systems. A typical wireless sensing system, however, may require considerable complexity to perform the necessary analog to digital conversion and subsequent wireless transmission. Alternatively, in the case of inductive link based systems, large, manually o... View full abstract»

• ### Degradation of Alias Rejection in Continuous-Time Delta–Sigma Modulators by Weak Loop-Filter Nonlinearities

Publication Year: 2018, Page(s):3207 - 3215
| | PDF (1992 KB) | HTML

Implicit anti-aliasing is a remarkable property of continuous-time delta–sigma modulators employing a time-invariant loop filter. It turns out that weak nonlinearity of the operational transconductance amplifier (OTA) used in the input integrator, in conjunction with the DAC pulse shape and OTA parasitics can greatly degrade the alias rejection of the modulator. The authors report and analyze this... View full abstract»

• ### A Self-Powered Supply-Sensing Biosensor Platform Using Bio Fuel Cell and Low-Voltage, Low-Cost CMOS Supply-Controlled Ring Oscillator With Inductive-Coupling Transmitter for Healthcare IoT

Publication Year: 2018, Page(s):2784 - 2796
Cited by:  Papers (2)
| | PDF (4093 KB) | HTML

This paper proposes a self-powered disposable supply-sensing biosensor platform for big-data-based healthcare applications. The proposed supply-sensing biosensor platform is based on bio fuel cells and a 0.23-V 0.25-μm zero-Vthall-digital CMOS supply-controlled ring oscillator with a current-driven pulse-interval-modulated inductive-coupling transmitter. The fully digital, and current-d... View full abstract»

• ### Homeostatic Fault Tolerance in Spiking Neural Networks: A Dynamic Hardware Perspective

Publication Year: 2018, Page(s):687 - 699
| | PDF (2824 KB) | HTML

Fault tolerance is a remarkable feature of biological systems and their self-repair capability influence modern electronic systems. In this paper, we propose a novel plastic neural network model, which establishes homeostasis in a spiking neural network. Combined with this plasticity and the inspiration from inhibitory interneurons, we develop a fault-resilient robotic controller implemented on an... View full abstract»

• ### A Mixed-Signal Circuit Technique for Cancellation of Interferers Modulated by LO Phase-Noise in 4G/5G CA Transceivers

Publication Year: 2018, Page(s):3745 - 3755
| | PDF (3461 KB) | HTML

In RF transceivers operating in carrier-aggregation, spurs are generated on the transceiver chip which may down-convert any blocker signal located at the spur frequency into the receiver baseband. The blocker signal could either be the transceiver’s own transmit signal when operating in frequency-division duplex, or a WiFi-related signal received by the antenna. This so-called modulated spur inter... View full abstract»

• ### Generalized Analysis of High-Order Switch-RC$N$-Path Mixers/Filters Using the Adjoint Network

Publication Year: 2018, Page(s):3267 - 3278
| | PDF (2425 KB) | HTML

This paper presents a systematic method to analyze N-path mixers and filters consisting of periodically switched RC-networks of arbitrary order. It is assumed that each capacitor periodically exchanges charge with the rest of the network during the on-phase of the switching clock, then samples its charge, and holds it perfectly until the next on-phase. This assumption allows for using the adjoint ... View full abstract»

• ### A 2.5-GHz CMOS Full-Duplex Front-End for Asymmetric Data Networks

Publication Year: 2018, Page(s):3174 - 3185
| | PDF (2998 KB) | HTML

Electrical balance-based full-duplex front-end allows high power operation but has strong tradeoff between Tx and Rx insertion loss. In this paper, we present a capacitive bridge-based duplexer for full-duplex operation with tunable Tx/Rx insertion loss to improve link budget in an asymmetric data network. Theoretical analysis is done to show that capacitive bridge-based duplexer can be better tha... View full abstract»

• ### A 0.19 mm210 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS

Publication Year: 2018, Page(s):3606 - 3616
| | PDF (3338 KB) | HTML

This paper presents a 2.3 GS/s 12-way time-interleaved pipelined-SAR ADC achieving 1.1 GHz input bandwidth with 47.4 dB signal-to-noise distortion ratio (SNDR). Here, we propose a hierarchical interleaving with passively shared sub-sampling front-end to eliminate the timing skews, thus avoiding the timing calibration for design simplicity as well as better area and power efficiency. To provide a f... View full abstract»

• ### A Phasor-Based Analysis of Sinusoidal Injection Locking in LC and Ring Oscillators

Publication Year: 2018, Page(s):1 - 14
| | PDF (2248 KB)

A new perspective into the locking behavior of LC and ring oscillators is presented. By decomposing a sinusoidal injection current into in-phase and quadrature-phase components, exact expressions for the amplitude and phase of an injection-locked LC oscillator which hold for any injection strength and frequency are derived and confirmed by simulation. The analysis, which can be naturally extended ... View full abstract»

• ### Digitally Assisted On-Chip Body Bias Tuning Scheme for Ultra Low-Power VLSI Systems

Publication Year: 2018, Page(s):3241 - 3254
| | PDF (3144 KB) | HTML

Body bias control is one of the most efficient means to reduce leakage power, adjust process variation, and apply performance boost. However, such control incurs a certain power overhead that has to be reduced, especially in ultra low-power systems. In order to exploit the advantages of body bias control while guaranteeing power efficiency, an on-chip control scheme is required. Conventionally, on... View full abstract»

• ### A Wideband Inductorless dB-Linear Automatic Gain Control Amplifier Using a Single-Branch Negative Exponential Generator for Wireline Applications

Publication Year: 2018, Page(s):3196 - 3206
| | PDF (3525 KB) | HTML

This paper reports a wideband inductorless automatic gain control (AGC) amplifier for wireline applications. To realize a dB-linear AGC range, a pseudo-folded Gilbert cell driven by a single-branch negative exponential generator (NEG) is proposed as the core variable-gain amplifier. The NEG features a composite of dual Taylor series to extend the AGC approximation range without sacrificing the pre... View full abstract»

• ### Analysis and Modeling of Chopping Phase Non-Overlap in Continuous-Time$\Delta\Sigma$Modulators

Publication Year: 2018, Page(s):3216 - 3226
| | PDF (1768 KB) | HTML

Chopping is a technique to reduce offset and flicker noise in amplifiers by up-converting them to higher frequency, and subsequently filtering them out. A typical chopping implementation uses two complementary phases which have a finite non-overlap time in between them. When such a chopping phase is used in the first integrator of a continuous-time delta sigma modulator, the non-overlap time can s... View full abstract»

• ### A Study on the Design Parameters for MEMS Oscillators Incorporating Nonlinearities

Publication Year: 2018, Page(s):3424 - 3434
| | PDF (4020 KB) | HTML

This paper presents a comprehensive study on the design parameters for MEMS oscillators incorporating nonlinear mechanisms. Three different CMOS amplifier topologies in tandem with double-ended tuning-fork resonators are developed to perform a general study, thus revealing the CMOS circuit design scenarios for low phase noise. The close-to-carrier phase noise cancellation is experimentally demonst... View full abstract»

• ### Theory and applications of incremental /spl Delta//spl Sigma/ converters

Publication Year: 2004, Page(s):678 - 690
Cited by:  Papers (150)  |  Patents (9)
| | PDF (407 KB) | HTML

Analog-Digital (A/D) converters used in instrumentation and measurements often require high absolute accuracy, including very high linearity and negligible dc offset. The realization of high-resolution Nyquist-rate converters becomes very expensive when the resolution exceeds 16 bits. The conventional delta-sigma (/spl Delta//spl Sigma/) structures used in telecommunication and audio applications ... View full abstract»

• ### Data and Hardware Efficient Design for Convolutional Neural Network

Publication Year: 2018, Page(s):1642 - 1651
Cited by:  Papers (1)
| | PDF (4894 KB) | HTML

Hardware design of deep convolutional neural networks (CNNs) faces challenges of high computational complexity and data bandwidth as well as huge divergence in different CNN network layers, in which the throughput of the convolutional layer would be bounded by available hardware resource, and throughput of the fully connected layer would be bounded by available data bandwidth. Thus, a highly flexi... View full abstract»

• ### A Low Phase Noise and Wide Tuning Range Millimeter-Wave VCO Using Switchable Coupled VCO-Cores

Publication Year: 2015, Page(s):554 - 563
Cited by:  Papers (15)
| | PDF (2588 KB) | HTML

This work presents a millimeter-wave (mm-wave) dual-mode voltage-controlled oscillator (VCO) topology with switchable coupled VCO-cores for wide frequency tuning range and low phase noise application. By taking advantage of the different parasitic capacitance of cross-coupled pair when the VCO-core operates in ON and OFF states, the dual-mode operation of VCO can be realized, and the oscillations ... View full abstract»

• ### Development of Single-Transistor-Control LDO Based on Flipped Voltage Follower for SoC

Publication Year: 2008, Page(s):1392 - 1401
Cited by:  Papers (90)  |  Patents (3)
| | PDF (2180 KB) | HTML

The design issues of a single-transistor-control (STC) low-drop-out (LDO) based on flipped voltage follower is discussed in this paper, in particular the feedback stability at different conditions of output capacitors, equivalent series resistances (ESRs) and load current. Based on the analysis, an STC LDO was implemented in a standard 0.35-mum MOS technology. It is proven experimentally that the ... View full abstract»

• ### Design and Implementation of a 0.3-V Differential Difference Amplifier

Publication Year: 2018, Page(s):1 - 11
| | PDF (2370 KB)

A new silicon realization of an ultra-low-voltage and ultra-low-power differential-difference amplifier (DDA) is presented in this paper. The circuit combines the idea of non-tailed bulk-driven differential pairs with a partial positive feedback used for voltage gain boosting. The DDA operates from VDD ranging from 0.3 to 0.5 V. For a 0.3-V version, the circuit provides measured DC voltage gain la... View full abstract»

• ### A 93% Peak Efficiency Fully-Integrated Multilevel Multistate Hybrid DC–DC Converter

Publication Year: 2018, Page(s):2617 - 2630
| | PDF (4923 KB) | HTML

The general structure of a multilevel multistate dc- dc converter is introduced, which is a hybrid between inductor-based (buck) converters and capacitor-based (switched capacitor) converters. The control of the new converter is hybrid between switched capacitor converters and buck converters, where the coarse tuning of the output voltage is achieved through the selection of an appropriate operati... View full abstract»

• ### An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with −55 dBc Fractional and −91 dBc Reference Spurs

Publication Year: 2018, Page(s):3756 - 3768
| | PDF (4910 KB) | HTML

We propose a time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios, which is optimized for advanced CMOS. It is based on a 1/8-length time-to-digital converter (TDC) of stabilized 7-ps resolution, as well as wide tuning range, and fine-resolution class-F digitally controlled oscillator (DCO) with only switchable metal capacitors. The 0.4-mW TDC clocked at 40 MHz maintains ... View full abstract»

• ### Consensus Tracking of Multi-Agent Systems With Lipschitz-Type Node Dynamics and Switching Topologies

Publication Year: 2014, Page(s):499 - 511
Cited by:  Papers (338)
| | PDF (3732 KB) | HTML

Distributed consensus tracking is addressed in this paper for multi-agent systems with Lipschitz-type node dynamics. The main contribution of this work is solving the consensus tracking problem without the assumption that the topology among followers is strongly connected and fixed. By using tools from M-matrix theory, a class of consensus tracking protocols based only on the relative states among... View full abstract»

• ### A Reconfigurable Streaming Deep Convolutional Neural Network Accelerator for Internet of Things

Publication Year: 2018, Page(s):198 - 208
Cited by:  Papers (2)
| | PDF (2922 KB) | HTML

Convolutional neural network (CNN) offers significant accuracy in image detection. To implement image detection using CNN in the Internet of Things (IoT) devices, a streaming hardware accelerator is proposed. The proposed accelerator optimizes the energy efficiency by avoiding unnecessary data movement. With unique filter decomposition technique, the accelerator can support arbitrary convolution w... View full abstract»

• ### Demystifying and Mitigating Code-Dependent Switching Distortions in Current-Steering DACs

Publication Year: 2018, Page(s):1 - 14
| | PDF (4404 KB)

This paper analyzes the intermodulation between the element transition rate and the output-dependent unit switching distortion, i.e., the switching distortion of one switching unit, in current-steering digital-to-analog converters (DACs). The analysis and experimental results reveal how this intermodulation affects the DAC linearity. Based on this, we also propose a technique, termed random pairwi... View full abstract»

• ### TEAM: ThrEshold Adaptive Memristor Model

Publication Year: 2013, Page(s):211 - 221
Cited by:  Papers (226)  |  Patents (1)
| | PDF (2472 KB) | HTML

Memristive devices are novel devices, which can be used in applications ranging from memory and logic to neuromorphic systems. A memristive device offers several advantages: nonvolatility, good scalability, effectively no leakage current, and compatibility with CMOS technology, both electrically and in terms of manufacturing. Several models for memristive devices have been developed and are discus... View full abstract»

• ### Analysis and Design of Voltage-Controlled Oscillator Based Analog-to-Digital Converter

Publication Year: 2010, Page(s):18 - 30
Cited by:  Papers (108)  |  Patents (5)
| | PDF (1424 KB) | HTML

A voltage-controlled oscillator (VCO) based analog-to-digital converter (ADC) is a time-based architecture with a first-order noise-shaping property, which can be implemented using a VCO and digital circuits. This paper analyzes the performance of VCO-based ADCs in the presence of nonidealities such as jitter, nonlinearity, mismatch, and the metastability of D flip-flops. Based on this analysis, d... View full abstract»

• ### Area-Efficient Time-Shared Digital-to-Analog Converter With Dual Sampling for AMOLED Column Driver IC’s

Publication Year: 2018, Page(s):3227 - 3240
| | PDF (3950 KB) | HTML

This paper presents a 24-channel time-shared 8-bit digital-to-analog converter (DAC) with dual sampling to minimize the effective channel area of the column driver integrated circuit (IC) for high-resolution active-matrix organic light emitting diodes (AMOLED). The proposed time-shared DAC significantly reduces the effective channel area of the column driver IC, since a single high-speed DAC is sh... View full abstract»

Publication Year: 2016, Page(s):763 - 772
Cited by:  Papers (5)
| | PDF (1936 KB) | HTML

Small metal-oxide-metal (MOM) capacitors are essential to energy-efficient mixed-signal integrated circuit design. However, only few reports discuss their matching properties based on large sets of measured data. In this paper, we report matching properties of femtofarad and sub-femtofarad MOM vertical-field parallel-plate capacitors and lateral-field fringing capacitors. We study the effect of bo... View full abstract»

• ### A 50-MHz-1-GHz 2.3-dB NF Noise-Cancelling Balun-LNA Employing a Modified Current-Bleeding Technique and Balanced Loads

Publication Year: 2018, Page(s):1 - 9
| | PDF (2935 KB)

A new noise-cancelling method that employs a modified current-bleeding (CBLD) technique and balanced loads is presented by developing a design for a low-noise and high-linearity balun-low-noise amplifier (LNA) for broadband applications. The basic common-gate (CG)-common-source (CS) balun topology cannot achieve a noise figure (NF) of less than 3 dB. Thus, a practical topology containing a CS tran... View full abstract»

• ### An Architecture to Accelerate Convolution in Deep Neural Networks

Publication Year: 2018, Page(s):1349 - 1362
Cited by:  Papers (1)
| | PDF (3035 KB) | HTML

In the past few years, the demand for real-time hardware implementations of deep neural networks (DNNs), especially convolutional neural networks (CNNs), has dramatically increased, thanks to their excellent performance on a wide range of recognition and classification tasks. When considering real-time action recognition and video/image classification systems, latency is of paramount importance. T... View full abstract»

• ### Linearization Techniques for CMOS Low Noise Amplifiers: A Tutorial

Publication Year: 2011, Page(s):22 - 36
Cited by:  Papers (142)  |  Patents (4)
| | PDF (1569 KB) | HTML

This tutorial catalogues and analyzes previously reported CMOS low noise amplifier (LNA) linearization techniques. These techniques comprise eight categories: a) feedback; b) harmonic termination; c) optimum biasing; d) feedforward; e) derivative superposition (DS); f) IM2 injection; g) noise/distortion cancellation; and h) post-distortion. This paper also addresses broadband-LNA-linearization iss... View full abstract»

• ### A Monolithic High-Voltage Li-Ion Battery Charger With Sharp Mode Transition and Partial Current Control Technique

Publication Year: 2018, Page(s):3099 - 3109
| | PDF (4589 KB) | HTML

A high-voltage (HV) lithium-ion battery charger control chip with sharp mode transition and partial current control technique is proposed in this paper. The proposed sharp mode transition eliminates the transition region between constant current (CC) and constant voltage (CV) stages in traditional CC-CV chargers. This technique reduces the charging time and simplifies the compensator design. Furth... View full abstract»

• ### Power and Conjugately Matched High Band UWB Power Amplifier

Publication Year: 2018, Page(s):3138 - 3149
| | PDF (2202 KB) | HTML

A common source RF amplifier can be designed to be either power or conjugately matched at the output but not both, since the required load impedances are distinct. In this paper, we have shown that using a drain-gate feedback network brings the power and conjugate match impedances closer together, up to a point where they coincide at a cost of slightly decreased efficiency. We have thoroughly anal... View full abstract»

• ### Simulation and Analysis of Random Decision Errors in Clocked Comparators

Publication Year: 2009, Page(s):1844 - 1857
Cited by:  Papers (51)  |  Patents (2)
| | PDF (1565 KB) | HTML

Clocked comparators have found widespread use in noise sensitive applications including analog-to-digital converters, wireline receivers, and memory bit-line detectors. However, their nonlinear, time-varying dynamics resulting in discrete output levels have discouraged the use of traditional linear time-invariant (LTI) small-signal analysis and noise simulation techniques. This paper describes a l... View full abstract»

• ### A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS

Publication Year: 2018, Page(s):2109 - 2117
| | PDF (3261 KB) | HTML

This paper presents a PLL supporting diverse low-power clocking needs including wide input (6-200 MHz) and output (0.15-5 GHz) frequency ranges and SSC operation. Fabricated in 14nm FinFET CMOS, a low-power switched-cap loop filter is employed to enable high -3dB PLL bandwidth (&gt;40% of f<sub>REF</sub> = 19.2 MHz), and the proposed reference current generator (IrefGen) provides a... View full abstract»

• ### Near-Field MIMO Communication Links

Publication Year: 2018, Page(s):3027 - 3036
| | PDF (3176 KB) | HTML

A procedure to achieve near-field multiple input multiple output (MIMO) communication with equally strong channels is demonstrated in this paper. This has applications in near-field wireless communications, such as Chip-to-Chip (C2C) communication or wireless links between printed circuit boards. Designing the architecture of these wireless C2C networks is, however, based on standard engineering d... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK