IEEE Transactions on Circuits and Systems I: Regular Papers

Includes the top 50 most frequently accessed documents for this publication according to the usage statistics for the month of

• Time Domain Processing Techniques Using Ring Oscillator-Based Filter Structures

Publication Year: 2017, Page(s):3003 - 3012
Cited by:  Papers (1)
| | PDF (2197 KB) | HTML

The ability to process time-encoded signals with high fidelity is becoming increasingly important for the time domain (TD) circuit techniques that are used at the advanced nanometer technology nodes. This paper proposes a compact oscillator-based subsystem that performs precise filtering of asynchronous pulse-width modulation encoded signals and makes extensive use of digital logic, enabling low-v... View full abstract»

• Full On-Chip CMOS Low-Dropout Voltage Regulator

Publication Year: 2007, Page(s):1879 - 1890
Cited by:  Papers (264)  |  Patents (14)
| | PDF (1617 KB) | HTML

This paper proposes a solution to the present bulky external capacitor low-dropout (LDO) voltage regulators with an external capacitorless LDO architecture. The large external capacitor used in typical LDOs is removed allowing for greater power system integration for system-on-chip (SoC) applications. A compensation scheme is presented that provides both a fast transient response and full range al... View full abstract»

• IMAGING-In-Memory AlGorithms for Image processiNG

Publication Year: 2018, Page(s):1 - 14
| | PDF (3438 KB)

Data-intensive applications such as image processing suffer from massive data movement between memory and processing units. The severe limitations on system performance and energy efficiency imposed by this data movement are further exacerbated with any increase in the distance the data must travel. This data transfer and its associated obstacles could be eliminated by the use of emerging non-vola... View full abstract»

• Efficient Hardware Architectures for Deep Convolutional Neural Network

Publication Year: 2018, Page(s):1941 - 1953
| | PDF (1975 KB) | HTML

Convolutional neural network (CNN) is the state-of-the-art deep learning approach employed in various applications. Real-time CNN implementations in resource limited embedded systems are becoming highly desired recently. To ensure the programmable flexibility and shorten the development period, field programmable gate array is appropriate to implement the CNN models. However, the limited bandwidth... View full abstract»

• The flipped voltage follower: a useful cell for low-voltage low-power circuit design

Publication Year: 2005, Page(s):1276 - 1291
Cited by:  Papers (281)  |  Patents (3)
| | PDF (1159 KB) | HTML

In this paper, a basic cell for low-power and/or low-voltage operation is identified. It is evidenced how different versions of this cell, coined as "flipped voltage follower (FVF)" have been used in the past for many applications. A detailed classification of basic topologies derived from the FVF is given. In addition, a comprehensive list of recently proposed low-voltage/low-power CMOS circuits ... View full abstract»

• A 0.49–13.3 MHz Tunable Fourth-Order LPF with Complex Poles Achieving 28.7 dBm OIP3

Publication Year: 2018, Page(s):2353 - 2364
| | PDF (5220 KB) | HTML

A novel switched-capacitor low-pass filter architecture is presented. In the proposed scheme, a feedback path is added to a charge-rotating real-pole filter to implement complex poles. The selectivity is enhanced, and the in-band loss is reduced compared with the real-pole filter. The output thermal noise level and the tuning range are both close to those of the real-pole filter. These features ma... View full abstract»

• Low-Power Single-Ended SAR ADC Using Symmetrical DAC Switching for Image Sensors With Passive CDS and PGA Technique

Publication Year: 2018, Page(s):2378 - 2388
Cited by:  Papers (1)
| | PDF (4289 KB) | HTML

An integrated, power-saving SAR analog-to-digital converter suitable for image sensor applications is presented in this paper. In comparison with previous works, the proposed, build-in passive correlated double sampling (CDS) and programmable gain amplifying (PGA) technique is superior in power, as it achieves correlated noise cancellation and signal amplification without additional OTAs. Furtherm... View full abstract»

• All-Digital Blind Background Calibration Technique for Any Channel Time-Interleaved ADC

Publication Year: 2018, Page(s):2503 - 2514
| | PDF (3129 KB) | HTML

This paper proposes a novel digital adaptive blind background calibration technique for the gain, timing skew, and offset mismatch errors in a time-interleaved analog-to-digital converter (TI-ADC). Based on the frequency-shifted basis functions generated only from the measured TI-ADC output, the three mismatch errors can be represented, extracted, and then subtracted from the TI-ADC output adaptiv... View full abstract»

• A 93% Peak Efficiency Fully-Integrated Multilevel Multistate Hybrid DC–DC Converter

Publication Year: 2018, Page(s):2617 - 2630
| | PDF (4923 KB) | HTML

The general structure of a multilevel multistate dc- dc converter is introduced, which is a hybrid between inductor-based (buck) converters and capacitor-based (switched capacitor) converters. The control of the new converter is hybrid between switched capacitor converters and buck converters, where the coarse tuning of the output voltage is achieved through the selection of an appropriate operati... View full abstract»

• A 12 mV Input, 90.8% Peak Efficiency CRM Boost Converter With a Sub-Threshold Startup Voltage for TEG Energy Harvesting

Publication Year: 2018, Page(s):2631 - 2640
| | PDF (2618 KB) | HTML

This paper proposed a high efficiency boost converter targeting thermoelectric generator energy harvesting. The proposed converter adopts the critical conduction mode rather than the discontinuous mode to reduce the conduction loss, which can improve the peak efficiency at high input power. To reduce the minimum input voltage, an adaptive on-resistance switch, which can automatically change the hi... View full abstract»

• A Systematic Design Method for Direct Delta-Sigma Receivers

Publication Year: 2018, Page(s):2389 - 2402
| | PDF (3775 KB) | HTML

Next generation receivers, such as the direct ΔΣ receiver (DDSR), shift the boundary between analog and digital closer to the antenna by merging the functionalities of different sub-blocks. In the DDSR, the analog components are used to their maximum potential as each stage participates in amplification, blocker filtering, anti-aliasing, and quantization noise shaping simultaneously, resulting in ... View full abstract»

• Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures

Publication Year: 2008, Page(s):1441 - 1454
Cited by:  Papers (112)  |  Patents (2)
| | PDF (1188 KB) | HTML

The need for highly integrable and programmable analog-to-digital converters (ADCs) is pushing towards the use of dynamic regenerative comparators to maximize speed, power efficiency and reconfigurability. Comparator thermal noise is, however, a limiting factor for the achievable resolution of several ADC architectures with scaled supply voltages. While mismatch in these comparators can be compens... View full abstract»

• Switched-Capacitor/Switched-Inductor Structures for Getting Transformerless Hybrid DC–DC PWM Converters

Publication Year: 2008, Page(s):687 - 696
Cited by:  Papers (478)  |  Patents (1)
| | PDF (1294 KB) | HTML

A few simple switching structures, formed by either two capacitors and two-three diodes (C-switching), or two inductors and two-three diodes (L-switching) are proposed. These structures can be of two types: ldquostep-downrdquo and ldquostep-up.rdquo These blocks are inserted in classical converters: buck, boost, buck-boost, Cuk, Zeta, Sepic. The ldquostep-downrdquo C- or L-switching structures can... View full abstract»

• A 53 dB$\Omega~7$-GHz Inductorless Transimpedance Amplifier and a 1-THz+ GBP Limiting Amplifier in 0.13-$\mu$m CMOS

Publication Year: 2018, Page(s):2365 - 2377
| | PDF (7988 KB) | HTML

An inductorless 10-Gb/s optical receiver including a novel transimpedance amplifier (TIA) with dual feedback loop and a limiting amplifier with third-order nested feedback is presented. The current-buffer-based TIA employs an active CherryHooper stage in the auxiliary amplifier and reuses the tail current source to achieve 10 Gb/s operation in the presence of a 1 pF photodiode input capacitance. S... View full abstract»

• Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey

Publication Year: 2011, Page(s):1 - 21
Cited by:  Papers (105)  |  Patents (7)
| | PDF (1691 KB) | HTML

This paper presents a tutorial overview of ΣΔ modulators, their operating principles and architectures, circuit errors and models, design methods, and practical issues. A review of the state of the art on nanometer CMOS implementations is described, giving a survey of cutting-edge ΣΔ architectures, with emphasis on their application to the next generation of wireless telecom systems. View full abstract»

• Power Bounds and Energy Efficiency in Incremental &#x0394;&#x03A3; Analog-to-Digital Converters

Publication Year: 2018, Page(s):1 - 11
| | PDF (1709 KB)

Incremental analog-to-digital-converters (IADCs) are variants of &#x25B3;&#x03A3; ADCs, which have been increasingly used for low-power sensory applications in recent years. Most IADC applications require high resolution and high energy efficiency. In this paper, we present a systematic analysis of IADCs. We derive analytical design equations for practical IADC designs. Process limitations... View full abstract»

• Event-Triggered Control for Consensus Problem in Multi-Agent Systems With Quantized Relative State Measurements and External Disturbance

Publication Year: 2018, Page(s):2232 - 2242
Cited by:  Papers (1)
| | PDF (3683 KB) | HTML

For decreasing communication load and overcoming network constrains, such as the limited bandwidth and data loss in multi-agent networks, this paper integrates the two control strategies to investigate the bounded consensus problem of multi-agent systems (MASs) with external disturbance on the basis of an undirected graph, namely, the quantized control and the event-triggered control. In the exist... View full abstract»

• Consensus of Multiagent Systems and Synchronization of Complex Networks: A Unified Viewpoint

Publication Year: 2010, Page(s):213 - 224
Cited by:  Papers (999)
| | PDF (1045 KB) | HTML

This paper addresses the consensus problem of multiagent systems with a time-invariant communication topology consisting of general linear node dynamics. A distributed observer-type consensus protocol based on relative output measurements is proposed. A new framework is introduced to address in a unified way the consensus of multiagent systems and the synchronization of complex networks. Under thi... View full abstract»

• A Fully On-Chip Digitally Assisted LDO Regulator With Improved Regulation and Transient Responses

Publication Year: 2018, Page(s):1 - 8
| | PDF (2795 KB)

This paper presents a fully on-chip mixed-mode low-dropout (LDO) regulator with improved regulation and transient responses. With the help of the digital regulation part, the supported maximum load current is significantly improved, while the chip area overhead is very small. A Miller compensation capacitor and a buffer stage are used to achieve stability and improve power MOS gate slew rate. The ... View full abstract»

• X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories

Publication Year: 2018, Page(s):1 - 14
| | PDF (3651 KB)

Silicon-based static random access memories (SRAM) and digital Boolean logic have been the workhorse of the state-of-the-art computing platforms. Despite tremendous strides in scaling the ubiquitous metal-oxide-semiconductor transistor, the underlying von-Neumann computing architecture has remained unchanged. The limited throughput and energy-efficiency of the state-of-the-art computing systems, t... View full abstract»

• A Reconfigurable Streaming Deep Convolutional Neural Network Accelerator for Internet of Things

Publication Year: 2018, Page(s):198 - 208
Cited by:  Papers (1)
| | PDF (2922 KB) | HTML

Convolutional neural network (CNN) offers significant accuracy in image detection. To implement image detection using CNN in the Internet of Things (IoT) devices, a streaming hardware accelerator is proposed. The proposed accelerator optimizes the energy efficiency by avoiding unnecessary data movement. With unique filter decomposition technique, the accelerator can support arbitrary convolution w... View full abstract»

• Comprehensive Analysis of Distortion in the Passive FET Sample-and-Hold Circuit

Publication Year: 2018, Page(s):1157 - 1173
| | PDF (7127 KB) | HTML

Analysis simplified with circuit insights reveals the major sources of distortion in a passive FET-switch-based sampling circuit: 1) $R_{\mathrm{\scriptscriptstyle ON}}$ -modulation; 2) turn-OFF-time instant; and 3) signal-dependent charge-injection. Explicit expressions for second- and third-order distortions advance intuitive understanding of the processes of distortion. Circuit simulations and ... View full abstract»

• Homeostatic Fault Tolerance in Spiking Neural Networks: A Dynamic Hardware Perspective

Publication Year: 2018, Page(s):687 - 699
| | PDF (2824 KB) | HTML

Fault tolerance is a remarkable feature of biological systems and their self-repair capability influence modern electronic systems. In this paper, we propose a novel plastic neural network model, which establishes homeostasis in a spiking neural network. Combined with this plasticity and the inspiration from inhibitory interneurons, we develop a fault-resilient robotic controller implemented on an... View full abstract»

• Simplified Unified Analysis of Switched-RC Passive Mixers, Samplers, and $N$ -Path Filters Using the Adjoint Network

Publication Year: 2017, Page(s):2714 - 2725
Cited by:  Papers (2)
| | PDF (2173 KB) | HTML

Recent innovations in software defined CMOS radio transceiver architectures heavily rely on high-linearity switched-RC sampler and passive-mixer circuits, driven by digitally programmable multiphase clocks. Although seemingly simple, the frequency domain analysis of these linear periodically time variant (LPTV) circuits is often deceptively complex. This paper uses the properties of sampled LPTV s... View full abstract»

• 40-nm CMOS Wideband High-IF Receiver Using a Modified Charge-Sharing Bandpass Filter to Boost Q-Factor

Publication Year: 2018, Page(s):2581 - 2591
| | PDF (3056 KB) | HTML

A 40-nm CMOS wideband high-IF receiver is presented in this paper. The low-noise transconductance amplifier (LNTA) uses dual noise cancellation in order to improve its noise figure. The LNTA has also a folded-cascode structure to increase its output impedance and prepare for a current-mode passive mixer. This structure is merged into the output stage of the LNTA, so there is no need for extra tran... View full abstract»

• Low$1/f^{3}$Phase Noise Quadrature LC VCOs

Publication Year: 2018, Page(s):2127 - 2138
| | PDF (2475 KB) | HTML

Series-coupled quadrature LC voltage-controlled oscillators(SQVCOs) perform robustly over a wide tuning range, but have a higher 1/f3phase noise than their single-phase counterparts. Switching transistors inject noise into the tank only once per cycle leading to an asymmetric impulse sensitivity function(ISF) and large flicker noise upconversion. Circuit topologies with additional capac... View full abstract»

• Analysis and Design of Voltage-Controlled Oscillator Based Analog-to-Digital Converter

Publication Year: 2010, Page(s):18 - 30
Cited by:  Papers (106)  |  Patents (5)
| | PDF (1424 KB) | HTML

A voltage-controlled oscillator (VCO) based analog-to-digital converter (ADC) is a time-based architecture with a first-order noise-shaping property, which can be implemented using a VCO and digital circuits. This paper analyzes the performance of VCO-based ADCs in the presence of nonidealities such as jitter, nonlinearity, mismatch, and the metastability of D flip-flops. Based on this analysis, d... View full abstract»

• Approximate Multipliers Based on New Approximate Compressors

Publication Year: 2018, Page(s):1 - 14
| | PDF (5241 KB)

Approximate computing is an emerging trend in digital design that trades off the requirement of exact computation for improved speed and power performance. This paper proposes novel approximate compressors and an algorithm to exploit them for the design of efficient approximate multipliers. By using the proposed approach, we have synthesized approximate multipliers for several operand lengths usin... View full abstract»

• An 11-Bit 250-nW 10-kS/s SAR ADC With Doubled Input Range for Biomedical Applications

Publication Year: 2018, Page(s):61 - 73
Cited by:  Papers (1)
| | PDF (2856 KB) | HTML

This paper presents a low-power, area-efficient 11-b single-ended successive-approximation-register (SAR) analog-todigital converter (ADC) targeted for biomedical applications. The design features an energy-efficient switching technique with an error cancelling capacitor network. The input range is twice the reference voltage. The ADC's loading of the previous stage is reduced by using a single-en... View full abstract»

• An Architecture to Accelerate Convolution in Deep Neural Networks

Publication Year: 2018, Page(s):1349 - 1362
| | PDF (3035 KB) | HTML

In the past few years, the demand for real-time hardware implementations of deep neural networks (DNNs), especially convolutional neural networks (CNNs), has dramatically increased, thanks to their excellent performance on a wide range of recognition and classification tasks. When considering real-time action recognition and video/image classification systems, latency is of paramount importance. T... View full abstract»

• Integrated ExG, Vibration and Temperature Measurement Front-End for Wearable Sensing

Publication Year: 2018, Page(s):2422 - 2430
| | PDF (3740 KB) | HTML

This paper presents a programmable CMOS integrated front-end ASIC targeting the acquisition of signals in biomedical applications, including rehabilitation and treadmill exercise monitoring. The analog front-end is combined with a commercial microcontroller for clock generation, signal processing, and feedback generation. The ASIC provides a unique combination of sensing interfaces, including a dc... View full abstract»

• A Novel Transmitter Architecture for Spectrally-Precoded OFDM

Publication Year: 2018, Page(s):2592 - 2605
| | PDF (3094 KB) | HTML

Frequency nulling spectral precoding is an approach that suppresses the out-of-band emission in orthogonal frequency division (OFDM) systems. In this paper, we discuss the transmitter architecture of the spectrally precoded OFDM systems. We design a novel precoder that matches the practical implementation of the OFDM modulator. We show that spectral precoding can relax the analog low pass filterin... View full abstract»

• A Low-Power, Wireless, Capacitive Sensing Frontend Based on a Self-Oscillating Inductive Link

Publication Year: 2018, Page(s):2645 - 2656
| | PDF (3512 KB) | HTML

Wireless sensing systems are becoming popular in a range of applications, particularly in the case of biomedical circuits and food monitoring systems. A typical wireless sensing system, however, may require considerable complexity to perform the necessary analog to digital conversion and subsequent wireless transmission. Alternatively, in the case of inductive link based systems, large, manually o... View full abstract»

• A Pulse Frequency Modulation Interpretation of VCOs Enabling VCO-ADC Architectures With Extended Noise Shaping

Publication Year: 2018, Page(s):444 - 457
Cited by:  Papers (3)
| | PDF (3643 KB) | HTML

In this paper, we propose to study voltage controlled oscillators (VCOs) based on the equivalence with pulse frequency modulators (PFMs). This approach is applied to the analysis of VCO-based analog-to-digital converters (VCO-ADCs) and deviates significantly from the conventional interpretation, where VCO-ADCs have been described as the first-order ΔΣ modulators. A first advantage of our approach ... View full abstract»

• A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS

Publication Year: 2018, Page(s):2109 - 2117
| | PDF (3261 KB) | HTML

This paper presents a PLL supporting diverse low-power clocking needs including wide input (6-200 MHz) and output (0.15-5 GHz) frequency ranges and SSC operation. Fabricated in 14nm FinFET CMOS, a low-power switched-cap loop filter is employed to enable high -3dB PLL bandwidth (&gt;40% of f<sub>REF</sub> = 19.2 MHz), and the proposed reference current generator (IrefGen) provides a... View full abstract»

• A Low-Power NB-IoT Transceiver With Digital-Polar Transmitter in 180-nm CMOS

Publication Year: 2017, Page(s):2569 - 2581
Cited by:  Papers (3)
| | PDF (4584 KB) | HTML

A fully integrated 750~960 MHz wireless transceiver (TRX) is presented for single-tone NB-IoT applications. Effective design methodologies and techniques, from the system level to circuit level, are proposed to address various design challenges while achieving low-power consumption. The TRX consists of a low-IF receiver with 180-kHz signal bandwidth, a digital polar transmitter with 3.75-kHz signa... View full abstract»

• TEAM: ThrEshold Adaptive Memristor Model

Publication Year: 2013, Page(s):211 - 221
Cited by:  Papers (216)  |  Patents (1)
| | PDF (2472 KB) | HTML

Memristive devices are novel devices, which can be used in applications ranging from memory and logic to neuromorphic systems. A memristive device offers several advantages: nonvolatility, good scalability, effectively no leakage current, and compatibility with CMOS technology, both electrically and in terms of manufacturing. Several models for memristive devices have been developed and are discus... View full abstract»

• A 2.4 GHz CMOS Class-F Power Amplifier With Reconfigurable Load-Impedance Matching

Publication Year: 2018, Page(s):1 - 12
| | PDF (3734 KB)

A novel reconfigurable CMOS class-F power amplifier (PA) at 2.4 GHz is proposed in this paper. It is able to match the output load variations mainly due to the effect of hand and head on a mobile phone. The effect of load variation on power-added efficiency (PAE), output power, and distortion is compensated by reconfiguring the output network using an impedance tuner. The tuner controls the output... View full abstract»

• Analysis and Design of the Classical CMOS Schmitt Trigger in Subthreshold Operation

Publication Year: 2017, Page(s):869 - 878
Cited by:  Papers (5)
| | PDF (3050 KB) | HTML

In this paper, the classical CMOS Schmitt trigger (ST) operating in the subthreshold regime is analyzed. The complete DC voltage transfer characteristic of the CMOS ST is determined. The metastable segment of the characteristic is explained in terms of the negative resistance of the NMOS and PMOS subcircuits of the ST. Small-signal analysis is carried out to determine the minimum supply voltage at... View full abstract»

• Theoretical Analysis of Circuit Non-Idealities in a Passive Spectrum Scanner Based on Periodically Time-Varying Circuit Components

Publication Year: 2018, Page(s):2403 - 2410
| | PDF (2417 KB) | HTML

Spectrum scanners based on passive, linear periodically time-varying RC circuits have been shown to be highly linear and consume low power. They rely on the Filtering by Aliasing technique to achieve sharp filtering from a continuous-time input to a discrete-time output. The presence of circuit parasitics can adversely affect scanner performance. Hence, this paper presents a theoretical analysis o... View full abstract»

• A Sub-1ppm/°C Current-Mode CMOS Bandgap Reference With Piecewise Curvature Compensation

Publication Year: 2018, Page(s):904 - 913
| | PDF (3669 KB) | HTML

This paper presents a low temperature coefficient (TC) CMOS BGR for high-performance multi-channel analog-to-digital converter (ADC) working under wide temperature range. Besides the logarithmic compensation, both leakage and piecewise curvature compensation are implemented to extend its operating temperature range and keep its low TC. A β-compensation technique is used to cancel the PTAT and non-... View full abstract»

• A High-Precision Resistor-Less CMOS Compensated Bandgap Reference Based on Successive Voltage-Step Compensation

Publication Year: 2018, Page(s):1 - 11
| | PDF (2548 KB)

A curvature-compensated resistor-less bandgap reference (BGR), which is fabricated in 0.5-&#x03BC;m CMOS process, is proposed in this paper. The BGR utilizes successive voltage-step compensation to produce a temperature-insensitive voltage reference (VR), including one &#x0394;VGS step for first-order compensation and another one for higher order curvature correction. Moreover, a supply no... View full abstract»

• A Two-Stage Fully Differential Inverter-Based Self-Biased CMOS Amplifier With High Efficiency

Publication Year: 2011, Page(s):1591 - 1603
Cited by:  Papers (44)  |  Patents (1)
| | PDF (1735 KB) | HTML

A two-stage fully differential CMOS amplifier comprising inverters as input structures and employing self-biasing techniques is presented. The proposed amplifier benefits from an optimum compensation through time-domain optimization which permits achieving high energy efficiency. Moreover, it achieves the highest efficiency of its class and although it relies on a quasi-class-A topology, it is com... View full abstract»

• Kron Reduction of Graphs With Applications to Electrical Networks

Publication Year: 2013, Page(s):150 - 163
Cited by:  Papers (157)
| | PDF (3757 KB) | HTML

Consider a weighted undirected graph and its corresponding Laplacian matrix, possibly augmented with additional diagonal elements corresponding to self-loops. The Kron reduction of this graph is again a graph whose Laplacian matrix is obtained by the Schur complement of the original Laplacian matrix with respect to a specified subset of nodes. The Kron reduction process is ubiquitous in classic ci... View full abstract»

• A Scalable Optoelectronic Neural Probe Architecture With Self-Diagnostic Capability

Publication Year: 2018, Page(s):2431 - 2442
Cited by:  Papers (1)
| | PDF (3506 KB) | HTML

There is a growing demand for the development of new types of implantable optoelectronics to support both basic neuroscience and optogenetic treatments for neurological disorders. Target specification requirements include multi-site optical stimulation, programmable radiance profile, safe operation, and miniaturization. It is also preferable to have a simple serial interface rather than large numb... View full abstract»

• Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial

Publication Year: 2012, Page(s):3 - 29
Cited by:  Papers (160)
| | PDF (1561 KB) | HTML

In this paper, the state of the art in ultra-low power (ULP) VLSI design is presented within a unitary framework for the first time. A few general principles are first introduced to gain an insight into the design issues and the approaches that are specific to ULP systems, as well as to better understand the challenges that have to be faced in the foreseeable future. Intuitive understanding is acc... View full abstract»

• Analysis and Background Self-Calibration of Comparator Offset in Loop-Unrolled SAR ADCs

Publication Year: 2018, Page(s):458 - 470
| | PDF (2811 KB) | HTML

In conventional charge redistribution successive approximation register (SAR) ADCs that use a single comparator, the comparator offset causes no distortion but a dc shift in the transfer curve. In loop-unrolled (LU) SAR ADCs, on the other hand, mismatched comparator offset voltages introduce input-level-dependent errors to the conversion result, which deteriorates the linearity and limits the reso... View full abstract»

• An Area-Efficient Column-Parallel Digital Decimation Filter With Pre-BWI Topology for CMOS Image Sensor

Publication Year: 2018, Page(s):2524 - 2533
| | PDF (4075 KB) | HTML

This paper presents an area-efficient design of a column-parallel second-order digital decimation filter for a$\Sigma \Delta$analog-to-digital converter-based CMOS image sensor. By using the proposed pre-bitwise-inversion topology having the same mathematical function, the chip area could be curtailed, where the bit-wise-invers... View full abstract»

• Memristor-Based Circuit Design for Multilayer Neural Networks

Publication Year: 2018, Page(s):677 - 686
Cited by:  Papers (1)
| | PDF (2210 KB) | HTML

Memristors are promising components for applications in nonvolatile memory, logic circuits, and neuromorphic computing. In this paper, a novel circuit for memristor-based multilayer neural networks is presented, which can use a single memristor array to realize both the plus and minus weight of the neural synapses. In addition, memristor-based switches are utilized during the learning process to u... View full abstract»

• A Sub-10 mV Power Converter With Fully Integrated Self-Start, MPPT, and ZCS Control for Thermoelectric Energy Harvesting

Publication Year: 2018, Page(s):1744 - 1757
Cited by:  Papers (1)
| | PDF (4026 KB) | HTML

An inductive power converter for thermoelectric generator (TEG) is presented in this paper. A novel redundant inverter ring oscillator is proposed to self-oscillate in a very low supply voltage down to 45 mV. An additional self-start assist circuit with a differential clock booster and an exponential charge pump is implemented in the power converter to achieve lower self-start voltage. Boundary co... View full abstract»

Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK