# IEEE Transactions on Circuits and Systems I: Regular Papers

Includes the top 50 most frequently accessed documents for this publication according to the usage statistics for the month of

• ### Understanding Phase Error and Jitter: Definitions, Implications, Simulations, and Measurement

Publication Year: 2019, Page(s):1 - 19
| | PDF (1696 KB) | HTML

Precision oscillators are ubiquitous in modern electronic systems, and their accuracy often limits the performance of such systems. Hence, a deep understanding of how oscillator performance is quantified, simulated, and measured, and how it affects the system performance is essential for designers. Unfortunately, the necessary information is spread thinly across the published literature and textbo... View full abstract»

• ### Consensus of Multiagent Systems and Synchronization of Complex Networks: A Unified Viewpoint

Publication Year: 2010, Page(s):213 - 224
Cited by:  Papers (1104)
| | PDF (1045 KB) | HTML

This paper addresses the consensus problem of multiagent systems with a time-invariant communication topology consisting of general linear node dynamics. A distributed observer-type consensus protocol based on relative output measurements is proposed. A new framework is introduced to address in a unified way the consensus of multiagent systems and the synchronization of complex networks. Under thi... View full abstract»

• ### Noise Filtering and Linearization of Single-Ended Sampled-Data Circuits

Publication Year: 2019, Page(s):1331 - 1341
| | PDF (3317 KB) | HTML

The performance of analog integrated circuits is often limited by the noise generated in its components. Several circuit techniques exist for mitigating the effects of the low-frequency noise. In this paper, a novel approach is described, which can also reduce even-order distortion, another major limitation of analog circuits. It may also allow the use of single-ended circuits in applications wher... View full abstract»

• ### The flipped voltage follower: a useful cell for low-voltage low-power circuit design

Publication Year: 2005, Page(s):1276 - 1291
Cited by:  Papers (302)  |  Patents (3)
| | PDF (1159 KB) | HTML

In this paper, a basic cell for low-power and/or low-voltage operation is identified. It is evidenced how different versions of this cell, coined as "flipped voltage follower (FVF)" have been used in the past for many applications. A detailed classification of basic topologies derived from the FVF is given. In addition, a comprehensive list of recently proposed low-voltage/low-power CMOS circuits ... View full abstract»

• ### Efficient Hardware Architectures for Deep Convolutional Neural Network

Publication Year: 2018, Page(s):1941 - 1953
Cited by:  Papers (6)
| | PDF (1975 KB) | HTML

Convolutional neural network (CNN) is the state-of-the-art deep learning approach employed in various applications. Real-time CNN implementations in resource limited embedded systems are becoming highly desired recently. To ensure the programmable flexibility and shorten the development period, field programmable gate array is appropriate to implement the CNN models. However, the limited bandwidth... View full abstract»

• ### Full On-Chip CMOS Low-Dropout Voltage Regulator

Publication Year: 2007, Page(s):1879 - 1890
Cited by:  Papers (275)  |  Patents (14)
| | PDF (1617 KB) | HTML

This paper proposes a solution to the present bulky external capacitor low-dropout (LDO) voltage regulators with an external capacitorless LDO architecture. The large external capacitor used in typical LDOs is removed allowing for greater power system integration for system-on-chip (SoC) applications. A compensation scheme is presented that provides both a fast transient response and full range al... View full abstract»

• ### Switched-Capacitor/Switched-Inductor Structures for Getting Transformerless Hybrid DC–DC PWM Converters

Publication Year: 2008, Page(s):687 - 696
Cited by:  Papers (534)  |  Patents (1)
| | PDF (1294 KB) | HTML

A few simple switching structures, formed by either two capacitors and two-three diodes (C-switching), or two inductors and two-three diodes (L-switching) are proposed. These structures can be of two types: ldquostep-downrdquo and ldquostep-up.rdquo These blocks are inserted in classical converters: buck, boost, buck-boost, Cuk, Zeta, Sepic. The ldquostep-downrdquo C- or L-switching structures can... View full abstract»

• ### Approximate Multipliers Based on New Approximate Compressors

Publication Year: 2018, Page(s):4169 - 4182
Cited by:  Papers (1)
| | PDF (4744 KB) | HTML

Approximate computing is an emerging trend in digital design that trades off the requirement of exact computation for improved speed and power performance. This paper proposes novel approximate compressors and an algorithm to exploit them for the design of efficient approximate multipliers. By using the proposed approach, we have synthesized approximate multipliers for several operand lengths usin... View full abstract»

• ### A Novel Digital-Intensive Hybrid Polar-I/Q RF Transmitter Architecture

Publication Year: 2018, Page(s):4390 - 4403
Cited by:  Papers (1)
| | PDF (3773 KB) | HTML

A novel digital-intensive hybrid transmitter (TX) architecture is presented, combining conventional inphase and quadrature (I/Q) with constrained phase modulation. The proposed architecture utilizes an RF-DAC with phase modulated RF clock and adjusted I/Q components. By incorporating phase modulation the quadrature component is kept small while the inphase component approaches the complex signal e... View full abstract»

• ### Error-Feedback Mismatch Error Shaping for High-Resolution Data Converters

Publication Year: 2019, Page(s):1342 - 1354
| | PDF (2862 KB) | HTML

Device mismatch is a key concern for high-resolution data converters. This paper presents a comprehensive study of the error-feedback (EF)-based mismatch error shaping (MES) technique. EF MES overcomes the key challenge of the classic dynamic element matching-based MES whose complexity grows exponentially with the number of bits; however, the prior EF MES comes with the limitations of limited shap... View full abstract»

• ### World’s Fastest FFT Architectures: Breaking the Barrier of 100 GS/s

Publication Year: 2019, Page(s):1507 - 1516
| | PDF (3399 KB) | HTML

This paper presents the fastest fast Fourier transform (FFT) hardware architectures so far. The architectures are based on a fully parallel implementation of the FFT algorithm. In order to obtain the highest throughput while keeping the resource utilization low, we base our design on making use of advanced shift-and-add techniques to implement the rotators and on selecting the most suitable FFT al... View full abstract»

• ### X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories

Publication Year: 2018, Page(s):4219 - 4232
| | PDF (3431 KB) | HTML

Silicon-based static random access memories (SRAM) and digital Boolean logic have been the workhorse of the state-of-the-art computing platforms. Despite tremendous strides in scaling the ubiquitous metal-oxide-semiconductor transistor, the underlying von-Neumann computing architecture has remained unchanged. The limited throughput and energy-efficiency of the state-of-the-art computing systems, t... View full abstract»

• ### The Theory of Special Noise Invariants

Publication Year: 2019, Page(s):1305 - 1318
| | PDF (1193 KB) | HTML

This paper reports a novel systematic theory of the noise invariants of two-port linear noisy networks under lossless reciprocal input and output impedance transformations. The theory clarifies the relationship between the circuit theory of linear noisy networks and the theory of four noise parameters, which are widely applied in the design of low-noise amplifiers (LNAs). In particular, we prove t... View full abstract»

• ### Consensus Tracking of Multi-Agent Systems With Lipschitz-Type Node Dynamics and Switching Topologies

Publication Year: 2014, Page(s):499 - 511
Cited by:  Papers (376)
| | PDF (3732 KB) | HTML

Distributed consensus tracking is addressed in this paper for multi-agent systems with Lipschitz-type node dynamics. The main contribution of this work is solving the consensus tracking problem without the assumption that the topology among followers is strongly connected and fixed. By using tools from M-matrix theory, a class of consensus tracking protocols based only on the relative states among... View full abstract»

• ### Improving Receiver Close-In Blocker Tolerance by Baseband $G_m-C$ Notch Filtering

Publication Year: 2019, Page(s):885 - 896
| | PDF (3427 KB) | HTML

This paper presents a receiver front end with improved blocker handling implemented in a 65-nm CMOS technology. Since close-in blockers are challenging to reject at RF, the receiver features a baseband (BB) notch filter, which effectively sinks close-in blocker current directly from the output of an LNTA and passive mixer structure. The notch-filter frequency can be tuned to match the blocker offs... View full abstract»

• ### Exploiting Machine Learning Against On-Chip Power Analysis Attacks: Tradeoffs and Design Considerations

Publication Year: 2019, Page(s):769 - 781
| | PDF (4010 KB) | HTML

Modern power analysis attacks (PAAs) and existing countermeasures pose unique challenges on the design of simultaneously secure, power efficient, and high-performance ICs. In a typical PAA, power information is collected with a monitoring circuit connected to the compromised device. The non-typical voltage variations induced on a power distribution network (PDN) by such a malicious probing are sen... View full abstract»

• ### Learning in Memristive Neural Network Architectures Using Analog Backpropagation Circuits

Publication Year: 2019, Page(s):719 - 732
Cited by:  Papers (1)
| | PDF (4455 KB) | HTML Media

The on-chip implementation of learning algorithms would speed up the training of neural networks in crossbar arrays. The circuit level design and implementation of a back-propagation algorithm using gradient descent operation for neural network architectures is an open problem. In this paper, we propose analog backpropagation learning circuits for various memristive learning architectures, such as... View full abstract»

• ### Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures

Publication Year: 2008, Page(s):1441 - 1454
Cited by:  Papers (122)  |  Patents (2)
| | PDF (1188 KB) | HTML

The need for highly integrable and programmable analog-to-digital converters (ADCs) is pushing towards the use of dynamic regenerative comparators to maximize speed, power efficiency and reconfigurability. Comparator thermal noise is, however, a limiting factor for the achievable resolution of several ADC architectures with scaled supply voltages. While mismatch in these comparators can be compens... View full abstract»

• ### The Circuit Theory Behind Coupled-Mode Magnetic Resonance-Based Wireless Power Transmission

Publication Year: 2012, Page(s):2065 - 2074
Cited by:  Papers (206)
| | PDF (2999 KB) | HTML

Inductive coupling is a viable scheme to wirelessly energize devices with a wide range of power requirements from nanowatts in radio frequency identification tags to milliwatts in implantable microelectronic devices, watts in mobile electronics, and kilowatts in electric cars. Several analytical methods for estimating the power transfer efficiency (PTE) across inductive power transmission links ha... View full abstract»

• ### A System of Two Coupled Oscillators With a Continuously Controllable Phase Shift

Publication Year: 2019, Page(s):1531 - 1543
| | PDF (3059 KB) | HTML

We present a novel generalization of quadrature oscillators (QVCO) which we call “arbitrary phase oscillator” or APO for short. In contrast to a QVCO which generates only quadrature phases, the APO is capable of continuously generating any desired phase at its output. The proposed structure employs a novel coupling mechanism to generate arbitrary phase shifts between two coupled oscillators withou... View full abstract»

• ### Low-Pass Filtering SC-DAC for Reduced Jitter and Slewing Requirements on CTSDMs

Publication Year: 2019, Page(s):1369 - 1381
| | PDF (2633 KB) | HTML

In this paper, a technique is introduced that improves the performance of one-bit continuous-time sigma delta modulators (CTSDMs) using a low-pass filtering switched capacitor digital to analog converter (LPSC-DAC). This DAC effectively combines an infinite impulse response filter with a switched capacitor resistor DAC (SCR-DAC). The resulting DAC is inherently immune toward inter-symbol interfere... View full abstract»

• ### Matching Properties of Femtofarad and Sub-Femtofarad MOM Capacitors

Publication Year: 2016, Page(s):763 - 772
Cited by:  Papers (7)
| | PDF (1936 KB) | HTML

Small metal-oxide-metal (MOM) capacitors are essential to energy-efficient mixed-signal integrated circuit design. However, only few reports discuss their matching properties based on large sets of measured data. In this paper, we report matching properties of femtofarad and sub-femtofarad MOM vertical-field parallel-plate capacitors and lateral-field fringing capacitors. We study the effect of bo... View full abstract»

• ### Analysis of Reference Error in High-Speed SAR ADCs With Capacitive DAC

Publication Year: 2019, Page(s):82 - 93
| | PDF (2376 KB) | HTML

The high-speed successive-approximation-register (SAR) analog-to-digital converters (ADCs) rely on the switched capacitive digital-to-analog converter (CDAC) to perform the fast transition, which causes voltage ripples at the output of the reference circuits. Such ripples lead to the reference error that eventually prolongs the time for DAC settling. To minimize such error with a short available t... View full abstract»

• ### Implications of Passive Mixer Transparency for Impedance Matching and Noise Figure in Passive Mixer-First Receivers

Publication Year: 2010, Page(s):3092 - 3103
Cited by:  Papers (112)  |  Patents (11)
| | PDF (559 KB) | HTML

In this paper, a class of passive mixer-first, LNA-less receivers is analyzed in depth. Quadrature passive mixers are shown to present the impedance of their baseband port to the RF port and vice versa. This transparency property, in combination with resistive feedback differential amplifiers, and “complex” feedback between the I and Q paths, can be used to control the impedance at the RF port. Th... View full abstract»

• ### Network Science Meets Circuit Theory: Resistance Distance, Kirchhoff Index, and Foster’s Theorems With Generalizations and Unification

Publication Year: 2019, Page(s):1090 - 1103
| | PDF (1162 KB) | HTML

The emerging area of network science and engineering is concerned with the study of structural characteristics of networks, their impact on the dynamical behavior of systems as revealed through their topological properties, random evolution of networks, information spreading along a network, and so on. This area spans a wide range of applications in different disciplines. A topic of great interest... View full abstract»

• ### Design Methodology for Phase-Locked Loops Using Binary (Bang-Bang) Phase Detectors

Publication Year: 2017, Page(s):1637 - 1650
Cited by:  Papers (4)
| | PDF (3613 KB) | HTML

We present a linearized analysis of bang-bang phase-locked loops (PLLs) in the frequency domain that is complete and self-consistent. It enables the manual design of frequency synthesis PLLs for loop bandwidth, output phase noise and minimum jitter. Tradeoffs between various parameters of the loop become clear. The analysis is validated against measurements on four very different loops, and helps ... View full abstract»

• ### Event-Triggered Control for Consensus Problem in Multi-Agent Systems With Quantized Relative State Measurements and External Disturbance

Publication Year: 2018, Page(s):2232 - 2242
Cited by:  Papers (8)
| | PDF (3683 KB) | HTML

For decreasing communication load and overcoming network constrains, such as the limited bandwidth and data loss in multi-agent networks, this paper integrates the two control strategies to investigate the bounded consensus problem of multi-agent systems (MASs) with external disturbance on the basis of an undirected graph, namely, the quantized control and the event-triggered control. In the exist... View full abstract»

• ### CORDIC-Based Architecture for Computing Nth Root and Its Implementation

Publication Year: 2018, Page(s):4183 - 4195
Cited by:  Papers (2)
| | PDF (2623 KB) | HTML

This paper presents a COordinate Rotation Digital Computer (CORDIC)-based architecture for the computation of Nth root and proves its feasibility by hardware implementation. The proposed architecture performs the task of Nth root simply by shift-add operations and enables easy tradeoff between the speed (or precision) and the area. Technically, we divide the Nth root computation into three differe... View full abstract»

• ### Sub-1-dB and Wideband SiGe BiCMOS Low-Noise Amplifiers for $X$ -Band Applications

Publication Year: 2019, Page(s):1419 - 1430
| | PDF (4620 KB) | HTML

In this paper, a design methodology for SiGe HBT-based low-noise amplifiers (LNAs) is proposed that can be utilized for both sub-1-dB noise figure (NF) and wide bandwidth as an alternative to the conventional simultaneous input noise and power matching technique. This paper focuses on the removal of the series base inductor and the inclusion of an output matching network as a design parameter that... View full abstract»

• ### A Low-Power Fast Start-Up Crystal Oscillator With an Autonomous Dynamically Adjusted Load

Publication Year: 2019, Page(s):1382 - 1392
| | PDF (6290 KB) | HTML

An energy-efficient fast start-up method for crystal oscillators is presented, which enables aggressive duty-cycled operation of IoT radios to minimize overall power consumption. A digitally controlled crystal oscillator using the proposed startup technique in 90-nm CMOS is presented. Thanks to the dynamically adjusted load, the negative resistance is boosted, achieving a 13× start-up time reducti... View full abstract»

• ### A Phasor-Based Analysis of Sinusoidal Injection Locking in LC and Ring Oscillators

Publication Year: 2019, Page(s):355 - 368
| | PDF (2129 KB) | HTML

A new perspective into the locking behavior of LC and ring oscillators is presented. By decomposing a sinusoidal injection current into in-phase and quadrature-phase components, exact expressions for the amplitude and phase of an injection-locked LC oscillator which hold for any injection strength and frequency are derived and confirmed by simulation. The analysis, which can be naturally extended ... View full abstract»

• ### An Integrated Message-Passing Detector and Decoder for Polar-Coded Massive MU-MIMO Systems

Publication Year: 2019, Page(s):1205 - 1218
| | PDF (4651 KB) | HTML

For a coded massive multi-user multiple-input multiple-output (MIMO) system, a soft-output MIMO detector is essential since it can provide a significant coding gain, e.g., 3 dB, compared with a hard-output detector. However, the computational complexity of the soft-output MIMO detector is usually much greater than that of the hard-output detector. This paper presents the first soft-output message-... View full abstract»

• ### TEAM: ThrEshold Adaptive Memristor Model

Publication Year: 2013, Page(s):211 - 221
Cited by:  Papers (246)  |  Patents (1)
| | PDF (2472 KB) | HTML

Memristive devices are novel devices, which can be used in applications ranging from memory and logic to neuromorphic systems. A memristive device offers several advantages: nonvolatility, good scalability, effectively no leakage current, and compatibility with CMOS technology, both electrically and in terms of manufacturing. Several models for memristive devices have been developed and are discus... View full abstract»

• ### A frequency compensation scheme for LDO voltage regulators

Publication Year: 2004, Page(s):1041 - 1050
Cited by:  Papers (167)  |  Patents (7)
| | PDF (562 KB) | HTML

A stable low dropout (LDO) voltage regulator topology for low equivalent series resistance (ESR) capacitive loads is presented. The proposed scheme generates a zero internally instead of relying on the zero generated by the load capacitor and its ESR combination for stability. It is demonstrated that this scheme realizes robust frequency compensation, facilitates the use of multilayer ceramic capa... View full abstract»

• ### A Reconfigurable Streaming Deep Convolutional Neural Network Accelerator for Internet of Things

Publication Year: 2018, Page(s):198 - 208
Cited by:  Papers (9)
| | PDF (2922 KB) | HTML

Convolutional neural network (CNN) offers significant accuracy in image detection. To implement image detection using CNN in the Internet of Things (IoT) devices, a streaming hardware accelerator is proposed. The proposed accelerator optimizes the energy efficiency by avoiding unnecessary data movement. With unique filter decomposition technique, the accelerator can support arbitrary convolution w... View full abstract»

• ### A 53-67 GHz Low-Noise Mixer-First Receiver Front-End in 65-nm CMOS

Publication Year: 2019, Page(s):1 - 13
| | PDF (4173 KB)

In this paper, we present a mixer-first receiver front-end suitable for millimeter wave (mm-wave) applications. The proposed architecture includes a modified single-balanced mixer core with an on-chip balun in order to provide a differential output from an injected single-ended local oscillator signal. The mm-wave active balun incorporates a cascode cross-coupled structure to achieve a high voltag... View full abstract»

• ### A 25–35 GHz Neutralized Continuous Class-F CMOS Power Amplifier for 5G Mobile Communications Achieving 26% Modulation PAE at 1.5 Gb/s and 46.4% Peak PAE

Publication Year: 2019, Page(s):834 - 847
| | PDF (3598 KB) | HTML

This paper presents a high-efficiency neutralized continuous class-F (CCF) CMOS power amplifier (PA) design technique for millimeter-wave (mmW) 5G mobile communications. A parasitic-aware tuned-load with a high-order harmonicresonance network is proposed to shape the current and voltage waveforms for the CCF PA. At mmW frequencies, the gate- drain capacitance (Cgd) creates adverse capacitive loadi... View full abstract»

• ### A Fully-Integrated Low-Dropout Regulator With Full-Spectrum Power Supply Rejection

Publication Year: 2015, Page(s):707 - 716
Cited by:  Papers (49)
| | PDF (2674 KB) | HTML

A fully-integrated low-dropout regulator (LDO) with fast transient response and full spectrum power supply rejection (PSR) is proposed to provide a clean supply for noise-sensitive building blocks in wideband communication systems. With the proposed point-of-load LDO, chip-level high-frequency glitches are well attenuated, consequently the system performance is improved. A tri-loop LDO architectur... View full abstract»

• ### Kron Reduction of Graphs With Applications to Electrical Networks

Publication Year: 2013, Page(s):150 - 163
Cited by:  Papers (202)
| | PDF (3757 KB) | HTML

Consider a weighted undirected graph and its corresponding Laplacian matrix, possibly augmented with additional diagonal elements corresponding to self-loops. The Kron reduction of this graph is again a graph whose Laplacian matrix is obtained by the Schur complement of the original Laplacian matrix with respect to a specified subset of nodes. The Kron reduction process is ubiquitous in classic ci... View full abstract»

• ### Highly Digital Second-Order ΔΣ VCO ADC

Publication Year: 2019, Page(s):1 - 11
| | PDF (5024 KB)

A continuous-time second-order ΔΣ analog-to-digital converter (ADC) is presented in this paper. The proposed ADC is based on a novel architecture and uses current starved ring oscillators as integrators to achieve the second-order noise shaping. The proposed architecture does not require excess loop delay compensation or nonlinearity calibration. Static element mismatch in the multi-bit current di... View full abstract»

• ### A Novel 1.2–V 4.5-ppm/°C Curvature-Compensated CMOS Bandgap Reference

Publication Year: 2014, Page(s):1026 - 1035
Cited by:  Papers (54)
| | PDF (2075 KB) | HTML

This paper proposes a novel CMOS bandgap reference (BGR) with high-order curvature-compensation by using MOS transistors operating in weak inversion region. The mechanism of the proposed curvature-compensation technique is analyzed thoroughly and the corresponding BGR circuit was implemented in standard CMOS 0.18 μm technology. The experimental results show that the proposed BGR achieves 4.5 ppm/°... View full abstract»

• ### A 1.2-V 2.41-GHz Three-Stage CMOS OTA With Efficient Frequency Compensation Technique

Publication Year: 2019, Page(s):20 - 30
| | PDF (2474 KB) | HTML

A performance-boosting frequency-compensation technique, called feed-forward Gm-stage and regular Miller plus indirect compensation (FGRMIC), is presented in this paper. The proposed structure consists of three parts that ensure the stability and significantly improve the performance, such as gain-bandwidth product (GBW), slew rate, and sensitivity. The first part is a feed-forward transconductanc... View full abstract»

• ### A Two-Stage Fully Differential Inverter-Based Self-Biased CMOS Amplifier With High Efficiency

Publication Year: 2011, Page(s):1591 - 1603
Cited by:  Papers (48)  |  Patents (1)
| | PDF (1735 KB) | HTML

A two-stage fully differential CMOS amplifier comprising inverters as input structures and employing self-biasing techniques is presented. The proposed amplifier benefits from an optimum compensation through time-domain optimization which permits achieving high energy efficiency. Moreover, it achieves the highest efficiency of its class and although it relies on a quasi-class-A topology, it is com... View full abstract»

• ### A Resistorless High-Precision Compensated CMOS Bandgap Voltage Reference

Publication Year: 2019, Page(s):428 - 437
| | PDF (5789 KB) | HTML

A resistorless high-precision compensated CMOS bandgap voltage reference (BGR), which is compatible with a standard CMOS process, is presented in this paper. A higherorder curvature correction method called base-emitter voltage linearization is adapted to directly compensate the thermal nonlinearity of base-emitter voltage. With proper mathematical operations of high-order temperature currents, mo... View full abstract»

• ### A Second-Order Bandpass $\Delta\Sigma$ Time-to-Digital Converter With Negative Time-Mode Feedback

Publication Year: 2019, Page(s):1355 - 1368
| | PDF (4929 KB) | HTML

This paper presents an all-digital bandpass ΔΣ time-to-digital converter (BP)ΔΣTDC) for IF data conversion. The proposed TDC is based on a second-order resonator implemented by a cascade of two time-mode lossless discrete integrators (LDI), and a digital-to-time converter (DTC) in a feedback loop. The DTC is based on a new topology of doubleedge voltage-controlled delay unit. The proposed TDC achi... View full abstract»

• ### 50 Years of CORDIC: Algorithms, Architectures, and Applications

Publication Year: 2009, Page(s):1893 - 1907
Cited by:  Papers (224)  |  Patents (8)
| | PDF (755 KB) | HTML

Year 2009 marks the completion of 50 years of the invention of CORDIC (coordinate rotation digital computer) by Jack E. Volder. The beauty of CORDIC lies in the fact that by simple shift-add operations, it can perform several computing tasks such as the calculation of trigonometric, hyperbolic and logarithmic functions, real and complex multiplications, division, square-root, solution of linear sy... View full abstract»

• ### Fully-Integrated Charge Pump Design Optimization for Above-Breakdown Biasing of Single-Photon Avalanche Diodes in 0.13- $\mu$ m CMOS

Publication Year: 2019, Page(s):1258 - 1269
| | PDF (2760 KB) | HTML

A design methodology for an area-optimized integrated charge pump is described suitable for on-chip high-voltage reverse bias of single-photon avalanche diodes (SPADs). The high-voltage generation block is implemented in a general-purpose 0.13-μm CMOS process and is capable of generating a maximum regulated output voltage of 17.7 V from an input of 1.8 V. An ON-OFF regulation scheme with dynamic c... View full abstract»

• ### Linearization Techniques for CMOS Low Noise Amplifiers: A Tutorial

Publication Year: 2011, Page(s):22 - 36
Cited by:  Papers (146)  |  Patents (4)
| | PDF (1569 KB) | HTML

This tutorial catalogues and analyzes previously reported CMOS low noise amplifier (LNA) linearization techniques. These techniques comprise eight categories: a) feedback; b) harmonic termination; c) optimum biasing; d) feedforward; e) derivative superposition (DS); f) IM2 injection; g) noise/distortion cancellation; and h) post-distortion. This paper also addresses broadband-LNA-linearization iss... View full abstract»

• ### Signal Encoding and Processing in Continuous Time Using a Cascade of Digital Delays

Publication Year: 2019, Page(s):1017 - 1030
| | PDF (2202 KB) | HTML

We consider a digital encoding/processing system in which both the analog-to-digital converter and the digital signal processor are implemented by repeating a single fundamental design unit: the digital delay. Timing becomes an integral part of the resulting signal representation and processing, thereby promising to improve with technology scaling. System properties are studied and design consider... View full abstract»

• ### Development of Single-Transistor-Control LDO Based on Flipped Voltage Follower for SoC

Publication Year: 2008, Page(s):1392 - 1401
Cited by:  Papers (94)  |  Patents (3)
| | PDF (2180 KB) | HTML

The design issues of a single-transistor-control (STC) low-drop-out (LDO) based on flipped voltage follower is discussed in this paper, in particular the feedback stability at different conditions of output capacitors, equivalent series resistances (ESRs) and load current. Based on the analysis, an STC LDO was implemented in a standard 0.35-mum MOS technology. It is proven experimentally that the ... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK