# IEEE Transactions on Circuits and Systems I: Regular Papers

Includes the top 50 most frequently accessed documents for this publication according to the usage statistics for the month of

• ### Time Domain Processing Techniques Using Ring Oscillator-Based Filter Structures

Publication Year: 2017, Page(s):3003 - 3012
| | PDF (2197 KB) | HTML

The ability to process time-encoded signals with high fidelity is becoming increasingly important for the time domain (TD) circuit techniques that are used at the advanced nanometer technology nodes. This paper proposes a compact oscillator-based subsystem that performs precise filtering of asynchronous pulse-width modulation encoded signals and makes extensive use of digital logic, enabling low-v... View full abstract»

• ### Full On-Chip CMOS Low-Dropout Voltage Regulator

Publication Year: 2007, Page(s):1879 - 1890
Cited by:  Papers (242)  |  Patents (14)
| | PDF (1617 KB) | HTML

This paper proposes a solution to the present bulky external capacitor low-dropout (LDO) voltage regulators with an external capacitorless LDO architecture. The large external capacitor used in typical LDOs is removed allowing for greater power system integration for system-on-chip (SoC) applications. A compensation scheme is presented that provides both a fast transient response and full range al... View full abstract»

• ### Consensus of Multiagent Systems and Synchronization of Complex Networks: A Unified Viewpoint

Publication Year: 2010, Page(s):213 - 224
Cited by:  Papers (891)
| | PDF (1045 KB) | HTML

This paper addresses the consensus problem of multiagent systems with a time-invariant communication topology consisting of general linear node dynamics. A distributed observer-type consensus protocol based on relative output measurements is proposed. A new framework is introduced to address in a unified way the consensus of multiagent systems and the synchronization of complex networks. Under thi... View full abstract»

• ### The flipped voltage follower: a useful cell for low-voltage low-power circuit design

Publication Year: 2005, Page(s):1276 - 1291
Cited by:  Papers (259)  |  Patents (3)
| | PDF (1168 KB) | HTML

In this paper, a basic cell for low-power and/or low-voltage operation is identified. It is evidenced how different versions of this cell, coined as "flipped voltage follower (FVF)" have been used in the past for many applications. A detailed classification of basic topologies derived from the FVF is given. In addition, a comprehensive list of recently proposed low-voltage/low-power CMOS circuits ... View full abstract»

• ### A Reconfigurable Streaming Deep Convolutional Neural Network Accelerator for Internet of Things

Publication Year: 2018, Page(s):198 - 208
| | PDF (2922 KB) | HTML

Convolutional neural network (CNN) offers significant accuracy in image detection. To implement image detection using CNN in the Internet of Things (IoT) devices, a streaming hardware accelerator is proposed. The proposed accelerator optimizes the energy efficiency by avoiding unnecessary data movement. With unique filter decomposition technique, the accelerator can support arbitrary convolution w... View full abstract»

• ### An Architecture to Accelerate Convolution in Deep Neural Networks

Publication Year: 2018, Page(s):1349 - 1362
| | PDF (3035 KB) | HTML

In the past few years, the demand for real-time hardware implementations of deep neural networks (DNNs), especially convolutional neural networks (CNNs), has dramatically increased, thanks to their excellent performance on a wide range of recognition and classification tasks. When considering real-time action recognition and video/image classification systems, latency is of paramount importance. T... View full abstract»

• ### Comprehensive Analysis of Distortion in the Passive FET Sample-and-Hold Circuit

Publication Year: 2018, Page(s):1157 - 1173
| | PDF (7128 KB) | HTML

Analysis simplified with circuit insights reveals the major sources of distortion in a passive FET-switch-based sampling circuit: 1) $R_{mathrm{scriptscriptstyle ON}}$ -modulation; 2) turn-OFF-time instant; and 3) signal-dependent charge-injection. Explicit expressions for second- and third-order distortions advance intuitive understanding of the processes of distortion. Circuit simulations and me... View full abstract»

• ### Efficient Hardware Architectures for Deep Convolutional Neural Network

Publication Year: 2018, Page(s):1941 - 1953
| | PDF (1975 KB) | HTML

Convolutional neural network (CNN) is the state-of-the-art deep learning approach employed in various applications. Real-time CNN implementations in resource limited embedded systems are becoming highly desired recently. To ensure the programmable flexibility and shorten the development period, field programmable gate array is appropriate to implement the CNN models. However, the limited bandwidth... View full abstract»

• ### Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures

Publication Year: 2008, Page(s):1441 - 1454
Cited by:  Papers (103)  |  Patents (2)
| | PDF (1188 KB) | HTML

The need for highly integrable and programmable analog-to-digital converters (ADCs) is pushing towards the use of dynamic regenerative comparators to maximize speed, power efficiency and reconfigurability. Comparator thermal noise is, however, a limiting factor for the achievable resolution of several ADC architectures with scaled supply voltages. While mismatch in these comparators can be compens... View full abstract»

• ### Switched-Capacitor/Switched-Inductor Structures for Getting Transformerless Hybrid DC–DC PWM Converters

Publication Year: 2008, Page(s):687 - 696
Cited by:  Papers (417)  |  Patents (1)
| | PDF (1294 KB) | HTML

A few simple switching structures, formed by either two capacitors and two-three diodes (C-switching), or two inductors and two-three diodes (L-switching) are proposed. These structures can be of two types: ldquostep-downrdquo and ldquostep-up.rdquo These blocks are inserted in classical converters: buck, boost, buck-boost, Cuk, Zeta, Sepic. The ldquostep-downrdquo C- or L-switching structures can... View full abstract»

• ### A Pulse Frequency Modulation Interpretation of VCOs Enabling VCO-ADC Architectures With Extended Noise Shaping

Publication Year: 2018, Page(s):444 - 457
| | PDF (3643 KB) | HTML

In this paper, we propose to study voltage controlled oscillators (VCOs) based on the equivalence with pulse frequency modulators (PFMs). This approach is applied to the analysis of VCO-based analog-to-digital converters (VCO-ADCs) and deviates significantly from the conventional interpretation, where VCO-ADCs have been described as the first-order ΔΣ modulators. A first advantage of... View full abstract»

• ### A Low-Power NB-IoT Transceiver With Digital-Polar Transmitter in 180-nm CMOS

Publication Year: 2017, Page(s):2569 - 2581
| | PDF (4584 KB) | HTML

A fully integrated 750~960 MHz wireless transceiver (TRX) is presented for single-tone NB-IoT applications. Effective design methodologies and techniques, from the system level to circuit level, are proposed to address various design challenges while achieving low-power consumption. The TRX consists of a low-IF receiver with 180-kHz signal bandwidth, a digital polar transmitter with 3.75-kHz signa... View full abstract»

• ### Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey

Publication Year: 2011, Page(s):1 - 21
Cited by:  Papers (95)  |  Patents (7)
| | PDF (1691 KB) | HTML

This paper presents a tutorial overview of ΣΔ modulators, their operating principles and architectures, circuit errors and models, design methods, and practical issues. A review of the state of the art on nanometer CMOS implementations is described, giving a survey of cutting-edge ΣΔ architectures, with emphasis on their application to the next generation of wireless te... View full abstract»

• ### A Sub-1ppm/°C Current-Mode CMOS Bandgap Reference With Piecewise Curvature Compensation

Publication Year: 2018, Page(s):904 - 913
| | PDF (3669 KB) | HTML

This paper presents a low temperature coefficient (TC) CMOS BGR for high-performance multi-channel analog-to-digital converter (ADC) working under wide temperature range. Besides the logarithmic compensation, both leakage and piecewise curvature compensation are implemented to extend its operating temperature range and keep its low TC. A β-compensation technique is used to cancel the PTAT a... View full abstract»

• ### Wideband Inductorless Low-Power LNAs with Gm Enhancement and Noise-Cancellation

Publication Year: 2018, Page(s):26 - 38
| | PDF (3641 KB) | HTML

Two inductorless low-power differential low-noise amplifiers (LNAs) are designed for multiband wireless communication applications. Both LNAs are based on the combination of common-gate (CG) and shunt feedback topologies. In the first LNA, the cross-coupled push-pull structure with separated bias for nMOS and pMOS CG transistors is utilized to realize gm enhancement, partial noise cancellation, an... View full abstract»

• ### Analysis and Design of the Classical CMOS Schmitt Trigger in Subthreshold Operation

Publication Year: 2017, Page(s):869 - 878
Cited by:  Papers (1)
| | PDF (3050 KB) | HTML

In this paper, the classical CMOS Schmitt trigger (ST) operating in the subthreshold regime is analyzed. The complete DC voltage transfer characteristic of the CMOS ST is determined. The metastable segment of the characteristic is explained in terms of the negative resistance of the NMOS and PMOS subcircuits of the ST. Small-signal analysis is carried out to determine the minimum supply voltage at... View full abstract»

• ### A 250-MHz Pipelined ADC-Based $f_{S}/4$ Noise-Shaping Bandpass ADC

Publication Year: 2018, Page(s):1785 - 1794
| | PDF (2638 KB) | HTML

A new fS/4 bandpass ΔΣ-analog-to-digital converter (ADC) architecture is realized by feeding back the delayed quantization noise inherently produced by a pipelined ADC. Designed in a 55-nm global foundry (GF) LP-CMOS process, the prototype ADC sampling at 250 MHz achieves an Signal-to-Noise+Distortion Ratio of 72, 75.8, 80.1, and 85.3 dB in a 15.64-, 7.82-, 3.91-, and 1.95... View full abstract»

• ### Efficient Behavioral Simulation of Charge-Pump Phase-Locked Loops

Publication Year: 2018, Page(s):1968 - 1980
| | PDF (2739 KB) | HTML

The simulation of the full netlist of a phase locked loop (PLL) is resource demanding due to the prohibitive time needed to derive output noise, spurs, and transient performance from detailed transistor-level simulations. To overcome this limitation, behavioral models are needed but they must be accurate and time-efficient. This paper introduces a new behavioral macro-model of the charge-pump PLL,... View full abstract»

• ### The Circuit Theory Behind Coupled-Mode Magnetic Resonance-Based Wireless Power Transmission

Publication Year: 2012, Page(s):2065 - 2074
Cited by:  Papers (164)
| | PDF (2999 KB) | HTML

Inductive coupling is a viable scheme to wirelessly energize devices with a wide range of power requirements from nanowatts in radio frequency identification tags to milliwatts in implantable microelectronic devices, watts in mobile electronics, and kilowatts in electric cars. Several analytical methods for estimating the power transfer efficiency (PTE) across inductive power transmission links ha... View full abstract»

• ### How to Make Analog-to-Information Converters Work in Dynamic Spectrum Environments With Changing Sparsity Conditions

Publication Year: 2018, Page(s):1775 - 1784
| | PDF (4278 KB) | HTML

Compressed sensing (CS) analog to information converters (AICs) offer key benefits for signal reception or detection when the input signal is sparse. So far AICs have been demonstrated in environments with controlled input signal conditions and with fixed sparsity levels. This paper investigates how to make AICs effectively operate in dynamic environments with changing signal conditions and thus c... View full abstract»

• ### A Digital Phase-Locked Loop With Background Supply Voltage Sensitivity Minimization

Publication Year: 2018, Page(s):1830 - 1839
| | PDF (2512 KB) | HTML

A digital phase-locked loop (DPLL) with the background supply voltage sensitivity minimization is presented. By using a frequency subtractor, a digital supply voltage sensitivity controller can suppress the supply voltage sensitivity of a DPLL. This DPLL is fabricated in 40-nm CMOS technology. Its active area is 0.006 mm2 where the supply voltage sensitivity controller occupies about 20... View full abstract»

• ### A Wideband Inductorless LNA With Local Feedback and Noise Cancelling for Low-Power Low-Voltage Applications

Publication Year: 2010, Page(s):1993 - 2005
Cited by:  Papers (61)  |  Patents (2)
| | PDF (1159 KB) | HTML

A wideband noise-cancelling low-noise amplifier (LNA) without the use of inductors is designed for low-voltage and low-power applications. Based on the common-gate-common-source (CG-CS) topology, a new approach employing local negative feedback is introduced between the parallel CG and CS stages. The moderate gain at the source of the cascode transistor in the CS stage is utilized to boost the tra... View full abstract»

• ### Analysis of Common-Mode Interference and Jitter of Clock Receiver Circuits With Improved Topology

Publication Year: 2018, Page(s):1819 - 1829
| | PDF (2096 KB) | HTML

This paper presents an analysis based on the impulse sensitivity function to precisely characterize and estimate the jitter caused by the common-mode interference (CMI). Unlike the conventional common-mode rejection ratio concept, the proposed method considers the CMI jitter in a transient rather than in an ac perspective. Inspired by the analytical results, we propose a clock receiver circuit (CR... View full abstract»

• ### Analysis and Background Self-Calibration of Comparator Offset in Loop-Unrolled SAR ADCs

Publication Year: 2018, Page(s):458 - 470
| | PDF (2811 KB) | HTML

In conventional charge redistribution successive approximation register (SAR) ADCs that use a single comparator, the comparator offset causes no distortion but a dc shift in the transfer curve. In loop-unrolled (LU) SAR ADCs, on the other hand, mismatched comparator offset voltages introduce input-level-dependent errors to the conversion result, which deteriorates the linearity and limits the reso... View full abstract»

• ### A 33fJ/Step SAR Capacitance-to-Digital Converter Using a Chain of Inverter-Based Amplifiers

Publication Year: 2017, Page(s):310 - 321
Cited by:  Papers (2)
| | PDF (3650 KB) | HTML

A 12 - bit energy-efficient capacitive sensor interface circuit that fully relies on capacitance-domain successive approximation (SAR) technique is presented. Analysis shows that for SAR capacitance-to-digital converter (CDC) comparator offset voltage will result in parasitic-dependent conversion errors, which necessitates using an offset cancellation technique. Based on the presented analysis, a ... View full abstract»

• ### High-Efficiency Charge Pumps for Low-Power On-Chip Applications

Publication Year: 2018, Page(s):1143 - 1153
| | PDF (2501 KB) | HTML

This paper proposes charge pumps with improved power efficiency suitable for low-power on-chip applications. Undesired charge transfer, which has a direction opposite to that of the intended current flow, presents a significant source of power loss in charge pumps. The proposed charge pump circuit utilizes charge transfer switches with a complementary branch scheme to significantly reduce undesire... View full abstract»

• ### Design of High-Order Type-II Delay-Locked Loops With a Fast-Settling-Zero-Overshoot Step Response and Large Jitter-Rejection Capabilities

Publication Year: 2018, Page(s):1805 - 1818
| | PDF (4589 KB) | HTML

In this paper, a design method for high-order delay-lock loops (DLLs) is presented and verified through simulations and physical experiments. The general approach is based on selecting the closed-loop transfer function of the DLL, together with identifying the coefficients of the phase-detector and voltage-controlled delay line, and subsequently, solving for parameters of the loop filter of the DL... View full abstract»

• ### A Fully-Integrated Low-Dropout Regulator With Full-Spectrum Power Supply Rejection

Publication Year: 2015, Page(s):707 - 716
Cited by:  Papers (25)
| | PDF (2674 KB) | HTML

A fully-integrated low-dropout regulator (LDO) with fast transient response and full spectrum power supply rejection (PSR) is proposed to provide a clean supply for noise-sensitive building blocks in wideband communication systems. With the proposed point-of-load LDO, chip-level high-frequency glitches are well attenuated, consequently the system performance is improved. A tri-loop LDO architectur... View full abstract»

• ### A 12-b 40-MS/s Calibration-Free SAR ADC

Publication Year: 2018, Page(s):881 - 890
| | PDF (3686 KB) | HTML

This paper presents a new circuit technique named residue oversampling, which is suitable for high-resolution analog-to-digital converters (ADCs). By adopting this technique and simplifying the dynamic element matching, the impacts of capacitor mismatch and noise upon the successive-approximation register ADCs are reduced significantly without calibrations. The proof-of-concept prototype was fabri... View full abstract»

• ### A Millimeter-Wave Fully Integrated Passive Reflection-Type Phase Shifter With Transformer-Based Multi-Resonance Loads for 360° Phase Shifting

Publication Year: 2018, Page(s):1406 - 1419
| | PDF (8192 KB) | HTML

This paper presents a millimeter-wave fully differential transformer-based passive reflection-type phase shifter (RTPS) capable of performing full span 360° continuous phase shift from 58 to 64 GHz. It consists of two transformerbased 90° couplers and two transformer-based multi-resonance reflective loads to provide 360° phase shift with low loss and ultra-compact chip size. O... View full abstract»

• ### A Fully Isolated Amplifier Based on Charge-Balanced SAR Converters

Publication Year: 2018, Page(s):1795 - 1804
| | PDF (2215 KB) | HTML

A galvanic isolated amplifier based on SAR converters architecture is presented which realizes chip level isolation in both the power and signal domains. The compact IC package contains an integrated isolated power converter which includes on-chip transformer, oscillator and rectifier, digital isolators based on on-chip transformers, a front-end programmable gain amplifier, a SAR ADC, a complement... View full abstract»

• ### Design Procedure for Two-Stage CMOS Opamp With Flexible Noise-Power Balancing Scheme

Publication Year: 2005, Page(s):1508 - 1514
Cited by:  Papers (43)
| | PDF (368 KB) | HTML

This paper presents a basic two-stage CMOS opamp design procedure that provides the circuit designer with a means to strike a balance between two important characteristics in electronic circuit design, namely noise performance and power consumption. It is shown in this paper that, unlike the previously reported design procedures, the proposed design step allows opamp designers to trade between noi... View full abstract»

• ### A Sub-1 ppm/°C Precision Bandgap Reference With Adjusted-Temperature-Curvature Compensation

Publication Year: 2017, Page(s):1308 - 1317
Cited by:  Papers (4)
| | PDF (3114 KB) | HTML

This paper presents a precision bandgap reference with an innovative adjusted-temperature-curvature compensation circuit that obtains a good temperature coefficient (TC) over a wide temperature range. The proposed compensation circuit for enhancing the voltage accuracy of the bandgap reference combines an addition circuit, subtraction circuit, and current mirror to achieve an adjusted piecewise li... View full abstract»

• ### Homeostatic Fault Tolerance in Spiking Neural Networks: A Dynamic Hardware Perspective

Publication Year: 2018, Page(s):687 - 699
| | PDF (2824 KB) | HTML

Fault tolerance is a remarkable feature of biological systems and their self-repair capability influence modern electronic systems. In this paper, we propose a novel plastic neural network model, which establishes homeostasis in a spiking neural network. Combined with this plasticity and the inspiration from inhibitory interneurons, we develop a fault-resilient robotic controller implemented on an... View full abstract»

• ### An On-Chip CMOS Temperature Sensor Using Self-Discharging P-N Diode in a $Delta$ - $Sigma$ Loop

Publication Year: 2018, Page(s):1887 - 1896
| | PDF (3043 KB) | HTML

A CMOS temperature sensor to monitor on-chip distributed thermal profile of high-performance system-on-chips (SoCs) is presented. The architecture of this sensor utilizes a self-discharging p-n diode to implement a first-order delta-sigma (Δ-Σ) loop. To determine the on-chip temperature, the temperature-dependent reverse-bias leakage current of the diode is measured. The sensor is im... View full abstract»

• ### A 0.55-V, 28-ppm/°C, 83-nW CMOS Sub-BGR With UltraLow Power Curvature Compensation

Publication Year: 2018, Page(s):95 - 106
| | PDF (2685 KB) | HTML

This paper proposes an ultralow power, high precision sub bandgap voltage reference (sub-BGR) for low-voltage self-powered devices. A novel ultralow power curvature compensation circuit is proposed to improve the temperature coefficient over a wide temperature range. A switch capacitor voltage divider with improved leakage current reduction switches is used to obtain a high accuracy and a low powe... View full abstract»

• ### Analysis and Design of Voltage-Controlled Oscillator Based Analog-to-Digital Converter

Publication Year: 2010, Page(s):18 - 30
Cited by:  Papers (94)  |  Patents (5)
| | PDF (1424 KB) | HTML

A voltage-controlled oscillator (VCO) based analog-to-digital converter (ADC) is a time-based architecture with a first-order noise-shaping property, which can be implemented using a VCO and digital circuits. This paper analyzes the performance of VCO-based ADCs in the presence of nonidealities such as jitter, nonlinearity, mismatch, and the metastability of D flip-flops. Based on this analysis, d... View full abstract»

• ### A K-/Ka-Band Concurrent Dual-Band Single-Ended Input to Differential Output Low-Noise Amplifier Employing a Novel Transformer Feedback Dual-Band Load

Publication Year: 2018, Page(s):1 - 12
| | PDF (3863 KB)

A concurrent dual-band single-ended input to differential output (single-ended-to-differential) low-noise amplifier (LNA) employing a novel transformer feedback single-ended-to-differential dual-band load is proposed. The developed LNA topology is flexible in controlling the stopband notch frequency by optimizing the transformer's self-inductance and coupling coefficient. It also has a unique adva... View full abstract»

• ### Continuous-Time Delta-Sigma Modulators With Time-Interleaved FIR Feedback

Publication Year: 2018, Page(s):434 - 443
| | PDF (2906 KB) | HTML

The use of a single-bit quantizer in a wideband CTΔΣM is attractive, as the quantizer can be implemented in a power and area-efficient manner. Unfortunately, 1-bit CTΔΣMs are plagued by a host of difficulties. Clock jitter and quantizer metastability are particularly problematic, and the higher loop filter linearity needed to process the full-scale feedback waveform res... View full abstract»

• ### Analysis and Optimization of Direct-Conversion Receivers With 25% Duty-Cycle Current-Driven Passive Mixers

Publication Year: 2010, Page(s):2353 - 2366
Cited by:  Papers (92)  |  Patents (5)
| | PDF (2929 KB) | HTML

The performance of zero-IF receivers with current-driven passive mixers driven by 25% duty-cycle quadrature clocks is studied and analyzed. It is shown that, in general, these receivers outperform the ones that utilize passive mixers with 50% duty-cycle clocks. The known problems in receivers with 50% duty-cycle mixers, such as having unequal high- and low-side conversion gains, unexpected IIP2 an... View full abstract»

• ### A frequency compensation scheme for LDO voltage regulators

Publication Year: 2004, Page(s):1041 - 1050
Cited by:  Papers (154)  |  Patents (7)
| | PDF (576 KB) | HTML

A stable low dropout (LDO) voltage regulator topology for low equivalent series resistance (ESR) capacitive loads is presented. The proposed scheme generates a zero internally instead of relying on the zero generated by the load capacitor and its ESR combination for stability. It is demonstrated that this scheme realizes robust frequency compensation, facilitates the use of multilayer ceramic capa... View full abstract»

• ### Synthesis of High Gain Operational Transconductance Amplifiers for Closed-Loop Operation Using a Generalized Controller-Based Compensation Method

Publication Year: 2016, Page(s):1794 - 1806
Cited by:  Papers (1)
| | PDF (3404 KB) | HTML

This paper presents a systematic procedure that can be used to create operational transconductance amplifiers (OTAs) for closed-loop operation using multiple low-gain stages to realize extremely high DC gain. Such devices are necessary to realize analog functions with demanding absolute accuracy requirements, e.g., high-resolution ADCs and DACs. The principle is based on the cascade of undamped in... View full abstract»

• ### Energy-Efficient Processor for Blind Signal Classification in Cognitive Radio Networks

Publication Year: 2014, Page(s):587 - 599
Cited by:  Papers (16)
| | PDF (2229 KB) | HTML

Blind modulation classification is of vital importance in spectrum surveillance applications and future heterogeneous wireless networks. In standardized wireless systems, modulation classification can be performed through exhaustive search of known signal features. Most commonly used classifiers are based on the detection of cyclostationary features, which are second-order moments of a signal, rel... View full abstract»

• ### Design and Hardware Implementation of Neuromorphic Systems With RRAM Synapses and Threshold-Controlled Neurons for Pattern Recognition

Publication Year: 2018, Page(s):1 - 13
| | PDF (9615 KB)

In this paper, a hardware-realized neuromorphic system for pattern recognition is presented. The system directly captures images from the environment, and then conducts classification using a single layer neural network. Metal-oxide resistive random access memory (RRAM) is used as electronic synapses, and threshold-controlled neurons are proposed as postsynaptic neurons to save the system area and... View full abstract»

• ### BiCMOS-Based Compensation: Toward Fully Curvature-Corrected Bandgap Reference Circuits

Publication Year: 2018, Page(s):1210 - 1223
| | PDF (3807 KB) | HTML

We present a novel BiCMOS-based temperature compensation technique aiming at complete correction of the curvature in the temperature response of bandgap references. The source of the appearance of this curvature is because the well-known nonlinear term T ln(T) in the base-emitter voltage (VBE) is not completely canceled across all temperature points. Here, we show that the gate-source v... View full abstract»

• ### Finite-Time H∞ State Estimation for Discrete Time-Delayed Genetic Regulatory Networks Under Stochastic Communication Protocols

Publication Year: 2018, Page(s): 1
| | PDF (1094 KB)

This paper investigates the problem of finite-time H∞ state estimation for discrete time-delayed genetic regulatory networks under stochastic communication protocols (SCPs). The network measurements are transmitted from two groups of sensors to a remote state estimator via two independent communication channels of limited bandwidths, and two SCPs are utilized to orchestrate the transmission... View full abstract»

• ### Memristor-Based Circuit Design for Multilayer Neural Networks

Publication Year: 2018, Page(s):677 - 686
| | PDF (2210 KB) | HTML

Memristors are promising components for applications in nonvolatile memory, logic circuits, and neuromorphic computing. In this paper, a novel circuit for memristor-based multilayer neural networks is presented, which can use a single memristor array to realize both the plus and minus weight of the neural synapses. In addition, memristor-based switches are utilized during the learning process to u... View full abstract»

• ### Analysis and Design Strategy of UHF Micro-Power CMOS Rectifiers for Micro-Sensor and RFID Applications

Publication Year: 2007, Page(s):153 - 166
Cited by:  Papers (155)  |  Patents (2)
| | PDF (1907 KB) | HTML

Design strategy and efficiency optimization of ultrahigh-frequency (UHF) micro-power rectifiers using diode-connected MOS transistors with very low threshold voltage is presented. The analysis takes into account the conduction angle, leakage current, and body effect in deriving the output voltage. Appropriate approximations allow analytical expressions for the output voltage, power consumption, an... View full abstract»

• ### A Two-Stage Fully Differential Inverter-Based Self-Biased CMOS Amplifier With High Efficiency

Publication Year: 2011, Page(s):1591 - 1603
Cited by:  Papers (36)  |  Patents (1)
| | PDF (1735 KB) | HTML

A two-stage fully differential CMOS amplifier comprising inverters as input structures and employing self-biasing techniques is presented. The proposed amplifier benefits from an optimum compensation through time-domain optimization which permits achieving high energy efficiency. Moreover, it achieves the highest efficiency of its class and although it relies on a quasi-class-A topology, it is com... View full abstract»

• ### Kron Reduction of Graphs With Applications to Electrical Networks

Publication Year: 2013, Page(s):150 - 163
Cited by:  Papers (117)
| | PDF (3757 KB) | HTML

Consider a weighted undirected graph and its corresponding Laplacian matrix, possibly augmented with additional diagonal elements corresponding to self-loops. The Kron reduction of this graph is again a graph whose Laplacian matrix is obtained by the Schur complement of the original Laplacian matrix with respect to a specified subset of nodes. The Kron reduction process is ubiquitous in classic ci... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK