# IEEE Transactions on Circuits and Systems I: Regular Papers

Includes the top 50 most frequently accessed documents for this publication according to the usage statistics for the month of

• ### Efficient Hardware Architectures for Deep Convolutional Neural Network

Publication Year: 2018, Page(s):1941 - 1953
Cited by:  Papers (3)
| | PDF (1975 KB) | HTML

Convolutional neural network (CNN) is the state-of-the-art deep learning approach employed in various applications. Real-time CNN implementations in resource limited embedded systems are becoming highly desired recently. To ensure the programmable flexibility and shorten the development period, field programmable gate array is appropriate to implement the CNN models. However, the limited bandwidth... View full abstract»

• ### Switched-Capacitor/Switched-Inductor Structures for Getting Transformerless Hybrid DC–DC PWM Converters

Publication Year: 2008, Page(s):687 - 696
Cited by:  Papers (512)  |  Patents (1)
| | PDF (1294 KB) | HTML

A few simple switching structures, formed by either two capacitors and two-three diodes (C-switching), or two inductors and two-three diodes (L-switching) are proposed. These structures can be of two types: ldquostep-downrdquo and ldquostep-up.rdquo These blocks are inserted in classical converters: buck, boost, buck-boost, Cuk, Zeta, Sepic. The ldquostep-downrdquo C- or L-switching structures can... View full abstract»

• ### Full On-Chip CMOS Low-Dropout Voltage Regulator

Publication Year: 2007, Page(s):1879 - 1890
Cited by:  Papers (271)  |  Patents (14)
| | PDF (1617 KB) | HTML

This paper proposes a solution to the present bulky external capacitor low-dropout (LDO) voltage regulators with an external capacitorless LDO architecture. The large external capacitor used in typical LDOs is removed allowing for greater power system integration for system-on-chip (SoC) applications. A compensation scheme is presented that provides both a fast transient response and full range al... View full abstract»

• ### Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures

Publication Year: 2008, Page(s):1441 - 1454
Cited by:  Papers (119)  |  Patents (2)
| | PDF (1188 KB) | HTML

The need for highly integrable and programmable analog-to-digital converters (ADCs) is pushing towards the use of dynamic regenerative comparators to maximize speed, power efficiency and reconfigurability. Comparator thermal noise is, however, a limiting factor for the achievable resolution of several ADC architectures with scaled supply voltages. While mismatch in these comparators can be compens... View full abstract»

• ### The flipped voltage follower: a useful cell for low-voltage low-power circuit design

Publication Year: 2005, Page(s):1276 - 1291
Cited by:  Papers (292)  |  Patents (3)
| | PDF (1159 KB) | HTML

In this paper, a basic cell for low-power and/or low-voltage operation is identified. It is evidenced how different versions of this cell, coined as "flipped voltage follower (FVF)" have been used in the past for many applications. A detailed classification of basic topologies derived from the FVF is given. In addition, a comprehensive list of recently proposed low-voltage/low-power CMOS circuits ... View full abstract»

• ### Consensus of Multiagent Systems and Synchronization of Complex Networks: A Unified Viewpoint

Publication Year: 2010, Page(s):213 - 224
Cited by:  Papers (1060)
| | PDF (1045 KB) | HTML

This paper addresses the consensus problem of multiagent systems with a time-invariant communication topology consisting of general linear node dynamics. A distributed observer-type consensus protocol based on relative output measurements is proposed. A new framework is introduced to address in a unified way the consensus of multiagent systems and the synchronization of complex networks. Under thi... View full abstract»

• ### An Oversampling Stochastic ADC Using VCO-Based Quantizers

Publication Year: 2018, Page(s):4037 - 4050
| | PDF (7029 KB) | HTML

An oversampling stochastic analog-to-digital converter is presented. This stochastic converter spatially averages quantization errors in multiple voltage-controlled oscillator (VCO)-based quantizers. Unlike other stochastic converters, this proposed architecture does not require an inverse Gaussian cumulative density function estimator. The digital adder becomes an ideal estimator due to uncorrela... View full abstract»

• ### An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with −55 dBc Fractional and −91 dBc Reference Spurs

Publication Year: 2018, Page(s):3756 - 3768
| | PDF (4910 KB) | HTML

We propose a time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios, which is optimized for advanced CMOS. It is based on a 1/8-length time-to-digital converter (TDC) of stabilized 7-ps resolution, as well as wide tuning range, and fine-resolution class-F digitally controlled oscillator (DCO) with only switchable metal capacitors. The 0.4-mW TDC clocked at 40 MHz maintains ... View full abstract»

• ### Approximate Multipliers Based on New Approximate Compressors

Publication Year: 2018, Page(s):4169 - 4182
| | PDF (4744 KB) | HTML

Approximate computing is an emerging trend in digital design that trades off the requirement of exact computation for improved speed and power performance. This paper proposes novel approximate compressors and an algorithm to exploit them for the design of efficient approximate multipliers. By using the proposed approach, we have synthesized approximate multipliers for several operand lengths usin... View full abstract»

• ### The Circuit Theory Behind Coupled-Mode Magnetic Resonance-Based Wireless Power Transmission

Publication Year: 2012, Page(s):2065 - 2074
Cited by:  Papers (202)
| | PDF (2999 KB) | HTML

Inductive coupling is a viable scheme to wirelessly energize devices with a wide range of power requirements from nanowatts in radio frequency identification tags to milliwatts in implantable microelectronic devices, watts in mobile electronics, and kilowatts in electric cars. Several analytical methods for estimating the power transfer efficiency (PTE) across inductive power transmission links ha... View full abstract»

• ### A Novel Digital-Intensive Hybrid Polar-I/Q RF Transmitter Architecture

Publication Year: 2018, Page(s):4390 - 4403
Cited by:  Papers (1)
| | PDF (3773 KB) | HTML

A novel digital-intensive hybrid transmitter (TX) architecture is presented, combining conventional inphase and quadrature (I/Q) with constrained phase modulation. The proposed architecture utilizes an RF-DAC with phase modulated RF clock and adjusted I/Q components. By incorporating phase modulation the quadrature component is kept small while the inphase component approaches the complex signal e... View full abstract»

• ### X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories

Publication Year: 2018, Page(s):4219 - 4232
| | PDF (3431 KB) | HTML

Silicon-based static random access memories (SRAM) and digital Boolean logic have been the workhorse of the state-of-the-art computing platforms. Despite tremendous strides in scaling the ubiquitous metal-oxide-semiconductor transistor, the underlying von-Neumann computing architecture has remained unchanged. The limited throughput and energy-efficiency of the state-of-the-art computing systems, t... View full abstract»

• ### A frequency compensation scheme for LDO voltage regulators

Publication Year: 2004, Page(s):1041 - 1050
Cited by:  Papers (166)  |  Patents (7)
| | PDF (562 KB) | HTML

A stable low dropout (LDO) voltage regulator topology for low equivalent series resistance (ESR) capacitive loads is presented. The proposed scheme generates a zero internally instead of relying on the zero generated by the load capacitor and its ESR combination for stability. It is demonstrated that this scheme realizes robust frequency compensation, facilitates the use of multilayer ceramic capa... View full abstract»

• ### A High-Precision Resistor-Less CMOS Compensated Bandgap Reference Based on Successive Voltage-Step Compensation

Publication Year: 2018, Page(s):4086 - 4096
| | PDF (2413 KB) | HTML

A curvature-compensated resistor-less bandgap reference (BGR), which is fabricated in 0.5-μm CMOS process, is proposed in this paper. The BGR utilizes successive voltagestep compensation to produce a temperature-insensitive voltage reference (VR), including one AVGS step for first-order compensation and another one for higher order curvature correction. Moreover, a supply noise bypassing technique... View full abstract»

• ### IMAGING: In-Memory AlGorithms for Image processiNG

Publication Year: 2018, Page(s):4258 - 4271
Cited by:  Papers (1)
| | PDF (3371 KB) | HTML

Data-intensive applications such as image processing suffer from massive data movement between memory and processing units. The severe limitations on system performance and energy efficiency imposed by this data movement are further exacerbated with any increase in the distance the data must travel. This data transfer and its associated obstacles could be eliminated by the use of emerging non-vola... View full abstract»

• ### Design procedure for two-stage CMOS opamp with flexible noise-power balancing scheme

Publication Year: 2005, Page(s):1508 - 1514
Cited by:  Papers (49)
| | PDF (358 KB) | HTML

This paper presents a basic two-stage CMOS opamp design procedure that provides the circuit designer with a means to strike a balance between two important characteristics in electronic circuit design, namely noise performance and power consumption. It is shown in this paper that, unlike the previously reported design procedures, the proposed design step allows opamp designers to trade between noi... View full abstract»

• ### High-Efficiency Wireless Power Transfer for Biomedical Implants by Optimal Resonant Load Transformation

Publication Year: 2013, Page(s):867 - 874
Cited by:  Papers (120)
| | PDF (1382 KB) | HTML

Wireless power transfer provides a safe and robust way for powering biomedical implants, where high efficiency is of great importance. A new wireless power transfer technique using optimal resonant load transformation is presented with significantly improved efficiency at the cost of only one additional chip inductor component. The optimal resonant load condition for the maximized power transfer e... View full abstract»

• ### Consensus Tracking of Multi-Agent Systems With Lipschitz-Type Node Dynamics and Switching Topologies

Publication Year: 2014, Page(s):499 - 511
Cited by:  Papers (358)
| | PDF (3732 KB) | HTML

Distributed consensus tracking is addressed in this paper for multi-agent systems with Lipschitz-type node dynamics. The main contribution of this work is solving the consensus tracking problem without the assumption that the topology among followers is strongly connected and fixed. By using tools from M-matrix theory, a class of consensus tracking protocols based only on the relative states among... View full abstract»

• ### A 14-ENOB Delta-Sigma-Based Readout Architecture for ECoG Recording Systems

Publication Year: 2018, Page(s):4051 - 4061
| | PDF (2641 KB) | HTML

This paper presents a delta-sigma based readout architecture targeting electrocortical recording in brain stimulation applications. The proposed architecture can accurately record a peak input signal up to 240 mV in a power-efficient manner without saturating or employing offset rejection techniques. The readout architecture consists of a delta-sigma modulator with an embedded analog front-end. Th... View full abstract»

• ### An Architecture to Accelerate Convolution in Deep Neural Networks

Publication Year: 2018, Page(s):1349 - 1362
Cited by:  Papers (3)
| | PDF (3035 KB) | HTML

In the past few years, the demand for real-time hardware implementations of deep neural networks (DNNs), especially convolutional neural networks (CNNs), has dramatically increased, thanks to their excellent performance on a wide range of recognition and classification tasks. When considering real-time action recognition and video/image classification systems, latency is of paramount importance. T... View full abstract»

• ### A Fully-Integrated Low-Dropout Regulator With Full-Spectrum Power Supply Rejection

Publication Year: 2015, Page(s):707 - 716
Cited by:  Papers (46)
| | PDF (2674 KB) | HTML

A fully-integrated low-dropout regulator (LDO) with fast transient response and full spectrum power supply rejection (PSR) is proposed to provide a clean supply for noise-sensitive building blocks in wideband communication systems. With the proposed point-of-load LDO, chip-level high-frequency glitches are well attenuated, consequently the system performance is improved. A tri-loop LDO architectur... View full abstract»

• ### A Reconfigurable Streaming Deep Convolutional Neural Network Accelerator for Internet of Things

Publication Year: 2018, Page(s):198 - 208
Cited by:  Papers (6)
| | PDF (2922 KB) | HTML

Convolutional neural network (CNN) offers significant accuracy in image detection. To implement image detection using CNN in the Internet of Things (IoT) devices, a streaming hardware accelerator is proposed. The proposed accelerator optimizes the energy efficiency by avoiding unnecessary data movement. With unique filter decomposition technique, the accelerator can support arbitrary convolution w... View full abstract»

• ### Loop-Filter Design and Analysis for Delta-Sigma Modulators and Oversampled IIR Filters

Publication Year: 2018, Page(s):4121 - 4132
| | PDF (3008 KB) | HTML

Delta-sigma modulators spectrally shape quantization noise in discrete systems and are used extensively in communications and signal-processing systems. They are implemented using a loop-filter that processes the input and feed-back signals such that the closed loop behavior has a separate signal transfer function (STF) and noise transfer function (NTF). Loop-filter design often relies on special ... View full abstract»

• ### Design Methodology for Phase-Locked Loops Using Binary (Bang-Bang) Phase Detectors

Publication Year: 2017, Page(s):1637 - 1650
Cited by:  Papers (2)
| | PDF (3613 KB) | HTML

We present a linearized analysis of bang-bang phase-locked loops (PLLs) in the frequency domain that is complete and self-consistent. It enables the manual design of frequency synthesis PLLs for loop bandwidth, output phase noise and minimum jitter. Tradeoffs between various parameters of the loop become clear. The analysis is validated against measurements on four very different loops, and helps ... View full abstract»

• ### A Mixed-Signal Circuit Technique for Cancellation of Interferers Modulated by LO Phase-Noise in 4G/5G CA Transceivers

Publication Year: 2018, Page(s):3745 - 3755
| | PDF (3461 KB) | HTML

In RF transceivers operating in carrier-aggregation, spurs are generated on the transceiver chip which may down-convert any blocker signal located at the spur frequency into the receiver baseband. The blocker signal could either be the transceiver's own transmit signal when operating in frequency-division duplex, or a WiFi-related signal received by the antenna. This so-called modulated spur inter... View full abstract»

• ### Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey

Publication Year: 2011, Page(s):1 - 21
Cited by:  Papers (111)  |  Patents (7)
| | PDF (1691 KB) | HTML

This paper presents a tutorial overview of ΣΔ modulators, their operating principles and architectures, circuit errors and models, design methods, and practical issues. A review of the state of the art on nanometer CMOS implementations is described, giving a survey of cutting-edge ΣΔ architectures, with emphasis on their application to the next generation of wireless telecom systems. View full abstract»

Publication Year: 2016, Page(s):763 - 772
Cited by:  Papers (7)
| | PDF (1936 KB) | HTML

Small metal-oxide-metal (MOM) capacitors are essential to energy-efficient mixed-signal integrated circuit design. However, only few reports discuss their matching properties based on large sets of measured data. In this paper, we report matching properties of femtofarad and sub-femtofarad MOM vertical-field parallel-plate capacitors and lateral-field fringing capacitors. We study the effect of bo... View full abstract»

• ### A Fully Integrated Low-Dropout Regulator With Differentiator-Based Active Zero Compensation

Publication Year: 2018, Page(s):3578 - 3591
| | PDF (4484 KB) | HTML

An area-efficient low-power fully integrated output-capacitorless low-dropout regulator (OCL-LDO) is presented in this paper. The three-stage OCL-LDO utilizes an embedded differentiator-based active zero compensation technique together with adaptive biasing. The proposed active zero compensation helps enhance the unity-gain bandwidth (UGB) of the regulator with very small silicon area and almost n... View full abstract»

• ### Operational Transconductance Amplifier With Class-B Slew-Rate Boosting for Fast High-Performance Switched-Capacitor Circuits

Publication Year: 2018, Page(s):3769 - 3779
| | PDF (2565 KB) | HTML

In this paper, a technique for slew-rate (SR) boosting suitable for switched-capacitor circuits is proposed. The proposed technique makes use of a class-B auxiliary amplifier that generates a compensating current only when high SR is demanded by large signals. The proposed architecture employs simple circuitry to detect the need for a large output current by employing a highly sensitive pre-amplif... View full abstract»

• ### An On-Chip Self-Characterization of a Digital-to-Time Converter by Embedding it in a First-Order$\Delta\Sigma$Loop

Publication Year: 2018, Page(s):3734 - 3744
| | PDF (2608 KB) | HTML

To characterize an on-chip programmable delay in a low-cost and high-resolution manner, a built-in self-test based on a first-order ΔΣ time-to-digital converter with self-calibration is proposed and implemented in TSMC 28-nm CMOS. The system is self-contained, and only one digital clock is needed for the measurements. A system self-calibration algorithm is proposed to calibrate nonlinearities of t... View full abstract»

• ### A Self-Powered Supply-Sensing Biosensor Platform Using Bio Fuel Cell and Low-Voltage, Low-Cost CMOS Supply-Controlled Ring Oscillator With Inductive-Coupling Transmitter for Healthcare IoT

Publication Year: 2018, Page(s):2784 - 2796
Cited by:  Papers (4)
| | PDF (4093 KB) | HTML

This paper proposes a self-powered disposable supply-sensing biosensor platform for big-data-based healthcare applications. The proposed supply-sensing biosensor platform is based on bio fuel cells and a 0.23-V 0.25-μm zero-Vthall-digital CMOS supply-controlled ring oscillator with a current-driven pulse-interval-modulated inductive-coupling transmitter. The fully digital, and current-d... View full abstract»

• ### Continuous-Time Delta-Sigma Modulators Based on Passive RC Integrators

Publication Year: 2018, Page(s):3662 - 3674
| | PDF (5050 KB) | HTML

Due to the emerging systems with constraints in terms of power and costs, such as smart sensor interfaces for the Internet-of-Things, the design of the ADCs becomes very challenging. In this paper, energy and area efficient techniques for continuous-time (CT) delta-sigma modulators (AΣMs) are discussed. These techniques are based on increasing the contribution of the 1-bit comparator to the loop g... View full abstract»

• ### Synthesis of Ternary Logic Circuits Using 2:1 Multiplexers

Publication Year: 2018, Page(s):4313 - 4325
| | PDF (3101 KB) | HTML

Traditionally, binary decision diagram (BDD)-based algorithms are used to synthesize binary logic functions. A BDD can be transformed into circuit implementation by replacing each node in the BDD with a 2:1 multiplexer. Similarly, a ternary decision diagram can be transformed into circuit implementation using 3:1 Multiplexers. In this paper, we present a novel synthesis technique to implement tern... View full abstract»

• ### A CMOS V-Band PLL With a Harmonic Positive Feedback VCO Leveraging Operation in Triode Region for Phase-Noise Improvement

Publication Year: 2018, Page(s):1 - 13
| | PDF (4496 KB)

This paper presents a 53-61 GHz low-power charge-pump integer-N type-II PLL, employing a class-D V-band voltage control oscillator. Transistors in the VCO enter deep triode region to achieve low DC power and phase noise. Pros and cons of the triode region are studied in this paper. We have explained how this region has been accurately exploited to reduce the phase-noise. This is unlike the general... View full abstract»

• ### CORDIC-Based Architecture for Computing Nth Root and Its Implementation

Publication Year: 2018, Page(s):4183 - 4195
Cited by:  Papers (1)
| | PDF (2623 KB) | HTML

This paper presents a COordinate Rotation Digital Computer (CORDIC)-based architecture for the computation of Nth root and proves its feasibility by hardware implementation. The proposed architecture performs the task of Nth root simply by shift-add operations and enables easy tradeoff between the speed (or precision) and the area. Technically, we divide the Nth root computation into three differe... View full abstract»

• ### Second-Order Equivalent Circuits for the Design of Doubly-Tuned Transformer Matching Networks

Publication Year: 2018, Page(s):4157 - 4168
| | PDF (2059 KB) | HTML

The doubly-tuned magnetic transformer, comprising coupled inductors shunted by capacitors, is today widely in use as interstage network and for impedance matching in silicon millimeter waves amplifiers. It provides several advantages, compared with simple LC resonators, but the design is made complex by the high order of the network, featuring multiple resonances, and by the large number of compon... View full abstract»

• ### Linearization Techniques for CMOS Low Noise Amplifiers: A Tutorial

Publication Year: 2011, Page(s):22 - 36
Cited by:  Papers (144)  |  Patents (4)
| | PDF (1569 KB) | HTML

This tutorial catalogues and analyzes previously reported CMOS low noise amplifier (LNA) linearization techniques. These techniques comprise eight categories: a) feedback; b) harmonic termination; c) optimum biasing; d) feedforward; e) derivative superposition (DS); f) IM2 injection; g) noise/distortion cancellation; and h) post-distortion. This paper also addresses broadband-LNA-linearization iss... View full abstract»

• ### A Fully Integrated Analog Front End for Biopotential Signal Sensing

Publication Year: 2018, Page(s):3800 - 3809
| | PDF (3248 KB) | HTML

A low-power fully-integrated analog front end for biopotential sensors is proposed. The signal conditioning circuitry features an integrating sampler and a digital-assisted electrode offset-cancellation loop. The chip is fabricated in a standard 0.18-μm CMOS process. The supply voltage is 1.2 V and the quiescent current is 7.7 μA. Measurement results show that the analog front end achieves an in-b... View full abstract»

• ### Energy-Efficient Neural Network Acceleration in the Presence of Bit-Level Memory Errors

Publication Year: 2018, Page(s):4285 - 4298
| | PDF (3813 KB) | HTML

As a result of the increasing demand for deep neural network (DNN)-based services, efforts to develop hardware accelerators for DNNs are growing rapidly. However, while highly efficient accelerators on convolutional DNNs (ConvDNNs) have been developed, less progress has been made with regards to fully-connected DNNs. Based on analysis of bit-level SRAM errors, we propose memory adaptive training w... View full abstract»

• ### Power Bounds and Energy Efficiency in Incremental$\Delta\Sigma$Analog-to-Digital Converters

Publication Year: 2018, Page(s):4110 - 4120
| | PDF (1652 KB) | HTML

Incremental analog-to-digital-converters (IADCs) are variants of ΔΣ ADCs, which have been increasingly used for low-power sensory applications in recent years. Most IADC applications require high resolution and high energy efficiency. In this paper, we present a systematic analysis of IADCs. We derive analytical design equations for practical IADC designs. Process limitations are included in the m... View full abstract»

• ### TEAM: ThrEshold Adaptive Memristor Model

Publication Year: 2013, Page(s):211 - 221
Cited by:  Papers (236)  |  Patents (1)
| | PDF (2472 KB) | HTML

Memristive devices are novel devices, which can be used in applications ranging from memory and logic to neuromorphic systems. A memristive device offers several advantages: nonvolatility, good scalability, effectively no leakage current, and compatibility with CMOS technology, both electrically and in terms of manufacturing. Several models for memristive devices have been developed and are discus... View full abstract»

• ### A 0.12–0.4 V, Versatile 3-Transistor CMOS Voltage Reference for Ultra-Low Power Systems

Publication Year: 2018, Page(s):3790 - 3799
| | PDF (2380 KB) | HTML

In this paper, we propose an ultra-low power compact 3-transistor voltage reference capable of operating at ultra-low supply voltages. The proposed circuit is based on the self-cascode MOSFET (SCM), which provides a reference voltage proportional to the threshold voltage (VT) difference of the two NMOS transistors that compose it. Reverse short-channel and narrow-width effects are explored to obta... View full abstract»

• ### A Full Ka-Band Power Amplifier With 32.9% PAE and 15.3-dBm Power in 65-nm CMOS

Publication Year: 2018, Page(s):2657 - 2668
| | PDF (3024 KB) | HTML

This paper presents a CMOS broadband millimeter wave power amplifier (PA) based on magnetically coupled resonator (MCR) matching network. The MCR matching network is analyzed theoretically. Design method for MCR-based broadband PA is proposed. For the PA's output matching network, the inductance ratio should be equal to the load/source resistance ratio to achieve broadband impedance transformation... View full abstract»

• ### Analysis and Optimization of Direct-Conversion Receivers With 25% Duty-Cycle Current-Driven Passive Mixers

Publication Year: 2010, Page(s):2353 - 2366
Cited by:  Papers (115)  |  Patents (5)
| | PDF (2929 KB) | HTML

The performance of zero-IF receivers with current-driven passive mixers driven by 25% duty-cycle quadrature clocks is studied and analyzed. It is shown that, in general, these receivers outperform the ones that utilize passive mixers with 50% duty-cycle clocks. The known problems in receivers with 50% duty-cycle mixers, such as having unequal high- and low-side conversion gains, unexpected IIP2 an... View full abstract»

• ### Finite-Time Bipartite Consensus for Multi-Agent Systems on Directed Signed Networks

Publication Year: 2018, Page(s):4336 - 4348
| | PDF (1871 KB) | HTML

This paper addresses the finite-time bipartite consensus problem for multi-agent systems (MASs) on a directed signed network. Some properties for signed digraphs are first investigated and two nonlinear control protocols are then designed for first- and second-order MASs, respectively, where agents may be influenced by bounded disturbances. Particularly, for MASs with second-order dynamics, a new ... View full abstract»

• ### Differential Capacitive Readout Circuit Using Oversampling Successive Approximation Technique

Publication Year: 2018, Page(s):4072 - 4085
| | PDF (3653 KB) | HTML

This paper designs a close loop Σ-Δ readout circuit for differential MEMS accelerometer. A technique named oversampling successive approximation (OSA) is employed to build basic amplifiers and integrators. This technique can largely reduce the gain error and thus low gain amplifier such as single stage amplifier is allowed to be used. As a result, the power consumption and chip area are reduced. H... View full abstract»

• ### Analysis and Design of a Multi-Core Oscillator for Ultra-Low Phase Noise

Publication Year: 2016, Page(s):529 - 539
Cited by:  Papers (21)
| | PDF (2669 KB) | HTML

In this paper, we exploit an idea of coupling multiple oscillators to reduce phase noise (PN) to beyond the limit of what has been practically achievable so far in a bulk CMOS technology. We then apply it to demonstrate for the first time an RF oscillator that meets the most stringent PN requirements of cellular basestation receivers while abiding by the process technology reliability rules. The o... View full abstract»

• ### Analysis and Design of Voltage-Controlled Oscillator Based Analog-to-Digital Converter

Publication Year: 2010, Page(s):18 - 30
Cited by:  Papers (111)  |  Patents (5)
| | PDF (1424 KB) | HTML

A voltage-controlled oscillator (VCO) based analog-to-digital converter (ADC) is a time-based architecture with a first-order noise-shaping property, which can be implemented using a VCO and digital circuits. This paper analyzes the performance of VCO-based ADCs in the presence of nonidealities such as jitter, nonlinearity, mismatch, and the metastability of D flip-flops. Based on this analysis, d... View full abstract»

• ### Nano-Ampere Low-Dropout Regulator Designs for IoT Devices

Publication Year: 2018, Page(s):4017 - 4026
| | PDF (5307 KB) | HTML

This paper presents two output-capacitor-free low-dropout regulators (LDOs) with nA quiescent current for Internet-of-Things (IoT) applications. The proposed LDO1 combines the dynamic current biasing and the adaptive current biasing techniques for drastically reducing the quiescent current to the nA level while achieving fast transient response. Based on LDO1, the proposed LDO2 adds an inverter-ba... View full abstract»

• ### Implications of Passive Mixer Transparency for Impedance Matching and Noise Figure in Passive Mixer-First Receivers

Publication Year: 2010, Page(s):3092 - 3103
Cited by:  Papers (109)  |  Patents (11)
| | PDF (559 KB) | HTML

In this paper, a class of passive mixer-first, LNA-less receivers is analyzed in depth. Quadrature passive mixers are shown to present the impedance of their baseband port to the RF port and vice versa. This transparency property, in combination with resistive feedback differential amplifiers, and “complex” feedback between the I and Q paths, can be used to control the impedance at the RF port. Th... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK