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Nanotechnology, IEEE Transactions on

Popular Articles (April 2015)

Includes the top 50 most frequently downloaded documents for this publication according to the most recent monthly usage statistics.
  • 1. The Role of Geometry Parameters and Fin Aspect Ratio of Sub-20nm SOI-FinFET: An Analysis Towards Analog and RF Circuit Design

    Publication Year: 2015 , Page(s): 546 - 554
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (937 KB) |  | HTML iconHTML  

    Nowadays FinFETs integrated into complex circuit applications can fulfill the demand of smartphones and tablets for better performance and make chips that can compute faster. This paper studies the impact of H_{{\rm F\in}} and W_{{\rm F\in}} variations on various performance matrices including static as well as dynamic figures of merit (FOMs). With the help of aspect ratio ( W_{{\rm F\in}}/H_{{\rm F\in}} ), the device is branched into three parts, i.e., FinFET, Trigate, and Planar MOSFET. This unique report is a presentation of a detailed analysis about the impact of fin height ( H_{{\rm F\in}} ) and width ( W_{{\rm F\in}} ) on various performances including the dc as well as ac FOMs. The static or low-frequency performances like threshold voltage ( V_{{\rm th}} ), on current ( I_{{\rm on}} ), off current ( I_{{\rm \off}} ), power dissipation, transconductance ( g_{{\rm m}} ), output conductance ( g_{{\rm d}} ), transconductance generation factor ( TGF = g_{{\rm m}}/I_{{\rm D}} ), early voltage ( V_{{\rm EA}} ), gain ( A_{{\rm V}} ), and dynamic or high-frequency performances as gate capacitance ( C_{{\rm \gg}} ), cutoff frequency ( f_{{\rm T}} ), output resistance (- inline-formula> R_{{\rm 0}} ), intrinsic delay are systematically presented with the variation of device geometry parameters. The results presented in this paper can be of great help to device engineers in designing 3-D devices as per their requirement. View full abstract»

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  • 2. Reconfigurable Terahertz Leaky-Wave Antenna Using Graphene-Based High-Impedance Surface

    Publication Year: 2015 , Page(s): 62 - 69
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (909 KB) |  | HTML iconHTML  

    The concept of graphene-based two-dimensional leaky-wave antenna (LWA), allowing both frequency tuning and beam steering in the terahertz band, is proposed in this paper. In its design, a graphene sheet is used as a tuning part of the high-impedance surface (HIS) that acts as the ground plane of such 2-D LWA. It is shown that, by adjusting the graphene conductivity, the reflection phase of the HIS can be altered effectively, thus controlling the resonant frequency of the 2-D LWA over a broad band. In addition, a flexible adjustment of its pointing direction can be achieved over a wide range, while keeping the operating frequency fixed. Transmission-line methods are used to accurately predict the antenna reconfigurable characteristics, which are further verified by means of commercial full-wave analysis tools. View full abstract»

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  • 3. Synthesis, Transfer, and Devices of Single- and Few-Layer Graphene by Chemical Vapor Deposition

    Publication Year: 2009 , Page(s): 135 - 138
    Cited by:  Papers (69)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (284 KB) |  | HTML iconHTML  

    The advance of graphene-based nanoelectronics has been hampered due to the difficulty in producing single- or few-layer graphene over large areas. We report a simple, scalable, and cost-efficient method to prepare graphene using methane-based CVD on nickel films deposited over complete Si/SiO2 wafers. By using highly diluted methane, single- and few-layer graphene were obtained, as confirmed by micro-Raman spectroscopy. In addition, a transfer technique has been applied to transfer the graphene film to target substrates via nickel etching. FETs based on the graphene films transferred to Si/SiO2 substrates revealed a weak p-type gate dependence, while transferring of the graphene films to glass substrate allowed its characterization as transparent conductive films, exhibiting transmittance of 80% in the visible wavelength range. View full abstract»

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  • 4. Design Guidelines for Sub-12 nm Nanowire MOSFETs

    Publication Year: 2015 , Page(s): 210 - 213
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (442 KB) |  | HTML iconHTML  

    Traditional thinking assumes that a light effective mass (m*), high mobility material will result in better transistor characteristics. However, sub-12-nm metal-oxide-semiconductor field effect transistors (MOSFETs) with light m* may underperform compared to standard Si, as a result of source to drain (S/D) tunneling. An optimum heavier mass can decrease tunneling leakage current, and at the same time, improve gate to channel capacitance because of an increased quantum capacitance (Cq). A single band effective mass model has been used to provide the performance trends independent of material, orientation and strain. This paper provides guidelines for achieving optimum m* for sub-12-nm nanowire down to channel length of 3 nm. Optimum m* are found to range between 0.2-1.0 m0 and more interestingly, these masses can be engineered within Si for both p-type and n-type MOSFETs. m* is no longer a material constant, but a geometry and strain dependent property of the channel material. View full abstract»

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  • 5. A Compact Analytical Model for the Drain Current of Gate-All-Around Nanowire Tunnel FET Accurate From Sub-Threshold to ON-State

    Publication Year: 2015 , Page(s): 358 - 362
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (444 KB) |  | HTML iconHTML  

    We present a compact analytical model for the drain current of a gate-all-around nanowire tunneling field effect transistor. The model takes into account the effect of oxide thickness, body doping, drain voltage, and gate metal work function. The model uses a tangent line approximation method to integrate the tunneling generation rate in the source-body depletion region. The accuracy of the model is tested against three dimensional numerical simulations calibrated using experimental results. The model predicts the drain current accurately in both the on-state (strong inversion), as well as in the sub-threshold region. View full abstract»

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  • 6. 3-D Finite Element Monte Carlo Simulations of Scaled Si SOI FinFET With Different Cross Sections

    Publication Year: 2015 , Page(s): 93 - 100
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1147 KB) |  | HTML iconHTML  

    Nanoscaled Si SOI FinFETs with gate lengths of 12.8 and 10.7 nm are simulated using 3-D finite element Monte Carlo (MC) simulations with 2-D Schrodinger-based quantum corrections. These nonplanar transistors are studied for two cross sections: rectangular-like and triangular-like, and for two channel orientations: (100) and (110). The 10.7-nm gate length rectangular-like FinFET is also simulated using the 3-D nonequilibrium Green's functions (NEGF) technique and the results are compared with MC simulations. The 12.8 and 10.7 nm gate length rectangular-like FinFETs give larger drive currents per perimeter by about 33- 37% than the triangular-like shaped but are outperformed by the triangular-like ones when normalised by channel area. The devices with a (100) channel orientation deliver a larger drive current by about 11% more than their counterparts with a (110) channel when scaled to 12.8 nm and to 10.7 nm gate lengths. ID - VG characteristics obtained from the 3-D NEGF simulations show a remarkable agreement with the MC results at low drain bias. At a high drain bias, the NEGF overestimates the on-current from about VG - VT = 0.3 V because the NEGF simulations do not include the scattering with interface roughness and ionized impurities. View full abstract»

    Open Access
  • 7. Use of Terahertz Photoconductive Sources to Characterize Tunable Graphene RF Plasmonic Antennas

    Publication Year: 2015 , Page(s): 390 - 396
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (536 KB) |  | HTML iconHTML  

    Graphene, owing to its ability to support plasmon polariton waves in the terahertz frequency range, enables the miniaturization and electrical tunability of antennas to allow wireless communications among nanosystems. One of the main challenges in the characterization and demonstration of graphene antennas is finding suitable terahertz sources to feed the antenna. This paper characterizes the performance of a graphene RF plasmonic antenna fed with a photoconductive source. The terahertz source is modeled and, by means of a full-wave EM solver, the radiated power as well as the tunable resonant frequency of the device is estimated with respect to material, laser illumination, and antenna geometry parameters. The results show that with this setup the antenna radiates terahertz pulses with an average power up to 1 μW and shows promising electrical frequency tunability. View full abstract»

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  • 8. Quantum Well InAs/AlSb/GaSb Vertical Tunnel FET With HSQ Mechanical Support

    Publication Year: 2015 , Page(s): 580 - 584
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (488 KB) |  | HTML iconHTML  

    A type-III (broken gap) band alignment heterojunction vertical in-line InAs/AlSb/GaSb tunnel FET, including a 2-nm-thin AlSb tunneling barrier is demonstrated. The impact of overlap and underlap gate is studied experimentally and supported further by quasi-stationary 2-D TCAD Sentaurus device simulations. Hydrogen silsesquioxane is used as a novel mechanical support structure to suspend the 10-nm-thin InAs drain with enough undercut to be able to demonstrate an overlap gate architecture. The overlap gate InAs/AlSb/GaSb TFET shows an ON current density of 22 μA/μm2 at V_{{\rm GS}} = V_{{\rm DS}} = 0.4 V and the subthreshold slope is 194 mV/decade at room temperature and 46 mV/decade at 100 K. View full abstract»

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  • 9. Controlling Grain Size and Continuous Layer Growth in Two-Dimensional MoS2 Films for Nanoelectronic Device Application

    Publication Year: 2015 , Page(s): 238 - 242
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (441 KB) |  | HTML iconHTML  

    We report that control over the grain size and lateral growth of monolayer MoS2 film, yielding a uniform large-area monolayer MoS2 film, can be achieved by submitting the SiO2 surfaces of the substrates to oxygen plasma treatment and modulating substrate temperature in chemical vapor deposition (CVD) process. Scanning electron microscopy and atomic force microscopy images and Raman spectra revealed that the MoS2 lateral growth could be controlled by the surface treatment conditions and process temperatures. Moreover, the obtained monolayer MoS2 films showed excellent scalable uniformity covering a centimeter-scale SiO2 /Si substrates, which was confirmed with Raman and photoluminescence mapping studies. Transmission electron microscopy measurements revealed that the MoS2 film of the monolayer was largely single crystalline in nature. Back-gate field effect transistors based on a CVD-grown uniform monolayer MoS2 film showed a good current on/off ratio of ~106 and a field effect mobility of 7.23 cm2/V·s. Our new approach to growing MoS2 films is anticipated to advance studies of MoS2 or other transition metal dichalcogenide material growth mechanisms and to facilitate the mass production of uniform high-quality MoS2 films for the commercialization of a variety of applications. View full abstract»

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  • 10. Domain Wall Memory-Layout, Circuit and Synergistic Systems

    Publication Year: 2015 , Page(s): 282 - 291
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2121 KB) |  | HTML iconHTML  

    Domain wall memory (DWM) is gaining significant attention for embedded cache application due to low standby power, excellent retention, and ability to store multiple bits per cell. Additionally, it provides fast access time, good endurance, and good retention. However, it suffers from poor write latency, shift latency, shift power, and write power. DWM is sequential in nature and latency of read/write operations depends on the offset of the bit from the read/write head. This paper investigates the circuit design challenges such as bitcell layout, head positioning, utilization factor of the nanowire, shift power, shift latency, and provides solutions to deal with these issues. A synergistic system is proposed by combining circuit techniques such as merged read/write heads (for compact layout), flipped-bitcell and shift gating (for shift power optimization), wordline strapping (for access latency), shift circuit design with two micro-architectural techniques: 1) segmented cache and 2) workload-aware dynamic shift and write current boosting to realize energy-efficient and robust DWM cache. Simulations show 3-33% performance and 1.2-14.4X power consumption improvement for cache segregation and 2.5-31% performance and 1.3-14.9X power enhancement for dynamic current boosting over a wide range of PARSEC benchmarks. View full abstract»

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  • 11. CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits

    Publication Year: 2011 , Page(s): 217 - 225
    Cited by:  Papers (20)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (773 KB) |  | HTML iconHTML  

    This paper presents a novel design of ternary logic gates using carbon nanotube (CNT) FETs (CNTFETs). Ternary logic is a promising alternative to the conventional binary logic design technique, since it is possible to accomplish simplicity and energy efficiency in modern digital design due to the reduced circuit overhead such as interconnects and chip area. A resistive-load CNTFET-based ternary logic design has been proposed to implement ternary logic based on CNTFET. In this paper, a novel design technique for ternary logic gates based on CNTFETs is proposed and compared with the existing resistive-load CNTFET logic gate designs. Especially, the proposed ternary logic gate design technique combined with the conventional binary logic gate design technique provides an excellent speed and power consumption characteristics in datapath circuit such as full adder and multiplier. Extensive simulation results using SPICE are reported to show that the proposed ternary logic gates consume significantly lower power and delay than the previous resistive-load CNTFET gates implementations. In realistic circuit application, the utilization of the proposed ternary gates combined with binary gates results in over 90% reductions in terms of the power delay product. View full abstract»

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  • 12. Building Memristor Applications: From Device Model to Circuit Design

    Publication Year: 2014 , Page(s): 1154 - 1162
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (627 KB) |  | HTML iconHTML  

    Since the memristor was first built in 2008 at HP Labs, no end of devices and models have been presented. Also, new applications appear frequently. However, the integration of the device at the circuit level is not straightforward, because available models are still immature and/or suppose high computational loads, making their simulation long and cumbersome. This study assists circuit/systems designers in the integration of memristors in their applications, while aiding model developers in the validation of their proposals. We introduce the use of a memristor application framework to support the work of both the model developer and the circuit designer. First, the framework includes a library with the best-known memristor models, being easily extensible with upcoming models. Systematic modifications have been applied to these models to provide better convergence and significant simulations speedups. Second, a quick device simulator allows the study of the response of the models under different scenarios, helping the designer with the stimuli and operation time selection. Third, fine tuning of the device including parameters variations and threshold determination is also supported. Finally, SPICE/Spectre subcircuit generation is provided to ease the integration of the devices in application circuits. The framework provides the designer with total control overconvergence, computational load, and the evolution of system variables, overcoming usual problems in the integration of memristive devices. View full abstract»

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  • 13. Paper-Based Lithium-Ion Batteries Using Carbon Nanotube-Coated Wood Microfibers

    Publication Year: 2013 , Page(s): 408 - 412
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (650 KB) |  | HTML iconHTML  

    Lithium-ion batteries using flexible paper-based current collectors have been developed. These current collectors were fabricated from wood microfibers that were coated with carbon nanotubes (CNT) through an electrostatic layer-by-layer nanoassembly process. The carbon nanotube mass loading of the presented (CNT-microfiber paper) current collectors is 10.1 μg/cm2. The capacities of the batteries made with the current collectors are 150 mAh/g for lithium cobalt oxide (LCO) half-cell, 158 mAh/g for lithium titanium oxide (LTO) half-cell, and 126 mAh/g for LTO/LCO full-cell. The fabrication approach of the CNT-microfiber paper current collectors, the assembly of the batteries, and the experimental results are presented and discussed. View full abstract»

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  • 14. Two Memristor SPICE Models and Their Applications in Microwave Devices

    Publication Year: 2014 , Page(s): 607 - 616
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1085 KB) |  | HTML iconHTML  

    This paper presents two simple SPICE circuit models of the memristor using two different kinds of integrators. These models expand and simplify the previous methods of solving the memristor's modeling equations presented by Hewlett-Packard Lab. The behaviors of the two memristor models are investigated when they are excited by a sinusoidal voltage source. Both models satisfy the general features of memristive systems such as having a zero-crossing property in the form of an i-v Lissajous figure. In order to explore the unique characteristics and applications of the memristor in microwave devices, first we incorporate the memristor in a microstrip transmission line as a load. We do the analysis using a finite-difference time-domain simulator integrated with a nonlinear SPICE circuit solver. Furthermore, we design a reconfigurable microstrip bandpass filter based on a memristor-loaded resonator, and utilize a memristor as a carrier-wave modulator connecting the microstrip patch antenna to the ground. View full abstract»

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  • 15. Investigation of the TiN Gate Electrode With Tunable Work Function and Its Application for FinFET Fabrication

    Publication Year: 2006 , Page(s): 723 - 730
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1849 KB) |  | HTML iconHTML  

    The titanium nitride (TiN) gate electrode with a tunable work function has successfully been deposited on the sidewalls of upstanding Si-fin channels of FinFETs by using a conventional reactive sputtering. It was found that the work function of the TiN (phiTiN) slightly decreases with increasing nitrogen (N2) gas flow ratio, RN=N2/(Ar+N2) in the sputtering, from 17% to 100%. The experimental threshold voltage (Vth) dependence on the RN shows that the more RN offers the lower Vth for the TiN gate n-channel FinFETs. The composition analysis of the TiN films with different RN showed that the more amount of nitrogen is introduced into the TiN films with increasing RN, which suggests that the lowering of phi TiN with increasing RN should be related to the increase in nitrogen concentration in the TiN film. The desirable Vth shift from -0.22 to 0.22 V was experimentally confirmed by fabricating n+ poly-Si and TiN gate n-channel multi-FinFETs without a channel doping. The developed simple technique for the conformal TiN deposition on the sidewalls of Si-fin channels is very attractive to the TiN gate FinFET fabrication View full abstract»

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  • 16. Memristor Multiport Readout: A Closed-Form Solution for Sneak Paths

    Publication Year: 2014 , Page(s): 274 - 282
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (5175 KB) |  | HTML iconHTML  

    In this paper, we introduce for the first time, a closed-form solution for the memristor-based memory sneak paths without using any gating elements. The introduced technique fully eliminates the effect of sneak paths by reading the stored data using multiple access points and evaluating a simple addition/subtraction on the different readings. The new method requires fewer reading steps compared to previously reported techniques, and has a very small impact on the memory density. To verify the underlying theory, the proposed system is simulated using Synopsys HSPICE showing the ability to achieve a 100% sneak-path error-free memory. In addition, the effect of quantization bits on the system performance is studied. View full abstract»

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  • 17. Graphene Terahertz Plasmon Oscillators

    Publication Year: 2008 , Page(s): 91 - 99
    Cited by:  Papers (136)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1000 KB) |  | HTML iconHTML  

    In this paper we propose and discuss coherent terahertz sources based on charge density wave (plasmon) amplification in two-dimensional graphene. The coupling of the plasmons to interband electron-hole transitions in population inverted graphene layers can lead to plasmon amplification through stimulated emission. Plasmon gain values in graphene can be very large due to the small group velocity of the plasmons and the strong confinement of the plasmon field in the vicinity of the graphene layer. We present a transmission line model for plasmon propagation in graphene that includes plasmon dissipation and plasmon interband gain due to stimulated emission. Using this model, we discuss design for terahertz plasmon oscillators and derive the threshold condition for oscillation taking into account internal losses and also losses due to external coupling. The threshold condition is shown to depend on the ratio of the external impedance and the characteristic impedance of the plasmon transmission line. The large gain values available at terahertz frequencies in graphene can lead to integrated oscillators that have dimensions in the 1-10 mum range. View full abstract»

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  • 18. Wideband Modeling of Graphene-Based Structures at Different Temperatures Using Hybrid FDTD Method

    Publication Year: 2015 , Page(s): 250 - 258
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2189 KB) |  | HTML iconHTML  

    An efficient finite-difference time-domain (FDTD) algorithm is proposed for studying frequency- and temperature-dependent characteristics of some graphene-based structures, with auxiliary differential equation-FDTD method and its conformal modification technique integrated together for handling such atomically thin and electrically dispersive periodic geometries. Numerical results are presented to show their tunable transmittances, surface plasmon polarization-mode characteristics and Fano resonances, where the effects of chemical potential of graphene, biasing electric field strength, as well as operating temperature are captured and investigated in detail. View full abstract»

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  • 19. Heterogeneous NEMS-CMOS DCM Buck Regulator for Improved Area and Enhanced Power Efficiency

    Publication Year: 2015 , Page(s): 140 - 151
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1982 KB) |  | HTML iconHTML  

    In CMOS switches, the input signal modulates the on-channel resistance for a constant gate voltage. This necessitates over design of CMOS switches. Also, further CMOS scaling in the nanometer regime has failed to improve energy efficiency due to increasing leakage energy. Looking beyond CMOS, nanoelectromechanical (NEM) relays are a promising class of emerging devices that exhibit energy-efficient switching and zero leakage operation. Ron of the NEM relay switch is constant and is insensitive to the gate slew rate. This creates a paradigm shift in design of power switches. This coupled with infinite Roff offers significant area and power advantages over CMOS. Numerous end applications of NEM relay logic circuits have been proposed recently, including digital logic and memory. NEMS-based miniature switches form an interesting alternative in power management integrated circuits, the area of which is primarily dominated by CMOS power transistors. This study explores discontinuous-conduction mode buck regulator with specifications suitable for portable applications using a NEMS-CMOS hybrid design, and the results are compared against a standard commercial 0.35-μm CMOS implementation. The electromechanical model has been developed for a suspended gate relay operating at 1 V with a nominal air gap of 5-10 nm published in the literature. The model accounts for the mechanical, electrical, and dispersion effects in the relay. This study shows that NEMS-CMOS hybrid dc-dc converter has an area savings of 60% over CMOS and achieves an overall higher efficiency over CMOS, with a peak efficiency of 94.3% at 100 mA. View full abstract»

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  • 20. Interference Modeling and Capacity Analysis for Microfluidic Molecular Communication Channels

    Publication Year: 2015 , Page(s): 570 - 579
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (724 KB) |  | HTML iconHTML  

    The impact of the interference on the molecular communication (MC) between a transmitter and receiver pair which are connected through a microfluidic channel containing fluid flow is investigated. The interference modeling and the capacity analysis is performed based on the microfluidic channel geometry, the flow velocity, and the distance. During the analysis, time-scale of biological oscillators is specifically targeted, which is in the range of several minutes to a few hours. The signal-to-interference and noise ratio is shown to be constant with respect to the location of the interfering transmitter. The capacity of the MC link between the designated transmitter and the corresponding receiver is shown to be upper bounded by 1 bit/per channel use when exposed to a single interfering transmitter. For the multiple, i.e., N, transmitters, the decay of pairwise MC capacity is also studied as a factor of N. Finally, placement of the two transmitter and receiver pairs on the opposite sides of the microfluidic channel is studied. Three different microfluidic interference channel configurations, i.e., both-sided interference (microfluidic X channel), one-sided interference (microfluidic Z channel), and interference-free, are proposed based on the distance of the receiver from the interfering transmitter, microfluidic channel cross section, and the fluid flow velocity. For large-scale integration of chemical analysis systems on a microfluidic chip, the provided information-theoretic analysis and the capacity expressions for the MIC can be utilized to analyze the throughput of the chip, which can lead to improvement in efficiency and optimization of the design. View full abstract»

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  • 21. Novel Complementary Resistive Switch Crossbar Memory Write and Read Schemes

    Publication Year: 2015 , Page(s): 346 - 357
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1215 KB) |  | HTML iconHTML  

    Recent trends in emerging nonvolatile memory systems necessitate efficient read/write (R/W) schemes. Efficient solutions with zero sneak path current, nondestructive R/W operations, minimum area and low power are some of the key requirements. Toward this end, we propose a novel crossbar memory scheme using a configuration row of cells for assisting R/W operations. The proposed write scheme minimizes the overall power consumption compared to the previously proposed write schemes and reduces the state drift problem. We also propose two read schemes, namely, assisted-restoring and self-resetting read. In assisted-restoring scheme, we use the configuration cells which are used in the write scheme, whereas we implement additional circuitry for self-reset which addresses the problem of destructive read. Moreover, by formulating an analytical model of R/W operation, we compare the various schemes. The overhead for the proposed assisted-restoring write/read scheme is an extra redundant row for the given crossbar array. For a typical array size of 200 × 200 the area overhead is about 0.5%, however, there is a 4X improvement in power consumption compared to the recently proposed write schemes. Quantitative analysis of the proposed scheme is analyzed by using simulation and analytical models. View full abstract»

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  • 22. Annealing-Free Solution-Processed Silver Nanowire-Polymer Composite Transparent Electrodes and Flexible Device Applications

    Publication Year: 2015 , Page(s): 36 - 41
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (587 KB) |  | HTML iconHTML  

    By using ultrahigh aspect ratio (>2000:1) silver nanowires (AgNWs) and ethanol-diluted poly (3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) as the overcoating layer, we achieved flexible AgNW-polymer composite transparent electrodes of high conductivity and optical transmittance using facile solution processes at room temperature without annealing. The electrodes were applied in fabricating flexible capacitive pressure sensors and organic photovoltaic (OPV) devices. The pressure sensor with the composite electrodes presents three times higher sensitivity than that using ITO electrodes. A flexible 4 × 4 sensor array was also fabricated, which well proved the capability of the electrodes for spatially electronic signal collection and transmission. The fabricated flexible OPV device has a power conversion efficiency of 1.83%, which proves the potential of the electrodes for multilayer integration in optoelectronic device applications. View full abstract»

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  • 23. Potential of Ultralow-Power Cellular Neural Image Processing With Si/Ge Tunnel FET

    Publication Year: 2014 , Page(s): 627 - 629
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1038 KB) |  | HTML iconHTML  

    This letter studies the application of tunnel FET (TFET) for ultralow power image processing through cellular neural network (CNN). Through steeper switching slope, and thereby higher gm/IDS, a TFET-based CNN synapse can deliver the same performance as MOSFET even with a lower power. A TFET-based synapse is also scalable to the ultralow power regime; hence, by comprising more cells than MOSFET at the same power, TFET can reduce the multiplexing overheads in image processing with CNN. Utilizing unique properties of TFET, we show an improved performance for low power image processing using TFET. View full abstract»

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  • 24. Benchmarking nanotechnology for high-performance and low-power logic transistor applications

    Publication Year: 2005 , Page(s): 153 - 158
    Cited by:  Papers (232)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (520 KB) |  | HTML iconHTML  

    Recently there has been tremendous progress made in the research of novel nanotechnology for future nanoelectronic applications. In particular, several emerging nanoelectronic devices such as carbon-nanotube field-effect transistors (FETs), Si nanowire FETs, and planar III-V compound semiconductor (e.g., InSb, InAs) FETs, all hold promise as potential device candidates to be integrated onto the silicon platform for enhancing circuit functionality and also for extending Moore's Law. For high-performance and low-power logic transistor applications, it is important that these research devices are frequently benchmarked against the existing Si logic transistor data in order to gauge the progress of research. In this paper, we use four key device metrics to compare these emerging nanoelectronic devices to the state-of-the-art planar and nonplanar Si logic transistors. These four metrics include: 1) CV/I or intrinsic gate delay versus physical gate length Lg; 2) energy-delay product versus Lg; 3) subthreshold slope versus Lg; and 4) CV/I versus on-to-off-state current ratio ION/IOFF. The results of this benchmarking exercise indicate that while these novel nanoelectronic devices show promise and opportunities for future logic applications, there still remain shortcomings in the device characteristics and electrostatics that need to be overcome. We believe that benchmarking is a key element in accelerating the progress of nanotechnology research for logic transistor applications. View full abstract»

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  • 25. The Impact of Junction Doping Distribution on Device Performance Variability and Reliability for Fully Depleted Silicon on Insulator With Thin Box Layer MOSFETs

    Publication Year: 2015 , Page(s): 330 - 337
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (817 KB) |  | HTML iconHTML  

    In this study, we investigate the impact of junction doping distribution (LDD/halo) on variations and asymmetry of device characteristics for fully depleted silicon on insulator (FDSOI) with ultrathin buried oxide layer nMOSFET. The device performance and hot carrier induced degradations have also been examined. Junction doping dose of LDD/halo affects the effective channel length, parasitic source/drain resistance, and channel mobility. High junction doping dose enhances the device's performance but degrades device stability and reliability. Compared to high junction doping FDSOI nMOSFET, low junction doping device has lower device variability, better symmetry, and reliability, but suffers lower channel mobility and device driving capability. View full abstract»

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  • 26. Memristor Applications for Programmable Analog ICs

    Publication Year: 2011 , Page(s): 266 - 274
    Cited by:  Papers (38)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (565 KB) |  | HTML iconHTML  

    This paper demonstrates that memristors can be used to implement programmable analog circuits, leveraging memristor's fine-resolution programmable resistance without causing perturbations due to parasitic components. Fine-resolution programmable resistance is achieved by varying the amount of flux across memristors. The resistance programming can be achieved by controlling the input pulsewidth and its frequency. For demonstration, a memristor is designed for a pulse-programmable midband differential gain amplifier with fine resolution. View full abstract»

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  • 27. Low Complexity Design of Ripple Carry and Brent–Kung Adders in QCA

    Publication Year: 2012 , Page(s): 105 - 119
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2395 KB) |  | HTML iconHTML  

    The design of adders on quantum dot cellular automata (QCA) has been of recent interest. While few designs exist, investigations on reduction of QCA primitives (majority gates and inverters) for various adders are limited. In this paper, we present a number of new results on majority logic. We use these results to present efficient QCA designs for the ripple carry adder (RCA) and various prefix adders. We derive bounds on the number of majority gates for -bit RCA and -bit Brent-Kung, Kogge-Stone, Ladner-Fischer, and Han-Carlson adders. We further show that the Brent-Kung adder has lower delay than the best existing adder designs as well as other prefix adders. In addition, signal integrity and robustness studies show that the proposed Brent-Kung adder is fairly well-suited to changes in time-related parameters as well as temperature. Detailed simulations using QCADesigner are presented. View full abstract»

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  • 28. Forming Freeform Source Shapes by Utilizing Particle Swarm Optimization to Enhance Resolution in Extreme UV Nanolithography

    Publication Year: 2015 , Page(s): 322 - 329
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (876 KB) |  | HTML iconHTML  

    This paper investigated pixel-based source shape optimization to enhance the resolution in a projection extreme UV (EUV) lithography system. The particle swarm optimization method was proposed to optimize the source shapes. The layout patterns of the masks were corrected using model-based optical proximity correction. The optimal source shape in an EUV lithography system was verified using numerical calculations, through which the aerial image of two types of mask pattern exposure was determined. The two types of mask patterns were a logic line/space (L/S) pattern with a critical dimension (CD) of 16 nm and a SRAM contact hole (CH) pattern with a CD of 45 nm. Two significant metrics were used to evaluate the modified source performance: the latent image intensity and process window. Results from the numerical calculations showed that for L/S target patterns, using the optimal source produced a latent image error of 13.02% after exposure that was superior to that of traditional off-axis source exposure. The latent image intensity of the mask between the lines and the gaps differed substantially, corner rounding situations had effectively improved, and no bridges were observed. Concerning CH target patterns, using the optimal source produced a latent image error of 0.04% after exposure that was also superior to that of traditional sources. The latent image intensity between the holes and the gaps also differed significantly, and the latent image intensity distribution at the four corners of the CH had straight angles. Because the source shapes calculated in this study comprised pixel-based sources, the controllable microelectromechanical system mirror array chip was used to match each mirror to each pixel source, and the calculated source shapes were successfully projected. View full abstract»

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  • 29. Synthesis of Majority/Minority Logic Networks

    Publication Year: 2015 , Page(s): 473 - 483
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1533 KB) |  | HTML iconHTML  

    As CMOS technology reaches its physical limits, new technologies such as quantum-dot cellular automata, single electron tunneling, and tunneling-phase logic are being proposed as alternatives to CMOS technology. These technologies use either majority or minority logic to implement logic functions. Existing majority/minority logic synthesis methods, based on three-feasible networks, often result in suboptimal solutions. In this paper, an efficient algorithm to find the minimal majority gate mapping, along with a majority expression look-up table (MLUT) is developed. Based on the MLUT, a comprehensive majority/minority logic synthesis technique is proposed. A redundancy removal method is also developed to further optimize the synthesized circuit. This technique makes effort toward achieving different optimization goals and results in fewer majority gates and fewer levels than previous methods. For the 29 MCNC benchmark circuits, when targeted to optimize the logic levels, there is an average reduction of 7.0% in the number of levels as well as 6.3% in the number of gates. For optimization targeted to reduce gate counts, there is an average reduction of 9.5% in the number of gates as well as 0.8% in the number of levels, as compared to the best available method. View full abstract»

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  • 30. Comparative Analysis of Dielectric-Modulated FET and TFET-Based Biosensor

    Publication Year: 2015 , Page(s): 427 - 435
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1517 KB) |  | HTML iconHTML  

    An extensive study is presented to describe the impact of partial hybridization on the device electrostatics and on current of a silicon dielectric-modulated tunnel field effect transistor (DM-TFET). To gain insight into the various design considerations and factors influencing the sensitivity, both process-related issue such as cavity length variation and real-time issues related to biomolecules behavior such as partial hybridization, charge, and position of receptors/target molecules have been investigated through extensive numerical simulations. The results indicate that TFET-based sensor does not suffer from scaling issues and thus can help in miniaturization without compromising the sensitivity, unlike a nanogap-embedded DM-FET. View full abstract»

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  • 31. Dipole Nantennas Terminated by Traveling Wave Rectifiers for Ambient Thermal Energy Harvesting

    Publication Year: 2014 , Page(s): 767 - 778
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (8325 KB) |  | HTML iconHTML  

    In this paper, rectennas formed from nanodipole antennas terminated by plasmonic metal-insulator-metal (MIM) travelling wave transmission line rectifiers are developed for ambient thermal energy harvesting at 30 THz. The transmission lines are formed from two strips coupled either vertically or laterally. A systematic design approach is presented, that shows how different components can be integrated with each other with maximum radiation receiving nantenna efficiency, maximum coupling efficiency between nantenna and rectifier, and maximum MIM diode rectifier efficiency. The tunneling current of the rectifier is calculated using the transfer matrix method and the nonequilibrium Green's function. A detailed parametric study of the coupled strips plasmonic transmission lines is presented and thoroughly discussed. The overall efficiencies of the proposed travelling wave rectennas are fully expressed and compared. View full abstract»

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  • 32. Quantitative theory of nanowire and nanotube antenna performance

    Publication Year: 2006 , Page(s): 314 - 334
    Cited by:  Papers (118)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (925 KB) |  | HTML iconHTML  

    We present quantitative predictions of the performance of nanotubes and nanowires as antennas, including the radiation resistance, the input reactance and resistance, and antenna efficiency, as a function of frequency and nanotube length. Particular attention is paid to the quantum capacitance and kinetic inductance. We develop models for both far-field antenna patterns as well as near-field antenna-to-antenna coupling. In so doing, we also develop a circuit model for a transmission line made of two parallel nanotubes, which has applications for nanointerconnect technology. Finally, we derive an analog of Hallen's integral equation appropriate for single-walled carbon nanotube antennas View full abstract»

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  • 33. Flexible Janus Nanofiber to Help Achieve Simultaneous Enhanced Magnetism-Upconversion Luminescence Bifunction

    Publication Year: 2015 , Page(s): 243 - 249
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (604 KB) |  | HTML iconHTML  

    Novel flexible Janus nanofibers with magnetism-upconversion luminescence bifunction have been successfully fabricated via electrospinning technology using a homemade parallel spinneret. NaYF4:Yb3+, Er3+ and Fe3O4 nanoparticles (NPs) were, respectively, incorporated into polyvinyl pyrrolidone (PVP) and electrospun into Janus nanofibers with NaYF4:Yb3+, Er 3+/PVP as one strand nanofiber of the Janus nanofiber and Fe3O4/PVP as the other one. The morphologies and properties of the final products were investigated in detail by X-ray diffractometry, scanning electron microscopy, transmission electron microscopy, energy dispersive spectrometry, vibrating sample magnetometry and fluorescence spectroscopy. The results reveal that Janus nanofibers simultaneously possess superior magnetic and upconversion luminescent properties due to their special nanostructure, and the upconversion luminescent characteristics and saturation magnetizations of the Janus nanofibers can be tuned by adjusting the content of NaYF4:Yb3+, Er3+ NPs and Fe3O4 NPs. Compared with Fe3O4/NaYF4:Yb3+, Er3+/PVP composite nanofibers, the magnetism-upconversion luminescence bifunctional Janus nanofibers provide better performances owing to isolating NaYF4:Yb3+, Er3+ NPs from Fe3O4 NPs. The novel magnetism-upconversion luminescence bifunctional Janus nanofibers have potential applications in the fields of new nano-bio-label materials, drug target delivery materials and future nanodevices owing to their excellent magnetic-upconversion luminescent properties, flexibility and peculiar nanostructure. More importantly, the new strategy and construction technology are of universal significance to fabricate other bifunctional Janus nanofibers. View full abstract»

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  • 34. Design and Synthesis of Ultralow Energy Spin-Memristor Threshold Logic

    Publication Year: 2014 , Page(s): 574 - 583
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1399 KB) |  | HTML iconHTML  

    A threshold logic gate performs weighted sum of multiple inputs and compares the sum with a threshold. We propose spin-memristor threshold logic (SMTL) gates, which employ a memristive cross-bar array to perform current-mode summation of binary inputs, whereas the low-voltage fast-switching spintronic threshold devices carry out the threshold operation in an energy efficient manner. Field-programmable SMTL gate arrays can operate at a small terminal voltage of ~50 mV, resulting in ultralow power consumption in gates as well as programmable interconnect networks. We evaluate the performance of SMTL using threshold logic synthesis. Results for common benchmarks show that SMTL-based programmable logic hardware can be more than 100 × energy efficient than the state-of-the-art CMOS field-programmable gate array. View full abstract»

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  • 35. Investigation on High-Performance CMOS With p-Ge and n-InGaAs MOSFETs for Logic Applications

    Publication Year: 2015 , Page(s): 275 - 281
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (967 KB) |  | HTML iconHTML  

    CMOS circuits built using Ge-channel p-MOSFETs and InGaAs-channel n-MOSFETs have shown promise for high-performance logic applications. In this paper, we investigate for the first time the performance of such circuits using extensive device simulations. The digital performance of a CMOS inverter is evaluated in terms of noise margins, rise time, fall time, and propagation delay. Furthermore, frequency of oscillations of a three-stage ring oscillator is obtained for varying ratio of the channel width of the p- and the n-MOSFETs, respectively (Wp/Wn). Our investigations reveal that the CMOS circuits comprising of p-Ge and n-InGaAs MOSFETs outperform their equally sized Si counterpart. Moreover, superior performance of Ge/InGaAs-based CMOS is obtained for In0.75Ga0.25As channel with width ratio (Wp/Wn) of 10: 1. Also, Ge/InGaAs CMOS is found to lose its advantages over Si CMOS for 5 × 1012 eV-1 · cm-2. View full abstract»

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  • 36. Effect of Drain Doping Profile on Double-Gate Tunnel Field-Effect Transistor and its Influence on Device RF Performance

    Publication Year: 2014 , Page(s): 974 - 981
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (850 KB) |  | HTML iconHTML  

    In this paper, we have investigated the effect of drain doping profile on a double-gate tunnel field-effect transistor (DG-TFET) and its radio-frequency (RF) performances. Lateral asymmetric drain doping profile suppresses the ambipolar behavior, improves OFF-state current, reduces the gate-drain capacitance, and improves the RF performance. Further, placing the high-density layer in the channel near the source-channel junction, a reduction in the width of depletion region, improvement in ON-state current (ION), and subthreshold slope are analyzed for this asymmetric drain doping. However, it also improves many RF figures of merit for the DG-TFET. Furthermore, lateral asymmetric doping effects on RF performances are also checked for the various channel length. Therefore, this paper would be beneficial for a new generation of RF circuits and systems in a broad range of applications and operating frequencies covering RF spectrum. So, the RF figures of merit for the DG-TFET are analyzed in terms of transconductance (gm), unit-gain cutoff frequency (fT), maximum frequency of oscillation (fmax), and gain bandwidth product. For this, the RF figures of merit have been extracted from the V-parameter matrix generated by performing the small-signal ac analysis. Technology computer-aided design simulations have been performed by 2-D ATLAS, Silvaco International, Santa Clara, CA, USA. View full abstract»

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  • 37. Effect of Micro-Structured Copper as Cathode Material for P3HT-Based Diode

    Publication Year: 2015 , Page(s): 218 - 223
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1005 KB) |  | HTML iconHTML  

    Here, the effect of micro-structured cathode material on the device performance of indium tin oxide/poly(3-hexylethiophene)/copper diode (ITO/P3HT/Cu) is investigated. Two different forms of copper namely bulk metal (Cu{B}) and nanoparticle (Cu{N}) were used as top electrode to probe its effect on device performance. Crystallographic structure and nanoscale morphology of top Cu electrodes were characterized using X-ray diffraction and scanning electron microscopy. Electrode formed by evaporation of copper nanoparticle showed enhancement in current density. From capacitance based spectroscopy we observed that density of trap states in ITO/P3HT/copper larger size grain (Cu-LG) are one order greater than that in ITO/P3HT/copper smaller size grain (Cu-SG) device. View full abstract»

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  • 38. Carbon-nanotube-based voltage-mode multiple-valued logic design

    Publication Year: 2005 , Page(s): 168 - 179
    Cited by:  Papers (42)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1064 KB) |  | HTML iconHTML  

    Multivalued logic has always attracted the attention of digital system and logic designers. However, the high-performance and low-power CMOS process, which has been developed over the last two decades, has traditionally assisted successful circuit implementation of binary logic. Consequently, in spite of its large potential multivalued logic design is seldom a circuit designer's choice. This paper presents a novel method of multiple-valued logic design using carbon-nanotube field-effect transistors (CNFETs). The geometry-dependent threshold voltage of CNFETs has been effectively used to design a ternary logic family. We have developed a SPICE-compatible model of ballistic CNFETs that can account for varying geometries and operating conditions. SPICE simulations have been performed on the proposed logic gates, and the transfer characteristics as well as transient behavior have been extensively studied. Finally, a comparison in terms of power and performance of the ternary logic family vis-a`-vis traditional complementary field-effect transistor binary logic family has been presented. View full abstract»

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  • 39. Collocated Z-Axis Control of a High-Speed Nanopositioner for Video-Rate Atomic Force Microscopy

    Publication Year: 2015 , Page(s): 338 - 345
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1192 KB) |  | HTML iconHTML  

    A key hurdle to achieve video-rate atomic force microscopy (AFM) in constant-force contact mode is the inadequate bandwidth of the vertical feedback control loop. This paper describes techniques used to increase the vertical tracking bandwidth of a nanopositioner to a level that is sufficient for video-rate AFM. These techniques involve the combination of: a high-speed XYZ nanopositioner; a passive damping technique that cancels the inertial forces of the Z actuator which in turns eliminates the low 20-kHz vertical resonant mode of the nanopositioner; an active control technique that is used to augment damping to high vertical resonant modes at 60 kHz and above. The implementation of these techniques allows a tenfold increase in the vertical tracking bandwidth, from 2.3 (without damping) to 28.1 kHz. This allows high-quality, video-rate AFM images to be captured at 10 frames/s without noticeable artifacts associated with vibrations and insufficient vertical tracking bandwidth. View full abstract»

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  • 40. Effect of Line Defects on the Electrical Transport Properties of Monolayer MoS _{\bf 2} Sheet

    Publication Year: 2015 , Page(s): 51 - 56
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1076 KB) |  | HTML iconHTML  

    We present a computational study on the impact of line defects on the electronic properties of monolayer MoS2. Four different kinds of line defects with Mo and S as the bridging atoms, consistent with recent theoretical and experimental observations, are considered herein. We employ the density functional tightbinding (DFTB) method with a Slater-Koster-type DFTB-CP2K basis set for evaluating the material properties of perfect and the various defective MoS2 sheets. The transmission spectra are computed with a DFTB-non-equilibrium Green's function formalism. We also perform a detailed analysis of the carrier transmission pathways under a small bias and investigate the phase of the transmission eigenstates of the defective MoS2 sheets. Our simulations show a two to four fold decrease in carrier conductance of MoS2 sheets in the presence of line defects as compared to that for the perfect sheet. View full abstract»

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  • 41. Compensated Readout for High-Density MOS-Gated Memristor Crossbar Array

    Publication Year: 2015 , Page(s): 3 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (485 KB) |  | HTML iconHTML  

    Leakage current is one of the main challenges facing high-density MOS-gated memristor arrays. In this study, we show that leakage current ruins the memory readout process for high-density arrays, and analyze the tradeoff between the array density and its power consumption. We propose a novel readout technique and its underlying circuitry, which is able to compensate for the transistor leakage-current effect in the high-density gated memristor array. View full abstract»

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  • 42. A Memristor SPICE Implementation and a New Approach for Magnetic Flux-Controlled Memristor Modeling

    Publication Year: 2011 , Page(s): 250 - 255
    Cited by:  Papers (43)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (299 KB) |  | HTML iconHTML  

    This paper introduces a behavior model of a memristive soild-state device for simulation with a simulation program for integrated circuits emphasis (SPICE) compatible circuit simulator. After showing the underlying functional mechanics and model equations of a memristor the SPICE equivalent circuit based on a charge controlled memristor is presented and discussed. Hereafter, a magnetic flux controlled memristor model is introduced including technical description and SPICE implementation. It is shown that the presented SPICE models meet the requirements for simulations of multi memristor circuits. View full abstract»

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  • 43. Electromagnetic Performance of RF NEMS Graphene Capacitive Switches

    Publication Year: 2014 , Page(s): 70 - 79
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1572 KB) |  | HTML iconHTML  

    The RF performance of a nanoelectromechanical systems (NEMS) capacitive switch based on graphene is evaluated. Our results show that graphene can be a good candidate for the membrane of RF NEMS switches in applications where low actuation voltage and fast switching are required. The conductivity of the membrane is accurately modeled in the up- and down-state positions of the switch by considering the field effect of graphene. Rigorous full-wave simulations are then performed to obtain the scattering parameters of the switch. It is shown that graphene's conductivity variation due to electric field effect has a limited yet beneficial impact on the performance of the switch. It is also demonstrated that while monolayer graphene results in quite high switch losses at high frequency, the use of multilayer graphene, can considerably reduce the switch losses and improve the RF performance. Finally, an equivalent circuit model for the graphene-based RF NEMS switch is extracted and the results are compared with the full-wave 3-D electromagnetic simulation. These results motivate further efforts in the fabrication and characterization of graphene RF NEMS. View full abstract»

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  • 44. Investigation of Physically Unclonable Functions Using Flash Memory for Integrated Circuit Authentication

    Publication Year: 2015 , Page(s): 384 - 389
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (491 KB) |  | HTML iconHTML  

    Flash memory devices are investigated to confirm their application as physically unclonable functions (PUFs). Inherent fluctuations in the characteristics of flash memory devices, even with identical fabrication processes, produce different outputs, which are useful for device fingerprints. A difference in programming/erasing efficiency arises from a widely distributed threshold voltage. However, statistical fluctuations in the threshold voltage represent an advantage for PUF applications. The characteristics of PUFs, such as their unclonability, uncontrollability, unpredictability, and robustness, are investigated using fabricated flash memory devices. A simulation study is performed to support the experimental results and to show that the unpredictability is induced by variations in the gate dielectric thickness. View full abstract»

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  • 45. Efficient Multiternary Digit Adder Design in CNTFET Technology

    Publication Year: 2013 , Page(s): 283 - 287
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (920 KB) |  | HTML iconHTML  

    This letter presents an efficient multiternary digit (trit) adder design in carbon nanotube field effect transistor technology. The adder is based on an efficient single-trit full-adder design with low-complexity encoder and reduced complexity carry-generation unit. Further, we optimize the number of encoder and decoder blocks required while putting together several single-trit full-adder units to realize a multitrit adder. Extensive HSPICE simulation results show roughly 79% reduction in power-delay product for three-trit adders and 88 % reduction in power-delay product for nine-trit adders in comparison to a direct realization. View full abstract»

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  • 46. Using the Surface Plasmon Resonance of Au Nanoparticles to Enhance Ultraviolet Response of ZnO Nanorods-Based Schottky-Barrier Photodetectors

    Publication Year: 2015 , Page(s): 318 - 321
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (600 KB) |  | HTML iconHTML  

    Surface plasmon resonance mediated by Gold (Au) nanoparticles (NPs) was employed to enhance the ultraviolet (UV) response of ZnO nanorod (NR)-based Schottky-barrier photodetectors (SB-PDs). The defect-level emissions of ZnO NRs induce surface plasmon resonance in Au NPs and enhance the electromagnetic field near Au NPs, which excites a great deal of electrons from Au NPs crossing over the barrier height of Au NP/ZnO interface. This causes the band-to-band emission of ZnO (384 nm) is increased by a magnitude of three, and the deep-level emissions (450-700 nm) are drastically decreased as compared to ZnO NRs without coverings of Au NPs. Also, it drastically enhances the UV (340 nm)-to-visible (560 nm) rejection ratio from 115 to 443. The effect of surface plasmon resonance is verified by that the responsivity of SB-PD with the covering of Au NPs exhibits a greater increasing with applied reverse-bias voltage than that without Au NPs. View full abstract»

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  • 47. Synthesis of Atomically Thin {\bf MoS}_{\bf 2} Triangles and Hexagrams and Their Electrical Transport Properties

    Publication Year: 2014 , Page(s): 749 - 754
    Multimedia
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (520 KB) |  | HTML iconHTML  

    Atomically thin molybdenum disulfide (MoS2) triangles and hexagrams were prepared by a two-step growth ambient pressure chemical vapor deposition (APCVD) process. Molybdenum Trioxide (MoO3) nanobelts, a few microns in length and width, were prepared using a hydrothermal technique and utilized as the starting material. High temperature treatment of the MoO3 nanobelts followed by a rigorous sulfurization via APCVD processing provided different morphologies of MoS2 monolayers and bilayer (BL) sheets. Triangle and hexagram morphologies were characterized using Raman spectroscopy, photoluminescence (PL) measurements, scanning electron microscopy and atomic force microscopy (AFM). The regrowth step in the CVD process was proven to be ideal in enlarging the grain size. PL and Raman spectroscopy and AFM results confirmed the presence of monolayer and BL regions in the regrowth growth process. Triangle and hexagram domains are observed to be cooperatively nucleating and coalescing together to form large-area layers. Furthermore, the electrical transport properties of the synthesized MoS2 layers were studied. Electron mobility based on back gated field effect transistors was measured to be approximately 0.02 cm2/V. S. View full abstract»

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  • 48. Terahertz Communications in Human Tissues at the Nanoscale for Healthcare Applications

    Publication Year: 2015 , Page(s): 404 - 406
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (416 KB) |  | HTML iconHTML  

    This letter investigates nanoscale wireless communications in human tissues. Starting from propagation models, validated through real experiments, channel capacity and transmission ranges are derived for different physical transmission settings. Results highlight the challenges characterizing the communication in such a medium, thus, paving the way to novel research activities devoted to the design of pioneering nanomedical applications. View full abstract»

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  • 49. Design of a Nonvolatile 7T1R SRAM Cell for Instant-on Operation

    Publication Year: 2014 , Page(s): 905 - 916
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1388 KB) |  | HTML iconHTML  

    Energy consumption is a major concern in nanoscale CMOS ICs; the power-Off operational mode and low-voltage circuits have been proposed to alleviate energy dissipation. Static random access memories (SRAMs) are widely used in today's chips; nonvolatile SRAMs (NVSRAMs) have been proposed to preserve data, while providing fast power- On/Off speeds. Nonvolatile operation is usually accomplished by the use of a resistive RAM circuit (hence referred to as RRAM); the utilization of a RRAM with an SRAMs not only enables chips to achieve low energy consumption for nonvolatile operation, but it also permits to restore data when a restore on power-up is performed (this operation is also commonly referred to as “Instant-on”). This paper presents a novel NVSRAM circuit for “Instant-on” operation and evaluates its performance at nanometric feature sizes. The proposed memory cell consists of a SRAM core (in this case, a 6T cell) and an oxide resistive RRAM circuit (1T1R), thus making a 7T1R scheme. The proposed cell offers better nonvolatile performance (in terms of operations such as “Store,” “Power-down,” and “Restore”) when compared with existing nonvolatile cells. The scenario of multiple-context configuration is also analyzed. Figures of merit such as energy, operational delay, and area are also substantially improved, making the proposed design a better scheme for “Instant-on” operation. View full abstract»

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  • 50. Design of a Beam Reconfigurable THz Antenna With Graphene-Based Switchable High-Impedance Surface

    Publication Year: 2012 , Page(s): 836 - 842
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (889 KB) |  | HTML iconHTML  

    In this paper, a new beam reconfigurable antenna is proposed for THz application, which is based on a switchable high-impedance surface (HIS) using a single-layer graphene. The effects of impurity density and gate voltage on the conductivity of graphene are utilized, and the switchable reflection characteristic of the graphene-based HIS is observed. Then the THz antenna is designed over this switchable HIS. By applying different voltages for different rows of HIS units, the antenna beam can be reconfigurable. The performance of the antenna is analyzed with its reflection coefficient, radiation pattern, and input impedance. The radiation beam of the antenna can vary in a range of ±30° as demonstrated by the simulated results. View full abstract»

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Aims & Scope

The IEEE Transactions on Nanotechnology is devoted to the publication of manuscripts of archival value in the general area of nanotechnology, which is rapidly emerging as one of the fastest growing and most promising new technological developments for the next generation and beyond.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Fabrizio Lombardi
Dept. of ECE
Northeastern Univ.