IEEE Journal of Solid-State Circuits

Classical designs of optical transimpedance amplifiers for p-i-n photodiode receiver circuits generally employ common-emitter or common-source input stages. In this paper we explore the design of a new class of low noise “current-mode” optical transimpedance preamplifier based upon common-base input stages. Simulated and measured results of a 10 GHz GaAs HBT and 3.5 GHz BiCMOS common-b... View full abstract»

A class A/B BiCMOS power op-amp designed to drive the L/R load of a disk drive head actuator is presented. The amplifier uses totem pole NMOS outputs instead of bipolar devices to avoid the high collector resistance in the simplified process used. A unique floating buffer technique regulates the quiescent totem pole current of the output devices and provides control for deep triode NMOS operation.... View full abstract»

This paper presents a high-speed low-power cross-coupled active-pull-down ECL (CC-APD-ECL) circuit. The circuit features a cross-coupled active-pull-down scheme to improve the power-delay of the emitter-follower stage. The cross-coupled biasing scheme preserves the emitter-dotting capability and requires no extra biasing circuit branch and power for the active-pull-down transistor. Based on a 0.8 ... View full abstract»

A communication architecture tailored for analog VLSI perceptive systems is proposed. Information is generated on a transmitter array of cells each driving a pulse generator. The resulting pulse-frequency modulated signals are transmitted through the nonarbitered, asynchronous access of pulses to a common bus. Pulses are decoded and accumulated in a receiver chip and the mapping of the activity di... View full abstract»

Novel low-voltage swing CMOS and BiCMOS driver/receiver circuits for low-power VLSI applications are proposed. Interconnect wire drivers with low output signal swing are employed. Special receivers provide single and double level conversion while minimizing the total driver/receiver transmission delay. These level converters have no DC power dissipation. At 3.3 V power supply voltage, the proposed... View full abstract»

This paper describes an electrically programmable switched-capacitor (SC) biquad using quasi-passive algorithmic digital-to-analog converters (DAC's). Since only two equal-valued capacitors are needed for programming each capacitance value, the proposed technique offers compact, cost-effective programmability when compared to traditional programming techniques employing binary-weighted capacitor-a... View full abstract»

This paper reports on a single-chip read/write channel for disk drive. The integrated circuit implements a peak detector architecture fully compatible with zoned-bit recording applications. The chip contains all the functions needed to implement a high performance read channel, i.e., pulse detector, programmable active filter, servo demodulator, frequency synthesizer, data separator and RLL(1,7) E... View full abstract»

Novel full-swing BiCMOS/BiNMOS logic circuits using bootstrapping in the pull-up section for low supply voltage down to 1 V are reported. These circuit configurations use noncomplementary BiCMOS technology. Simulations have shown that they outperform other BiCMOS circuits at low supply voltage using 0.35 μm BiCMOS process. The delay and power dissipation of several NAND configurations have been... View full abstract»

A new active-pull-down nonthreshold logic (APD-NTL) BiCMOS circuit is presented and its performance has been evaluated and compared to that of standard NTL gate. The circuit utilizes an NMOS active-pull-down emitter-follower stage. A first-order analysis has been conducted to demonstrate the NMOS-APD concept. Simulation results based on 0.6 μm BiCMOS technology indicate that at a power consumpt... View full abstract»

A compact low noise operational amplifier using lateral p-n-p bipolar transistors in the input stage has been fabricated in a standard 1.2 μm digital n-well CMOS process. Like their n-p-n counterparts in p-well processes, these lateral p-n-p transistors exhibit low 1/f noise and good lateral β. The fabricated op amp has an area of only 0.211 mm2 with En=3.2 nV/√... View full abstract»

This study presents some of the first experimental data on the impact of NMOSFET hot-carrier-induced degradation on CMOS analog subcircuit performance. Because of circuit design requirements, most NMOSFET's used for analog applications are biased in the saturation region with a low gate-to-source voltage. Under such operating conditions, in addition to interface states, significant numbers of hole... View full abstract»

This paper proposes a BiCMOS wired-OR logic for high-speed multiple input logic gates. The logic utilizes the bipolar wired-OR to circumvent the use of a series connection of MOS transistors. The BiCMOS wired-OR logic was found to be the fastest compared with such conventional gates as CMOS NOR, BiCMOS multiemitter logic and CMOS wired-NOR logic, when the number of inputs was more than four and th... View full abstract»

In this paper we describe a TSPC (True Single-Phase-Clock) barrel shifter for high-speed, real time applications. The circuit consists of a shift and rotate array and a control unit, both having a pipeline structure, which allows on-line programming. Using 1.5 μm CMOS technology, a full custom prototype for 16-b data shift and rotate array has been implemented, with a simplified control unit, a... View full abstract»

This paper presents the results of measurements performed on test structures implementing circuits for controlled erase of floating gate MOSFET's. The obtained results show that, with cells fabricated using standard technology, the obtained performance is sufficiently good to allow use in analog applications. The circuit has been demonstrated to be robust with respect to variations of the programm... View full abstract»

We have fabricated a high yield integrated memory array processor (IMAP) LSI, which features a high memory bandwidth (1.28-GB/s) and low power consumption (4-W max.) and which contains a 2-Mb SRAM with 1.28-I/O's and 64 processor elements (PE's) in one chip. A high-bandwidth and low-power memory circuit design is the key technology to realize the IMAP-LSI. We adopted following new designs for memo... View full abstract»