IEEE Transactions on Computers
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Volume 43 Issue 3 • March 1994
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Previous Titles
- ( 1963 - 1967 ) IEEE Transactions on Electronic Computers
- ( 1955 - 1962 ) IRE Transactions on Electronic Computers
- ( 1952 - 1954 ) Transactions of the I.R.E. Professional Group on Electronic Computers
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Comments on "Evaluation of A+B = K conditions without carry propagation
Publication Year: 1994
Cited by: Papers (3) | Patents (7)A special carry-free circuit for the evaluation of conditions of the type A+B=K is proposed by Cortadella and Llaberia (1992), and its usefulness for reducing the negative effects of conditional branches in pipelined architectures is noted. It is shown that the same advantages are offered by another equally simple circuit based on carry-save redundant numbers and (3, 2)-counters. This alternative ... View full abstract»
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Comments on "Decomposition of complex multipliers using polynomial encoding"
Publication Year: 1994, Page(s):381 - 383
Cited by: Papers (1)Presents a better way of decomposition of complex multipliers using polynomial encoding than the method presented in the paper, "Decomposition of Complex Multipliers Using Polynomial Encoding." ibid., vol. 41, no. 10, p1331-3, 1992. The decomposition described in this paper makes use of smaller multipliers which results in smaller ROMs if ROM table look-ups are used to implement multipliers.... View full abstract»
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Comments on "A characterization of binary decision diagrams"
Publication Year: 1994, Page(s):383 - 384
Cited by: Papers (4)Chakravarty presents a characterization of BDD's in terms of the complexity of some computational problems, ibid., vol. 42, p. 129-137, Feb. 1993. In these comments, some incorrectly stated restrictions on the "number of repeated variables" are corrected and results on the translation problem (to include EXOR and NEXOR gates) are generalized.<
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Error correcting codes over Z2(m) for algorithm-based fault tolerance
Publication Year: 1994, Page(s):370 - 374
Cited by: Papers (7) | Patents (25)Algorithm-based fault tolerance is a scheme of low-cost error protection in real-time digital signal processing environments and other computation-intensive tasks. In this paper, a new method for encoding data is proposed and, furthermore, two kinds of error-correcting codes over Z2(m), which can be used with fixed-point arithmetic in practical algorithm-based fault tolerant systems, ar... View full abstract»
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Almost sure diagnosis of almost every good element [logic testing]
Publication Year: 1994, Page(s):295 - 305
Cited by: Papers (25)We demonstrate a structure for mutual test among N processing elements. We indicate how this structure might be used to identify the good dice on a semiconductor wafer at a cost below that of current techniques. Under either a digraph or a comparison model, our proposed test structure has the following properties: 1) It is nearly regular. 2) It can be laid out in area O(⊖(n). 3) In time &om... View full abstract»
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Some additions to “solution of switching equations based on a tabular algebra”
Publication Year: 1994, Page(s):365 - 367
Cited by: Papers (5)A method was presented by A.L. Ruiz, P.P. Trabado, and J.O. Lopera (see ibid., vol.42, no. 5, p. 591-6, 1993) for efficiently generating the solutions of Boolean equations by using tables (i.e., rectangular arrays or matrices) of 0's, 1's, and dashes to represent Boolean expressions. Some enhancements of their method are presented. First, it is shown how the uniting theorem can be applied directly... View full abstract»
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Fast hardware-based algorithms for elementary function computations using rectangular multipliers
Publication Year: 1994, Page(s):278 - 294
Cited by: Papers (50)As the name suggests, elementary functions play a vital role in scientific computations. Yet due to their inherent nature, they are a considerable computing task by themselves. Not surprisingly, since the dawn of computing, the goal of speeding up elementary function computation has been pursued. This paper describes new hardware based algorithms for the computation of the common elementary functi... View full abstract»
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Design of efficient balanced codes
Publication Year: 1994, Page(s):362 - 365
Cited by: Papers (34) | Patents (1)All words in a balanced code have equal number of ones and zeros. Denote by DC(n,k) a balanced (or dc-free) code of length n, and 2k code words. We design an efficient DC(k+r, k) code with k=2r+1-0.8√(r-2). These codes are optimal up to the construction method, introduced by D.E. Knuth (1986) View full abstract»
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Over-redundant digit sets and the design of digit-by-digit division units
Publication Year: 1994, Page(s):269 - 277
Cited by: Papers (17) | Patents (3)Over-redundant digit sets are defined as those ranging from -s to +s, with s⩾B, B being the radix. This paper presents new techniques for the direct computation of division, that use an over-redundant digit set for representing the quotient, instead of simply redundant ones used previously. In particular, general criteria for synthesizing the digit selection rules and remainder updating are gi... View full abstract»
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A parallel algorithm for reconfiguring a multibutterfly network with faulty switches
Publication Year: 1994, Page(s):321 - 326
Cited by: Papers (3)This paper describes a deterministic algorithm for reconfiguring a multibutterfly network with faulty switches. Unlike previous reconfiguration algorithms, the algorithm is performed entirely by the network, without the aid of any off-line computation, even though many of the switches may be faulty. The algorithm reconfigures an N-input multibutterfly network in O(logN) time. After reconfiguration... View full abstract»
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Computing display conflicts in string visualization
Publication Year: 1994, Page(s):350 - 361
Cited by: Papers (1)Strings are used to represent a variety of objects such as DNA sequences, text, and numerical sequences. A model for a system for the visualization and analysis of strings was proposed by D. Mehta and S. Sahni (1992). The problem of display conflicts that arise in this model was identified and methods to overcome it were suggested. These methods require the computation of display conflicts. We pre... View full abstract»
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High-performance 3-1 interlock collapsing ALU's
Publication Year: 1994, Page(s):257 - 268
Cited by: Papers (14) | Patents (5)A high-performance 3-1 interlock collapsing ALU, i.e., an ALU that allows the execution of most execution interlocks in a single machine cycle, is presented. We focus on reducing the Boolean equations describing the device and the incorporation of new mechanisms in the interlock collapsing ALU design. In particular, we focus on the reduction of the critical path, regarding delay, for the interlock... View full abstract»
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Conflict resolution and fault-free path selection in multicast-connected cube-based networks
Publication Year: 1994, Page(s):374 - 380
Cited by: Papers (2)Presents an algorithm that solves the conflict resolution problem in fault-tolerant multicast-connected MINs. Without loss of generality, the authors apply the algorithm to reconfigure a four-path cube-based network. An intensive simulation study is conducted to reveal the performance improvement gained by the conflict resolution and fault-free path selection algorithm on the network under study. ... View full abstract»
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Testing finite-state machines: state identification and verification
Publication Year: 1994, Page(s):306 - 320
Cited by: Papers (113)We study the complexity of two fundamental problems in the testing of finite-state machines. 1) Distinguishing sequences (state identification). We show that it is PSPACE-complete to determine whether a finite-state machine has a preset distinguishing sequence. There are machines that have distinguishing sequences, but only of exponential length. We give a polynomial time algorithm that determines... View full abstract»
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Guaranteeing synchronous message deadlines with the timed token medium access control protocol
Publication Year: 1994, Page(s):327 - 339
Cited by: Papers (92) | Patents (1)We study the problem of guaranteeing synchronous message deadlines in token ring networks where the timed token medium access control protocol is employed. Synchronous bandwidth, defined as the maximum time for which a node can transmit its synchronous messages every time it receives the token, is a key parameter in the control of synchronous message transmission. To ensure the transmission of syn... View full abstract»
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Perfect shifters [multiprocessor interconnection networks]
Publication Year: 1994, Page(s):340 - 349
Cited by: Papers (1)Pin-efficient single-instruction multiple-data networks, with p≈√(2m) pins per cell that can-in one clock tick-shift data by any amount k in an interval [-m,m] are considered. Perfect barrel shifters, which perform the group of permutations c→c+k(mod n), 0⩽k⩽n-1, using p=q+1 pins per cell, are known to exist for all n=q2+q+1, where q is any prime power. In sharp co... View full abstract»
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Safe system level diagnosis
Publication Year: 1994, Page(s):367 - 370
Cited by: Papers (13)A new approach called safe system level diagnosis is proposed. With this approach, in the event of a small number of faults, all the faulty nodes can be identified; also, in the event of a large number of faults, the fault condition can be detected. Systems which achieve a specified level of safe diagnosis are characterized and a diagnosis algorithm for such systems is presented. Also, an applicat... View full abstract»
Aims & Scope
The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.
Meet Our Editors
Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24
10129 Torino - Italy
e-mail: pmo@computer.org