# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 25 of 37

Publication Year: 2012
| PDF (145 KB)
• ### IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

Publication Year: 2012, Page(s): C2
| PDF (135 KB)
• ### Modeling and Design of Spintronic Integrated Circuits

Publication Year: 2012, Page(s):2801 - 2814
Cited by:  Papers (37)
| | PDF (2473 KB) | HTML

We present a theoretical and a numerical formalism for analysis and design of spintronic integrated circuits (SPINICs). The formalism encompasses a generalized circuit theory for spintronic integrated circuits based on nanomagnetic dynamics and spin transport. We propose an extension to the modified nodal analysis technique for the analysis of spin circuits based on the recently developed spin con... View full abstract»

• ### Random Pulsewidth Matching Frequency Synthesizer With Sub-Sampling Charge Pump

Publication Year: 2012, Page(s):2815 - 2824
Cited by:  Papers (5)
| | PDF (2382 KB) | HTML

This paper presents a fast locking phase-locked loop (FLPLL) system with reference-spur reduction techniques exploiting random pulsewidth matching and a sub-sampling charge pump. Through the randomization and average of the pulsewidth and the reduction of current mismatch, the frequency synthesizer can reduce the ripples on the control voltage of the voltage-controlled oscillator in order to reduc... View full abstract»

• ### Application of Kalman Gain for Minimum Mean-Squared Phase-Error Bound in Bang-Bang CDRs

Publication Year: 2012, Page(s):2825 - 2834
Cited by:  Papers (8)  |  Patents (1)
| | PDF (3126 KB) | HTML

This paper presents the minimum bound of the mean-squared phase-error of a bang-bang (BB) clock-and-data recovery (CDR) circuit under the condition of random phase tracking. An analogy between the Kalman filter and a linearized BB CDR is utilized for the derivation. The effects of demultiplexing, loop latency, and granular jitter are considered in the analysis to reflect reality. The validity of t... View full abstract»

• ### Pulsed Digital Oscillators for Electrostatic MEMS

Publication Year: 2012, Page(s):2835 - 2845
Cited by:  Papers (3)
| | PDF (3008 KB) | HTML

This paper introduces a new actuation scheme for implementing Pulsed Digital Oscillators (PDOs) for electrostatic MEMS resonators. In this scheme, the capacitance of the device is biased with a voltage and it is periodically sampled. Short pulses of zero voltage are applied depending on the decisions taken by the oscillator loop. The paper discusses in detail the implementation of such electrostat... View full abstract»

• ### A Flexible 500 MHz to 3.6 GHz Wireless Receiver with Configurable DT FIR and IIR Filter Embedded in a 7b 21 MS/s SAR ADC

Publication Year: 2012, Page(s):2846 - 2857
Cited by:  Papers (8)
| | PDF (2244 KB) | HTML

A flexible, software-configurable wireless receiver is implemented in 65 nm CMOS. The receive chain consists of wideband LNA and mixer, baseband amplifiers, and a 7-bit 21 MS/s filtering SAR ADC. This filtering ADC embeds a highly-integrated and configurable DT FIR/IIR filter to replace dedicated filtering stages. The tap length and coefficients of the embedded FIR filter are configurable from 16 ... View full abstract»

• ### A 5.4/2.7/1.62-Gb/s Receiver for DisplayPort Version 1.2 With Multi-Rate Operation Scheme

Publication Year: 2012, Page(s):2858 - 2866
Cited by:  Papers (9)
| | PDF (3389 KB) | HTML

A 5.4/2.7/1.62-Gb/s multi-rate receiver is designed for Display Port version 1.2. A dual-mode binary phase detector supports half-rate and quarter-rate phase detections to enable the multi-rate operation of the receiver without a wide-tuning VCO. In addition, a low voltage-drop active inductor with a voltage booster is implemented in the dual-mode binary phase detector to extend the bandwidth and ... View full abstract»

• ### Switched-Capacitor Level-Shifting Technique With Sampling Noise Reduction for Rail-to-Rail Input Range Instrumentation Amplifiers

Publication Year: 2012, Page(s):2867 - 2880
Cited by:  Papers (2)
| | PDF (2707 KB) | HTML

This paper proposes a switched-capacitor Adaptive Level-Shifting (ALS) technique for Instrumentation Amplifiers (IA). When used at the front end of an IA the ALS circuit enables true rail-to-rail input common-mode (CM) range and reduces CMRR requirements for the following IA. In the proposed implementation, two ALS circuits are combined with the two input stages of an Indirect Current-Feedback (IC... View full abstract»

• ### On the Noise Optimum of FET Broadband Transimpedance Amplifiers

Publication Year: 2012, Page(s):2881 - 2889
Cited by:  Papers (10)
| | PDF (1621 KB) | HTML

The optimum sizing of the front-end FET in transimpedance amplifiers (TIA) is revisited. Analytical solutions based on a second-order shunt-feedback TIA model that includes the feedback-resistor noise are derived. It is shown that the optimum FET size can be smaller or larger than suggested by the well-known capacitive matching rule, depending on whether the noise optimization is carried out under... View full abstract»

• ### Exploration of Second-Order Effects in High-Performance Continuous-Time $SigmaDelta$ Modulators Using Discrete-Time Models

Publication Year: 2012, Page(s):2890 - 2900
Cited by:  Papers (1)
| | PDF (2014 KB) | HTML

This paper proposes a method for the discretization of continuous-time sigma-delta modulators (CT-ΣΔMs) with various circuit nonidealities. Recurrence equations for the sampled states of a CT-ΣΔM are derived to find the equivalent discrete-time (DT) transfer functions of CT loop filters along with several second-order effects, such as finite DC gain, finite unity-gain b... View full abstract»

• ### Low-Voltage Low-Power 1.6 GHz Quadrature Signal Generation Through Stacking a Transformer-Based VCO and a Divide-by-Two

Publication Year: 2012, Page(s):2901 - 2910
Cited by:  Papers (4)
| | PDF (1984 KB) | HTML

This paper presents a differential VCO stacked with a divide-by-two to generate quadrature signals for low-power wireless applications. The transformer-based VCO core adopts the Armstrong VCO configuration to mitigate the small voltage headroom and the noise coupling. The operating conditions of the proposed quadrature local oscillator (LO) circuitry are derived based upon a linearized small-signa... View full abstract»

• ### A VLSI Efficient Programmable Power-of-Two Scaler for ${2^{n}-1,2^{n},2^{n}+1}$ RNS

Publication Year: 2012, Page(s):2911 - 2919
Cited by:  Papers (6)
| | PDF (1818 KB) | HTML

Variable scaling by power-of-two factor is the backbone operation of floating point arithmetic and is also commonly used in fixed-point digital signal processing (DSP) system for overflow prevention. While this operation can be readily performed in binary number system, it is extremely difficult to implement in residue number system (RNS). In the absence of an efficient solution to scale an intege... View full abstract»

• ### FPGA Implementations of Piecewise Affine Functions Based on Multi-Resolution Hyperrectangular Partitions

Publication Year: 2012, Page(s):2920 - 2933
Cited by:  Papers (12)
| | PDF (2224 KB) | HTML

In this paper we propose a digital architecture suited for fast, low-power and small-size electronic implementation of PieceWise Affine (PWA) functions defined over n-dimensional domains partitioned into multi-resolution hyperrectangles. The point location problem, which requires most of the computational effort, is solved through an orthogonal search tree, which is easily and efficiently implemen... View full abstract»

• ### Deeply Pipelined Digit-Serial LDPC Decoding

Publication Year: 2012, Page(s):2934 - 2944
Cited by:  Papers (8)
| | PDF (1001 KB) | HTML

Highly parallel VLSI implementations of low-density parity-check (LDPC) decoders have a large number of interconnections, which can result in designs with low logic density. Bit-serial architectures have been developed that reduce the number of wires needed, however, they do not fully realize the potential for deeply pipelined serial data processing. Digit- online arithmetic allows operations to b... View full abstract»

• ### An Area and Energy Efficient Inner-Product Processor for Serial-Link Bus Architecture

Publication Year: 2012, Page(s):2945 - 2955
| | PDF (3167 KB) | HTML

A unique word-serial inner-product processor architecture is proposed to capitalize on the high-speed serial-link bus. To eliminate the input buffers and deserializers, partial products are generated immediately from the serial input data and accumulated by an array of small binary counters operating in parallel to form a reduced partial product matrix directly. The height of the resultant partial... View full abstract»

• ### Chebyshev Stopbands for CIC Decimation Filters and CIC-Implemented Array Tapers in 1D and 2D

Publication Year: 2012, Page(s):2956 - 2968
Cited by:  Papers (37)
| | PDF (3442 KB) | HTML

The stopbands of a cascaded integrator-comb (CIC) decimation filter are ordinarily very narrow, as each results from a single multiple zero. Here response sharpening with a Chebyshev polynomial, using a previously reported CIC variant, separates each such multiple zero into an equiripple stopband. By trading unneeded depth at stopband center for improved depth at the stopband edge, the latter dept... View full abstract»

• ### Hybrid Partitioned SRAM-Based Ternary Content Addressable Memory

Publication Year: 2012, Page(s):2969 - 2979
Cited by:  Papers (11)  |  Patents (2)
| | PDF (1291 KB) | HTML

Although content addressable memory (CAM) provides fast search operation; however, CAM has disadvantages like low bit density and high cost per bit. This paper presents a novel memory architecture called hybrid partitioned static random access memory-based ternary content addressable memory (HP SRAM-based TCAM), which emulates TCAM functionality with conventional SRAM, thereby eliminating the inhe... View full abstract»

• ### The IEEE Standard 1459, the CPC Power Theory, and Geometric Algebra in Circuits With Nonsinusoidal Sources and Linear Loads

Publication Year: 2012, Page(s):2980 - 2990
Cited by:  Papers (7)
| | PDF (3161 KB) | HTML

An alternative circuit analysis technique and its associated power theory is compared to the IEEE Standard 1459 and the current's physical components power theory. The comparison shows that elimination of the fundamental reactive power quantity Q1 as defined by the Standard does not ensure supply current reduction. In contrast elimination of the reactive current as defined by the... View full abstract»

• ### Biologically Inspired Spiking Neurons: Piecewise Linear Models and Digital Implementation

Publication Year: 2012, Page(s):2991 - 3004
Cited by:  Papers (33)  |  Patents (7)
| | PDF (3269 KB) | HTML

There has been a strong push recently to examine biological scale simulations of neuromorphic algorithms to achieve stronger inference capabilities. This paper presents a set of piecewise linear spiking neuron models, which can reproduce different behaviors, similar to the biological neuron, both for a single neuron as well as a network of neurons. The proposed models are investigated, in terms of... View full abstract»

• ### A New Method for Determining the Generalised Frequency Response Functions of Nonlinear Systems

Publication Year: 2012, Page(s):3005 - 3014
Cited by:  Papers (4)
| | PDF (2661 KB) | HTML

The Generalised Frequency Response Functions (GFRFs) are important tools for the analysis of nonlinear systems based on the Volterra series approach. A new algorithm for extracting the GFRFs from a nonlinear difference equation model is proposed in this paper. The advantage of the new method over available techniques is that the new method determines the GFRFs using a numerical procedure based on ... View full abstract»

• ### Consensus of Nonlinear Agents in Directed Network With Switching Topology and Communication Delay

Publication Year: 2012, Page(s):3015 - 3023
Cited by:  Papers (12)
| | PDF (3104 KB) | HTML

This work studies the consensus problem of a group of agents with nonlinear dynamics while directional communications between agents with delay are assumed. To reflect the practical situation of having reconnections or disconnections between agents, the communication topology is considered to be switched within a finite set of digraphs. The consensus criterion with exponential convergence is estab... View full abstract»

• ### Evaluation of Harmonic Coupling Weights in Nonlinear Periodicity Preservation Systems

Publication Year: 2012, Page(s):3024 - 3033
Cited by:  Papers (3)
| | PDF (2302 KB) | HTML

When stimulated by a periodic stimulus, every component of a possibly nonlinear periodicity preservation system oscillates periodically with the same period as the stimulus. Changes in the harmonic structure of the the stimulus couples each input harmonic to, in general, every response harmonic. Knowledge of harmonic coupling weights (HCWs) allows model free characterization of effects of all smal... View full abstract»

• ### Small Perturbation Harmonic Coupling in Nonlinear Periodicity Preservation Circuits

Publication Year: 2012, Page(s):3034 - 3045
Cited by:  Papers (4)  |  Patents (2)
| | PDF (2586 KB) | HTML

Nonlinear systems and circuits, while required for many applications, presently require a design procedure that is often complex. In many cases, the design process is either based upon measurements or complex nonlinear models. This paper presents periodicity preservation (PP) and time invariant PP (TIPP) system theory as a simple way to characterize behavior for a significant class of nonlinear sy... View full abstract»

• ### Dynamical Systems Guided Design and Analysis of Silicon Oscillators for Central Pattern Generators

Publication Year: 2012, Page(s):3046 - 3059
Cited by:  Papers (2)
| | PDF (2605 KB) | HTML

In this paper, a dynamical systems (DS) approach is proposed for the analysis and design of bio-inspired silicon central pattern generator (CPG) systems. Based on this approach, a new leaky-integrate-and-leaky-discharge oscillator circuit is proposed that has dynamical properties closer to biological half-center oscillators while being power and area efficient. The membrane potential charges and d... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK