# IEEE Transactions on Very Large Scale Integration (VLSI) Systems

## Filter Results

Displaying Results 1 - 25 of 25

Publication Year: 2012, Page(s):C1 - C4
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• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

Publication Year: 2012, Page(s): C2
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• ### Secure Public Verification of IP Marks in FPGA Design Through a Zero-Knowledge Protocol

Publication Year: 2012, Page(s):1749 - 1757
Cited by:  Papers (9)
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In nanometer technology regime, design components mandate their reuse to meet the complex design challenges and hence comprise Intellectual Property (IP). Unauthorized reuse raises major security issues. IP mark(s) is embedded into a design for establishing the veracity of a legal IP owner/buyer. However, methods for trustworthy public verification of IP marks are not secure. For field-programmabl... View full abstract»

• ### A Multi-Agent Framework for Thermal Aware Task Migration in Many-Core Systems

Publication Year: 2012, Page(s):1758 - 1771
Cited by:  Papers (14)
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In deep submicrometer era, thermal hot spots, and large temperature gradients significantly impact system reliability, performance, cost, and leakage power. As the system complexity increases, it is more and more difficult to perform thermal management in a centralized manner because of state explosion and the overhead of monitoring the entire chip. In this paper, we propose a framework for distri... View full abstract»

• ### The Optimal Fan-Out of Clock Network for Power Minimization by Adaptive Gating

Publication Year: 2012, Page(s):1772 - 1780
Cited by:  Papers (17)  |  Patents (1)
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Gating of the clock signal in VLSI chips is nowadays a mainstream design methodology for reducing switching power consumption. In this paper we develop a probabilistic model of the clock gating network that allows us to quantify the expected power savings and the implied overhead. Expressions for the power savings in a gated clock tree are presented and the optimal gater fan-out is derived, based ... View full abstract»

• ### Fast Transient (FT) Technique With Adaptive Phase Margin (APM) for Current Mode DC-DC Buck Converters

Publication Year: 2012, Page(s):1781 - 1793
Cited by:  Papers (17)  |  Patents (1)
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This paper proposes a fast transient (FT) control with the adaptive phase margin (APM) to achieve good transient response in current-mode DC-DC buck converters at different load conditions. The overshoot/undershoot voltage and the transient recovery time are effectively reduced. The APM control can always maintain the system phase margin at an adequate value under different load conditions. That i... View full abstract»

• ### Power Yield Analysis Under Process and Temperature Variations

Publication Year: 2012, Page(s):1794 - 1803
Cited by:  Papers (6)
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In this paper, a method is proposed to accurately estimate the power yield, considering process-induced temperature and supply voltage variations. Process variations impose statistical behavior on the temperature and leakage current. This, in turn, impacts the IR drops due to the variations in the current, drawn off the power grid. By considering the process-induced statistical profile of the temp... View full abstract»

• ### Design Specification for BER Analysis Methods Using Built-In Jitter Measurements

Publication Year: 2012, Page(s):1804 - 1817
Cited by:  Papers (1)
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Timing jitter is a major limiting factor for data throughput in serial high-speed interfaces, which forces an accurate analysis of the impact on system performance. Histogram-based methods have been developed for this purpose, and can directly relate collected jitter distributions with the bit-error rate (BER). However, real measurements suffer from limitations introduced by the hardware, such as ... View full abstract»

• ### An All-Digital Clock Synchronization Buffer With One Cycle Dynamic Synchronizing

Publication Year: 2012, Page(s):1818 - 1827
Cited by:  Papers (4)
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This paper proposes an all-digital clock synchronization buffer (CSB) with one-cycle dynamic synchronization. The CSB synchronizes the input and output clocks in three clock cycles but maintains one cycle at fastest operating frequency. The CSB achieves one-cycle dynamic locking and synchronizes the dynamic frequencies with a modified structure. The CSB compensates for dynamic phase error with a m... View full abstract»

• ### Applying Effective Dynamic Frequency Scaling Method in Contactless Smart Card

Publication Year: 2012, Page(s):1828 - 1834
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A creative dynamic frequency scaling method in contactless smart card is presented for the first time. A low power magnetic field detection circuit, a simple load detection circuit, the quick load comparator and the simple clock switch scheme in the method are also presented. The test result shows that the longest communication distance is improved from 6 to 8 cm compared to the same contactless s... View full abstract»

• ### A New Self-Healing Methodology for RF Amplifier Circuits Based on Oscillation Principles

Publication Year: 2012, Page(s):1835 - 1848
Cited by:  Papers (21)
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This paper proposes a new self-healing methodology for embedded RF amplifiers in RF sub-systems. The proposed methodology is based on oscillation principles in which the device-under-test (DUT) generates its test signature with the help of additional circuitry. In the proposed methodology, the self-generated test signature from the RF amplifier is analyzed by using on-chip resources for testing an... View full abstract»

• ### An On-Demand Queue Management Architecture for a Programmable Traffic Manager

Publication Year: 2012, Page(s):1849 - 1862
Cited by:  Papers (4)
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A queue manager (QM) is a core traffic management (TM) function used to provide per-flow queuing in access and metro networks; however current designs have limited scalability. An on-demand QM (OD-QM) which is part of a new modular field-programmable gate-array (FPGA)-based TM is presented that dynamically maps active flows to the available physical resources; its scalability is derived from explo... View full abstract»

• ### Run-Time Reconfiguration of Expandable Cache for Embedded Systems

Publication Year: 2012, Page(s):1863 - 1875
Cited by:  Papers (1)
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Expandable cache proposed by Bournoutian and Orailoglu is very efficient in reducing miss rate and energy consumption with small area overhead. However, the original expandable cache with only one expansion scheme may lead to thrashing problems. In this work, based on the structure of expandable cache, we will introduce a new cache design which has many expansion schemes to fit different run-time ... View full abstract»

• ### On-Chip Measurement System for Within-Die Delay Variation of Individual Standard Cells in 65-nm CMOS

Publication Year: 2012, Page(s):1876 - 1880
Cited by:  Papers (2)
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New measurement system for characterizing within-die delay variations of individual standard cells is presented. The proposed measurement system are able to characterize rising and falling delay variations separately by directly measuring the input and output waveforms of individual gate using an on-chip sampling oscilloscope in 65 nm 1.2V CMOS process. Seven types of standard cells are measured w... View full abstract»

• ### A High Performance Switched Capacitor-Based DC-DC Buck Converter Suitable for Embedded Power Management Applications

Publication Year: 2012, Page(s):1880 - 1885
Cited by:  Papers (7)
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Here, we propose high performance buck converter architecture suitable for embedded applications. The proposed converter has high power efficiency, high power density, good driving capability, low output ripple, and good line and load regulation. The step down converter is constructed using a simple building block called cross coupled converter. As this block use low swing internal signals to cont... View full abstract»

• ### Maximizing Frequency and Yield of Power-Constrained Designs Using Programmable Power-Gating

Publication Year: 2012, Page(s):1885 - 1890
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A large spread of leakage power due to process variations impacts the total power consumption of integrated circuits (ICs) substantially. This in turn may reduce frequency and/or yield of power-constrained designs. Facing such challenges, we propose two methods using power-gating (PG) devices whose effective width can be adjusted during a post-silicon tuning process. In the first method, we consid... View full abstract»

• ### Functional Test-Sequence Grading at Register-Transfer Level

Publication Year: 2012, Page(s):1890 - 1894
Cited by:  Papers (2)
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We propose output deviations as a surrogate metric to grade functional test sequences at the register-transfer level without explicit fault simulation. Experimental results for the open-source Biquad filter core and the Scheduler module of the Illinois Verilog Model show that the deviations metric is computationally efficient and it correlates well with gate-level coverage for stuck-at, transition... View full abstract»

• ### Generation of Mixed Test Sets for Transition Faults

Publication Year: 2012, Page(s):1895 - 1899
Cited by:  Papers (9)
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Test sets that contain both broadside and skewed-load tests are important for achieving the highest possible delay fault coverage for standard-scan circuits. Both types of tests can be represented as 〈s1, v1, s2, v2 〉, where s1 and s2 are states, and v1 and v2 are primary input vectors. To facilit... View full abstract»

• ### Fibonacci Codes for Crosstalk Avoidance

Publication Year: 2012, Page(s):1899 - 1903
Cited by:  Papers (7)
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Propagation delay across long on-chip buses is significant when adjacent wires are transitioning in opposite direction (i.e., crosstalk transitions) as compared to transitioning in the same direction. By exploiting Fibonacci number system, we propose a family of Fibonacci coding techniques for crosstalk avoidance, relate them to some of the existing crosstalk avoidance techniques, and show how the... View full abstract»

• ### New Bit Parallel Multiplier With Low Space Complexity for All Irreducible Trinomials Over $GF(2^{n})$

Publication Year: 2012, Page(s):1903 - 1908
Cited by:  Papers (6)
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Koç and Sunar proposed an architecture of the Mastrovito multiplier for the irreducible trinomial f(x)=xn+xk+1, where k ≠ n/2 to reduce the time complexity. Also, many multipliers based on the Karatsuba-Ofman algorithm (KOA) was proposed that sacrificed time efficiency for low space complexity. In this paper, a new multiplication formula which is a va... View full abstract»

• ### A Low-Power Ternary Content Addressable Memory With Pai-Sigma Matchlines

Publication Year: 2012, Page(s):1909 - 1913
Cited by:  Papers (15)
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This paper proposes a Pai-Sigma matchline scheme to reduce the compare (search) power of a ternary content addressable memory (TCAM). The proposed matchline does not incur the issues of charge sharing and short circuit current, which typically exist in the hybrid nand-nor matchline. Moreover, the switching activity of the search lines of a TCAM with the proposed matchlines is low. A 32×64-b... View full abstract»

• ### Formal Performance Analysis for Faulty MIMO Hardware

Publication Year: 2012, Page(s):1914 - 1918
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Sources of noise such as quantization, introduce randomness into register transfer level (RTL) designs of complex systems. In previous work, we introduced a formal approach to compute the performance metrics for these designs with high confidence. We defined the performance metrics as properties in a probabilistic temporal logic. We then used probabilistic model checking to verify these properties... View full abstract»

• ### Low-Complexity Tone Reservation for PAPR Reduction in OFDM Communication Systems

Publication Year: 2012, Page(s):1919 - 1923
Cited by:  Papers (7)
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Orthogonal frequency division multiplexing communication systems have a drawback that some signal values can be much higher than the average signal value. Transmitting such a high signal increases symbol error rate (SER) significantly, as the signal is usually distorted by the nonlinearity of power amplifiers. Most of previous methods presented to reduce the peak-to-average-power ratio are based o... View full abstract»

• ### Low-Error and Hardware-Efficient Fixed-Width Multiplier by Using the Dual-Group Minor Input Correction Vector to Lower Input Correction Vector Compensation Error

Publication Year: 2012, Page(s):1923 - 1928
Cited by:  Papers (7)
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In this paper, we propose a new error compensation circuit by using the dual group minor input correction vector to lower input correction vector compensation error. By utilizing the symmetric property of the minor input correction vector, the hardware complexity of the error compensation circuit can be lowered. By constructing the error compensation circuit mainly from the “outer” p... View full abstract»

• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

Publication Year: 2012, Page(s): C3
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## Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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## Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu