# IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

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Displaying Results 1 - 17 of 17

Publication Year: 2012, Page(s): C1
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• ### IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

Publication Year: 2012, Page(s): C2
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• ### Low-Energy Standby-Sparing for Hard Real-Time Systems

Publication Year: 2012, Page(s):329 - 342
Cited by:  Papers (25)
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Time-redundancy techniques are commonly used in real-time systems to achieve fault tolerance without incurring high energy overhead. However, reliability requirements of hard real-time systems that are used in safety-critical applications are so stringent that time-redundancy techniques are sometimes unable to achieve them. Standby sparing as a hardware-redundancy technique can be used to meet hig... View full abstract»

• ### Analytical Optimization of Bit-Widths in Fixed-Point LTI Systems

Publication Year: 2012, Page(s):343 - 355
Cited by:  Papers (17)
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Analyses of range and precision are important for high-level synthesis and verification of fixed-point circuits. Conventional range and precision analysis methods mostly focus on combinational arithmetic circuits and suffer from major inefficiencies when dealing with sequential linear-time-invariant circuits. Such problems mainly include inability to analyze precision when quantization of constant... View full abstract»

• ### Efficient Full-Chip Statistical Leakage Analysis Based on Fast Matrix Vector Product

Publication Year: 2012, Page(s):356 - 369
Cited by:  Papers (1)
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Power consumption has become a major concern since the integrated circuit industry entered the nanometer design regime. Due to the increasing process variation, deterministic leakage power analysis becomes inadequate and thus statistical analysis is required. The challenges of statistical leakage analysis are that the huge number of random variables make trivial computation of the variance in O... View full abstract»

• ### Design and Implementation of Block-Based Partitioning for Parallel Flip-Chip Power-Grid Analysis

Publication Year: 2012, Page(s):370 - 379
Cited by:  Papers (1)
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Power-grid analysis is one of the critical design steps to ensure circuit reliability and achieve performance targets for very large scale integration systems. With each new technology generation, the circuit size has decreased and the power density has increased. Consequently, power-grid analysis has become ever more complex with greater CPU runtime and memory usage requirements. For a state-of-t... View full abstract»

• ### A Quadratic Eigenvalue Solver of Linear Complexity for 3-D Electromagnetics-Based Analysis of Large-Scale Integrated Circuits

Publication Year: 2012, Page(s):380 - 390
Cited by:  Papers (7)
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It is of critical importance to efficiently and accurately predict global resonances of a 3-D integrated circuit system that involves arbitrarily shaped lossy conductors and inhomogeneous materials. A quadratic eigenvalue solver of linear complexity and electromagnetic accuracy is developed in this paper to fulfill this task. Without sacrificing accuracy, the proposed eigenvalue solver has shown a... View full abstract»

• ### Synthesis of Active-Mode Power-Gating Circuits

Publication Year: 2012, Page(s):391 - 403
Cited by:  Papers (7)
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Active leakage is transient, which can be suppressed by design techniques such as dual-Vt. Active-mode power-gating (AMPG) can further reduce active leakage by power-gating groups of gates that perform computations with results that are not loaded due to clock-gating. AMPG involves several challenges; the grouping of gates must take circuit timing into account, and current switches need to ... View full abstract»

• ### Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors

Publication Year: 2012, Page(s):404 - 417
Cited by:  Papers (7)
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Conventional computer-aided design (CAD) methodologies optimize a processor module for correct operation and prohibit timing violations during nominal operation. We propose recovery-driven design, a design approach that optimizes a processor module for a target timing error rate (ER) instead of correct operation. The target ER is chosen based on how many errors can be gainfully tolerated by a hard... View full abstract»

• ### Intelligent Hotspot Prediction for Network-on-Chip-Based Multicore Systems

Publication Year: 2012, Page(s):418 - 431
Cited by:  Papers (12)  |  Patents (3)
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Hotspots are network-on-chip (NoC) routers or modules in multicore systems which occasionally receive packetized data from other networked element producers at a rate higher than they can consume it. This adverse phenomenon may greatly reduce the performance of NoCs, especially when wormhole flow-control is employed, as backpressure can cause the buffers of neighboring routers to quickly fill-up l... View full abstract»

• ### Stochastic Analysis of Switched-Capacitor Circuits for Sampled Data Converters

Publication Year: 2012, Page(s):432 - 436
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This paper describes an original simulation-based method to derive the stochastic properties of the output noise of switched-capacitor circuits which are used in sampled-data converters. The method relies on a linear time-varying approximation of the large-signal transient response of the switched circuits. It is shown how switched-capacitor-circuit noise and quantization noise, due to the presenc... View full abstract»

• ### $O(mn)$ Time Algorithm for Optimal Buffer Insertion of Nets With $m$ Sinks

Publication Year: 2012, Page(s):437 - 441
Cited by:  Papers (6)
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Buffer insertion is an effective technique to reduce interconnect delay. In this paper, we give a simple O(mn) time algorithm for optimal buffer insertion, where m is the number of sinks and n is the number of buffer positions. When m is small, our algorithm is a significant improvement over the recent O(nlog2n) time algorithm by S... View full abstract»

• ### Efficient Trace Signal Selection for Silicon Debug by Error Transmission Analysis

Publication Year: 2012, Page(s):442 - 446
Cited by:  Papers (7)
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In this paper, a technique is presented for selecting signals to observe during silicon debug. Internal signals are used to analyze, understand, and debug circuit misbehavior. An automated procedure to select which signals to observe is proposed to facilitate early detection of circuit malfunction and to enhance the utilization of hardware resources for storage. Signals that are most often sensiti... View full abstract»

• ### Early Analysis of Critical Faults: An Approach to Test Generation From Formal Specifications

Publication Year: 2012, Page(s):447 - 451
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This paper presents a formal methodology for test generation from formal specifications. Our method can be used for test generation for critical faults in component-based designs. Test generation for critical faults is done entirely using formal specifications and therefore the theory inherently guarantees that a generated test will be applicable to any implementation of the specifications. The th... View full abstract»

• ### IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

Publication Year: 2012, Page(s): C3
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• ### IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors

Publication Year: 2012, Page(s): C4
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• ### Corrigendum to “A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints” [Jan 12 109-120]

Publication Year: 2012, Page(s): 452
Cited by:  Papers (1)
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The authors for the above titled paper were incorrectly listed. The correct list of authors is presented here. View full abstract»

## Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Rajesh Gupta
University of California, San Diego
Computer Science and Engineering
9500 Gilman Drive
La Jolla California 92093, USA
gupta@cs.ucsd.edu