IEEE Transactions on Circuits and Systems I: Regular Papers

Current multigigahertz ADC performance is limited by the sampling clock timing jitter. This paper describes the effects of clock transition time on the spurious-free dynamic range (SFDR) of a CMOS T/H circuit. A signal-dependent nonlinearity model is first introduced that provides insight on the effect of finite clock transition time, and presents the use of sinusoidal signal as the sampling clock... View full abstract»

A novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map high-level converter specifications onto transistor sizes and biasing conditions. It is based on the combination of behavioral models for performance evaluation, optimization routines to minimize the power and area consumption of the circuit solution, and an algorithm to efficiently ... View full abstract»

In this paper we present a framework for robust design of continuous-time ΣΔ modulators. The approach allows to find a modulator which maintains its performance (stability, guar anteed peak SNR, . . .) over all the foreseen parasitic effects, provided it exists. For this purpose, we have introduced the S-figure as a criterion for the robustness of a continuous-time ΣΔ m... View full abstract»

This paper presents a low-cost production test strategy for digitally-calibrated analog-to-digital converters (ADCs) that incorporate an equalization-based background calibration scheme. The test time of these designs is dominated by the long calibration time required prior to conducting the final testing. To reduce overall test time, we present a two-step calibration approach that significantly r... View full abstract»

This paper proposes a low power content addressable memory (CAM) using low swing search lines. The CAM reduces the swing voltage and the power consumption of the search lines by using CAM cells as amplifiers. The CAM cells compare the stored data with the low swing search data on the search lines. The CAM also reduces the power consumption of match lines by using low swing NAND-NOR match lines. Th... View full abstract»

Reliability and variability have become big design challenges facing submicrometer SRAM designers. A low area overhead adaptive body bias (ABB) circuit is proposed in this paper to compensate for NBTI aging and process variations to improve the SRAM reliability and yield. The proposed ABB circuit consists of a threshold voltage sensing circuit and an on-chip analog controller. Postlayout simulatio... View full abstract»

A Lyapunov approach is developed in this paper for estimation of the magnitude of self-induced oscillations for systems with piecewise linear elements. The oscillatory trajectories are bounded by invariant level sets of a piecewise quadratic Lyapunov function. An optimization problem with bilinear-matrix-inequality constraints is formulated to minimize the invariant level set and to obtain tight b... View full abstract»

In this paper, we propose a novel approach for analyzing synchronization stability in a complex delayed dynamical network via impulsive control. We present the sufficiency conditions for pinning synchronization stability of single impulsive controller for an undirected complex delayed dynamical network in the presence of identical coupling delays between nodes. We also show that a single impulsive... View full abstract»

In this paper, an analytical tuning algorithm for a pi-network impedance tuner is presented. The pi-network consists of tunable capacitors with finite tuning range, and a fixed value inductor. The algorithm is able to determine all tunable network component values for matching any given load impedance. The resulting matching performance measured either in terms of the input VSWR or transducer gain... View full abstract»

In this paper the electric yield of DRAM core circuits is investigated by means of a statistical approach that incorporates a hierarchical linear Gaussian model for the DRAM core sensing process and a lognormal distribution model for the DRAM cell leakage. Analytical yield expressions are obtained and found to be dominated by two independent sources-either the lognormal distribution of the cell le... View full abstract»

Dynamic voltage scaling (DVS) is an important method in managing dynamically the system supply voltage for efficient power reduction. This approach is applied in very large scale integration (VLSI). A dc-dc converter is an electronic device which allows to vary the voltage and, thus, to implement DVS technique. In this paper, a high-performance controller is presented for a novel discrete DVS conv... View full abstract»

Emerging applications such as flash-based storage systems and 10 gigabit Ethernet require that there is no error floor even at bit error rates as low as 10-12 or so. It has been found that trapping sets are responsible for the error floors of many LDPC codes with AWGN channels. This paper presents a hardware based backtracking scheme to break the trapping sets at runtime for lowering th... View full abstract»

A method for large-signal behavior verification of power electronics dc-dc converters subject to uncertain variations in operating conditions is proposed. This method relies on the computation of the reach set, i.e., the set of all possible trajectories that arise from different initial conditions, unknown-but-bounded inputs, and inherent switching. Large-signal behavior verification is accomplish... View full abstract»