# IEEE Transactions on Very Large Scale Integration (VLSI) Systems

## Filter Results

Displaying Results 1 - 23 of 23

Publication Year: 2011, Page(s):C1 - C4
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• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

Publication Year: 2011, Page(s): C2
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• ### A 0.64 mm$^{2}$ Real-Time Cascade Face Detection Design Based on Reduced Two-Field Extraction

Publication Year: 2011, Page(s):1937 - 1948
Cited by:  Papers (11)
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Face detection is widely used in portable consumer handheld devices aimed at low area, low power, and high performance applications. The boosted cascade algorithm is one of the fastest face detection algorithms in use, but its hardware implementation requires a huge amount of SRAM to store the input data, integral image, and classifiers. This paper proposes a novel cascade face detection architect... View full abstract»

• ### A Hybrid Scheme for On-Chip Voltage Regulation in System-On-a-Chip (SOC)

Publication Year: 2011, Page(s):1949 - 1959
Cited by:  Papers (11)  |  Patents (1)
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Conventional off-chip or single-stage on-chip converter will fail to meet the demand for different supply voltage domains for various functional blocks/cores in traditional or future multi-/many-core system-on-a-chips (SOCS). In this paper, a hybrid two-stage voltage regulation scheme is proposed, where the first stage consists of a switching voltage regulator located off-chip, and the second stag... View full abstract»

• ### Power-Supply Noise Reduction Using Active Inductors in Mixed-Signal Systems

Publication Year: 2011, Page(s):1960 - 1968
Cited by:  Papers (2)
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Power-supply noise is a significant problem in mixed-signal systems on a chip. This is due to the impulse like current drawn by digital CMOS gates which couples to the sensitive analog circuits through supplies and the substrate. A noise-localization technique using on-chip active inductors is proposed. This would make the noise current generated by the digital gates to remain local in the region ... View full abstract»

• ### Path Delay Test Generation Toward Activation of Worst Case Coupling Effects

Publication Year: 2011, Page(s):1969 - 1982
Cited by:  Papers (5)
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As the feature size scales down, crosstalk noise on circuit timing becomes increasingly significant. In this paper, we propose a path delay test generation method toward activation of worst case crosstalk effects, in order to decrease the test escape of delay testing. The proposed method performs transition-map-based timing analysis to identify crosstalk-sensitive critical paths, followed by a det... View full abstract»

• ### A Low-Cost Built-In Redundancy-Analysis Scheme for Word-Oriented RAMs With 2-D Redundancy

Publication Year: 2011, Page(s):1983 - 1995
Cited by:  Papers (6)
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Built-in self-repair (BISR) techniques are widely used for repairing embedded random access memories (RAMs). One key component of a BISR module is the built-in redundancy-analysis (BIRA) design. This paper presents an effective BIRA scheme which executes the 2-D redundancy allocation based on a 1-D local bitmap. Two BIRA algorithms for supporting two different redundancy organizations are also pro... View full abstract»

• ### Full Fault Resilience and Relaxed Synchronization Requirements at the Cache-Memory Interface

Publication Year: 2011, Page(s):1996 - 2009
Cited by:  Papers (1)
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While multicore platforms promise significant speedup for many current applications, they also suffer from increased reliability problems as a result of ever scaling device size. The projected elevation in fault rate, together with the diverse behavior of fault manifestation, argues for highly efficient solutions of full fault resilience. Traditional duplication and checkpointing strategies typica... View full abstract»

• ### Application-Aware Topology Reconfiguration for On-Chip Networks

Publication Year: 2011, Page(s):2010 - 2022
Cited by:  Papers (44)
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In this paper, we present a reconfigurable architecture for networks-on-chip (NoC) on which arbitrary application-specific topologies can be implemented. When a new application starts, the proposed NoC tailors its topology to the application traffic pattern by changing the inter-router connections to some predefined configuration corresponding to the application. It addresses one of the main drawb... View full abstract»

• ### FPGA Based on Integration of CMOS and RRAM

Publication Year: 2011, Page(s):2023 - 2032
Cited by:  Papers (43)  |  Patents (4)
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In this paper, a novel CMOS-nano hybrid reconfigurable field-prgrammable gate array architecture (rFPGA) is introduced based on resistive memory (RRAM) devices. Different from the existing crossbar-based CMOS-nano architectures, rFPGA consists of mainly 1T1R RRAM structures that can be fabricated by using a CMOS-compatible process. These devices can efficiently establish FPGA block memories. More ... View full abstract»

• ### Configurable Multimode Embedded Floating-Point Units for FPGAs

Publication Year: 2011, Page(s):2033 - 2044
Cited by:  Papers (14)  |  Patents (1)
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Performance of field-programmable gate arrays (FPGAs) used for floating-point applications is poor due to the complexity of floating-point arithmetic. Implementing floating-point units (FPUs) on FPGAs consume a large amount of resources. This makes FPGAs less attractive for use in floating-point intensive applications. Therefore, there is a need for embedded FPUs in FPGAs. However, if unutilized, ... View full abstract»

• ### Reconfigurable Routers for Low Power and High Performance

Publication Year: 2011, Page(s):2045 - 2057
Cited by:  Papers (15)
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Network-on-chip (NoC) designs are based on a compromise among latency, power dissipation, or energy, and the balance is usually defined at design time. However, setting all parameters, such as buffer size, at design time can cause either excessive power dissipation (originated by router under utilization), or a higher latency. The situation worsens whenever the application changes its communicatio... View full abstract»

• ### A 14-GHz AC-Coupled Clock Distribution Scheme With Phase Averaging Technique Using Single LC-VCO and Distributed Phase Interpolators

Publication Year: 2011, Page(s):2058 - 2066
Cited by:  Papers (2)
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In this paper, we report the world's first ac-coupled clock distribution circuit for low-power and high-frequency clock distribution. By employing the proposed ac-coupled LC-based voltage-controlled oscillator (LC-VCO) and phase interpolators, the use of conventional current-mode-logic (CML) buffers with large power requirements can be prevented, and power consumption for clock distribution can be... View full abstract»

Publication Year: 2011, Page(s):2067 - 2080
Cited by:  Papers (7)
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The ever increasing importance of battery-powered devices coupled with high performance requirements and shrinking process geometries have further exacerbated the problem of energy efficiency in modern embedded systems. The cache memories are a major contributor to the system power consumption, and as such have been a primary target for energy reduction techniques. Recent advances in configurable ... View full abstract»

• ### Reducing Power in All Major CAM and SRAM-Based Processor Units via Centralized, Dynamic Resource Size Management

Publication Year: 2011, Page(s):2081 - 2094
Cited by:  Papers (6)
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Power minimization has become a primary concern in microprocessor design. In recent years, many circuit and micro-architectural innovations have been proposed to reduce power in many individual processor units. However, many of these prior efforts have concentrated on the approaches which require considerable redesign and verification efforts. Also it has not been investigated whether these techni... View full abstract»

• ### Linear and Switch-Mode Conversion in 3-D Circuits

Publication Year: 2011, Page(s):2095 - 2108
Cited by:  Papers (3)
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A methodology for DC-DC conversion in three-dimensional (3-D) circuits is described in this paper. The proposed approach exploits both linear and switching buck converters with different conversion ranges, thereby increasing power efficiency. By replacing the traditional LC filter within a switching converter with a distributed filter, a significant increase in efficiency is demonstrated. Addition... View full abstract»

• ### Vibration Energy Scavenging System With Maximum Power Tracking for Micropower Applications

Publication Year: 2011, Page(s):2109 - 2119
Cited by:  Papers (25)
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In this work, we present a vibration-based energy scavenging system based on piezoelectric conversion for micropower applications. A novel maximum power point (MPP) tracking scheme is proposed to harvest the maximum power from the vibration system. A time-multiplexing mechanism is employed to perform energy harvesting and MPP tracking alternately. In the MPP tracking mode, a voltage reference that... View full abstract»

• ### Minimum Supply Voltage and Yield Estimation for Large SRAMs Under Parametric Variations

Publication Year: 2011, Page(s):2120 - 2125
Cited by:  Papers (13)
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SRAM cell minimum operation voltage (Vmin) exhibits a skewed distribution in the presence of random parametric variations. Standard Monte Carlo (MC) simulation is prohibitively expensive to estimate the tail of the Vmin distribution for large SRAMs. We propose a fast and accurate method to estimate Vmin based on the statistical trend of static noise margin with VDD scaling. Our p... View full abstract»

• ### Digit-Level Semi-Systolic and Systolic Structures for the Shifted Polynomial Basis Multiplication Over Binary Extension Fields

Publication Year: 2011, Page(s):2125 - 2129
Cited by:  Papers (3)
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Finite field multiplication is one of the most important operations in the finite field arithmetic. In this paper, we study semi-systolic and systolic implementations of the shifted polynomial basis multiplication and propose low time complexity semi-systolic and systolic array structures. We show that our proposed semi-systolic multiplier is faster than its existing counterparts available in the ... View full abstract»

• ### A Bias-Dependent Model for the Impact of Process Variations on the SRAM Soft Error Immunity

Publication Year: 2011, Page(s):2130 - 2134
Cited by:  Papers (3)
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Nanometer SRAM cells are more susceptible to the particle strike soft errors and the increased statistical process variations, in advanced nanometer CMOS technologies. In this paper, an analytical model for the critical charge variations accounting for both die-to-die (D2D) and within-die (WID) variations, over a wide range of bias conditions, is proposed. The derived model is verified and compare... View full abstract»

• ### Security Evaluation of Balanced 1-of- $n$ Circuits

Publication Year: 2011, Page(s):2135 - 2139
Cited by:  Papers (2)
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A new balanced library is presented which consists of novel mixed 1-of-2 and 1-of-4 components based on N-nary logic. Cryptographic circuit specifications are refined and passed to optimization and mapping tools for mapping to a library of power-balanced components. Logic optimization tools are then applied to generate secure synchronous circuits for layout generation. This paper presents a new te... View full abstract»

• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

Publication Year: 2011, Page(s): 2140
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• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

Publication Year: 2011, Page(s): C3
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## Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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## Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu