# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 25 of 36

Publication Year: 2011, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

Publication Year: 2011, Page(s): C2
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• ### Guest Editorial Special Section on 2010 IEEE Custom Integrated Circuits Conference (CICC 2010)

Publication Year: 2011, Page(s):1993 - 1995
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• ### Technology Variability From a Design Perspective

Publication Year: 2011, Page(s):1996 - 2009
Cited by:  Papers (11)
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Increased variability in semiconductor process technology and devices requires added margins in the design to guarantee the desired yield. Variability is characterized with respect to the distribution of its components, its spatial and temporal characteristics and its impact on specific circuit topologies. Approaches to variability characterization and modeling for digital logic and SRAM are analy... View full abstract»

• ### The Design and Characterization of a Half-Volt 32 nm Dual-Read 6T SRAM

Publication Year: 2011, Page(s):2010 - 2016
Cited by:  Papers (1)
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Dual read port 6-transistor (6T) SRAMs play a critical role in high-performance cache designs thanks to doubling of access bandwidth, but stability and sensing challenges typically limit the low-voltage operation. We report a high-performance dual read port 8-way set associative 6T SRAM with a one clock cycle access latency, in a 32 nm metal-gate partially depleted SOI process technology, for low-... View full abstract»

• ### All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control

Publication Year: 2011, Page(s):2017 - 2025
Cited by:  Papers (22)
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A 45 nm microprocessor integrates an all-digital dynamic variation monitor (DVM) to continuously measure the impact of dynamic parameter variations on circuit-level performance to enhance silicon debug and adaptive clock control. The DVM consists of a tunable replica circuit, a time-to-digital converter, and multiplexers to measure circuit delay or frequency changes with less than a 1% measured re... View full abstract»

• ### Dynamic NBTI Management Using a 45 nm Multi-Degradation Sensor

Publication Year: 2011, Page(s):2026 - 2037
Cited by:  Papers (24)
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This paper proposes a low power unified oxide and negative bias temperature instability (NBTI) degradation sensor designed in 45 nm process node. The cell power consumption is 105 lower than a previously proposed sensor. The unified nature enables efficient reliability monitoring with reduced sensor deployment effort and area overhead. Using the sensor dynamic NBTI management (DNM) has ... View full abstract»

• ### Highly Integrated and Tunable RF Front Ends for Reconfigurable Multiband Transceivers: A Tutorial

Publication Year: 2011, Page(s):2038 - 2050
Cited by:  Papers (38)  |  Patents (9)
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Architectural and circuit techniques to integrate the RF front end passive components, namely the SAW filters and duplexers that are traditionally implemented off chip, are presented. Intended for software-defined and cognitive radio platforms, tunable high-Q filters realized by CMOS switches and linear or MOS capacitors allow the integration of highly reconfigurable transceiver front ends that ar... View full abstract»

• ### Spurious-Free Time-to-Digital Conversion in an ADPLL Using Short Dithering Sequences

Publication Year: 2011, Page(s):2051 - 2060
Cited by:  Papers (12)  |  Patents (1)
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We propose an enhancement to the digital phase detection mechanism in an all-digital phase-locked loop (ADPLL) by randomization of the frequency reference using carefully chosen dither sequences. This dithering renders the digital phase detector, realized as a time-to-digital converter (TDC), free from any phase domain spurious tones generated as a consequence of an ill-conditioned sampling of the... View full abstract»

• ### A 25 Gb/s 65-nm CMOS Low-Power Laser Diode Driver With Mutually Coupled Peaking Inductors for Optical Interconnects

Publication Year: 2011, Page(s):2061 - 2068
Cited by:  Papers (11)
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A 25 Gb/s laser diode (LD) driver has been developed on the basis of standard 65 nm CMOS technology for optical interconnects. The LD driver consists of a main driver capable of providing an average current of 30 mA and a predriver providing a gain of 20 dB. The main driver uses mutually coupled inductors to adjust the inductive peaking to improve eye patterns under various packaging conditions. T... View full abstract»

• ### A Low-Power ECoG/EEG Processing IC With Integrated Multiband Energy Extractor

Publication Year: 2011, Page(s):2069 - 2082
Cited by:  Papers (35)  |  Patents (1)
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Electrocorticography (ECoG) implants have recently demonstrated promising results towards potential use in brain-computer interfaces (BCIs). Spectral changes in ECoG signals can provide insight on functional mapping of sensorimotor cortex. We present a 6.4 μ W electrocorticography (ECoG)/electroencephalography (EEG) processing integrated circuit (EPIC) with 0.46 μVrms View full abstract»

• ### A Multibit Dual-Feedback CT $\Delta\Sigma$ Modulator With Lowpass Signal Transfer Function

Publication Year: 2011, Page(s):2083 - 2095
Cited by:  Papers (13)  |  Patents (1)
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This paper presents a dual-feedback continuous-time delta-sigma modulator that features a signal transfer function with low sensitivity to coefficient variations. The anti-aliasing of this topology is similar to that of the feedback architecture while using only two feedback paths for modulators of any order. The proposed architecture is a good candidate for low-power applications as it shows rela... View full abstract»

Publication Year: 2011, Page(s):2096 - 2107
Cited by:  Papers (23)  |  Patents (3)
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This paper investigates the performance benefit of using nonuniformly quantized ADCs for implementing high-speed serial receivers with decision-feedback equalization (DFE). A way of determining an optimal set of ADC thresholds to achieve the minimum bit-error rate (BER) is described, which can yield a very different set from the one that minimizes signal quantization errors. By recognizing that bo... View full abstract»

• ### Avoiding the Gain-Bandwidth Trade Off in Feedback Amplifiers

Publication Year: 2011, Page(s):2108 - 2113
Cited by:  Papers (10)
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The gain-bandwidth conflict is one the most important limitations of high gain feedback amplifiers. In this tutorial paper we will discuss in a unified manner the most important approaches aimed to design amplifiers with a constant closed-loop bandwidth. Advantages and drawbacks are evidenced and new potential solutions are also formulated. View full abstract»

• ### Comments on “Avoiding the Gain-Bandwidth Trade Off in Feedback Amplifiers”

Publication Year: 2011, Page(s):2114 - 2116
Cited by:  Papers (5)
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In this comment, the previous work on bandwidth enhancement of finite gain amplifiers using two or more opamps is brought to the attention of the reader. An analogy between finite gain amplifiers using opamps and current feedback operational amplifiers is also presented. View full abstract»

Publication Year: 2011, Page(s): 2117
Cited by:  Papers (1)
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This paper discussed the comments on avoiding the gain-bandwidth tradeoff in feedback amplifiers. View full abstract»

• ### On the Excess Noise Factor $\Gamma$ of a FET Driven by a Capacitive Source

Publication Year: 2011, Page(s):2118 - 2126
Cited by:  Papers (4)
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The excess noise factor Γ , also known as Ogawa's noise factor, is frequently used in the literature on optical receivers to calculate the noise and sensitivity of FET front-ends. After revisiting its definition and clarifying its applications and limitations, we derive an analytical expression for Γ in terms of the channel noise factor γ, the gate noise factor δ , and ... View full abstract»

• ### A 12b 50 MS/s 21.6 mW 0.18 $\mu$m CMOS ADC Maximally Sharing Capacitors and Op-Amps

Publication Year: 2011, Page(s):2127 - 2136
Cited by:  Papers (21)
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A 12b 50 MS/s 0.18 μ m CMOS pipeline ADC is described. The proposed capacitor and operational amplifier (op-amp) sharing techniques merge the front-end sample-and-hold amplifier (SHA) and the first multiplying digital-to-analog converter (MDAC1) to achieve low power without an additional reset timing and a memory effect. The second and third MDACs share a single op-amp to reduce power consu... View full abstract»

• ### Hardware Reduction in Digital Delta-Sigma Modulators Via Bus-Splitting and Error Masking—Part I: Constant Input

Publication Year: 2011, Page(s):2137 - 2148
Cited by:  Papers (13)
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In this two-part paper, a design methodology for bus-splitting digital delta-sigma modulators (DDSMs) is presented. The design methodology is based on error masking and is applied to both ditherless and dithered DDSMs with constant and sinusoidal inputs. Rules for selecting the appropriate wordlengths of the constituent DDSMs are derived which ensure that the spectral performance of the bus-splitt... View full abstract»

• ### A Continuously Tunable Hybrid LC-VCO PLL With Mixed-Mode Dual-Path Control and Bi-level $\Delta-\Sigma$ Modulated Coarse Tuning

Publication Year: 2011, Page(s):2149 - 2158
Cited by:  Papers (4)  |  Patents (2)
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This paper presents a dual-path PLL using a hybrid VCO to perform digital based frequency acquisition and analog based bandwidth control. With the mixed-mode dual-path control, the proposed PLL significantly alleviates noise coupling and area problems in the coarse-tuning path while minimizing open-loop gain variation in the fine-tuning path. In the hybrid VCO design, the nonlinearity issue of the... View full abstract»

• ### A Two-Dimensional Configurable Active Silicon Dendritic Neuron Array

Publication Year: 2011, Page(s):2159 - 2171
Cited by:  Papers (6)
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This paper presents a 2-D programmable dendritic neuron array consisting of a 3× 32 dendritic compartment array and a 1 × 32 somatic compartment array. Each dendritic compartment contains two types of regenerative nonlinearities: a NMDA synaptic nonlinearity and a dendritic spike nonlinearity. The chip supports the programmability of local synaptic weights and the configuration of de... View full abstract»

• ### Design and Modeling of a Neuro-Inspired Learning Circuit Using Nanotube-Based Memory Devices

Publication Year: 2011, Page(s):2172 - 2181
Cited by:  Papers (9)
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We present an original method to implement neuro-inspired supervised learning for a synaptic array based on carbon nanotube devices. The device characteristics required to implement on chip learning within a crossbar of carbon nanotube field effect transistors (CNTFETs) as synaptic arrays were experimentally demonstrated and accurately modeled through a specific electrical compact model. We perfor... View full abstract»

• ### Determining the Range of the Power Consumption in Linear DC Interval Parameter Circuits

Publication Year: 2011, Page(s):2182 - 2188
Cited by:  Papers (4)
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The paper considers the following worst-case steady-state tolerance analysis problem: given a linear dc circuit whose resistors and sources have preset tolerances, determine the range of the electrical power consumed in the circuit. It is shown that the power range sought can be computed as the range of an associated interval linear programming problem. A method for solving the latter problem is s... View full abstract»

• ### Design Trade-offs in Ultra-Low-Power Digital Nanoscale CMOS

Publication Year: 2011, Page(s):2189 - 2200
Cited by:  Papers (30)
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While the general trend in CMOS technology scaling is mostly focused on high-performance and high-speed circuits, the potential use of advanced nanoscale technologies for ultra-low power (ULP) applications with lower operating frequencies is still debated. In these types of applications, the supply voltage is generally reduced well below threshold voltage of MOS devices in order to limit dissipati... View full abstract»

• ### Carry Chains for Ultra High-Speed SiGe HBT Adders

Publication Year: 2011, Page(s):2201 - 2210
Cited by:  Papers (7)
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Adder structures utilizing SiGe Hetero-junction Bipolar Transistor (HBT) digital circuits are examined for use in high clock rate digital applications requiring high-speed integer arithmetic. A 4-gate deep test structure for 32-bit addition using a 210 GHz fT process has been experimentally verified to operate with 37.5 ps delay or 26.7 GHz speed. The paper documents a unique ble... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK