IEEE Transactions on Circuits and Systems I: Regular Papers

A stochastic flash analog-to-digital converter (ADC) is presented. A standard flash uses a resistor string to set individual comparator trip points. A stochastic flash ADC uses random comparator offset to set the trip points. Since the comparators are no longer sized for small offset, they can be shrunk down into digital cells. Using comparators that are implemented as digital cells produces a lar... View full abstract»

This paper presents a new high-gain structure for the distributed amplifier. Negative capacitance cells are exploited to ameliorate the loading effects of parasitic capacitors of gain cells in order to improve the gain of the distributed amplifier while keeping the desired bandwidth. In addition, the negative capacitance circuit creates a negative resistance that can be used to increase the amplif... View full abstract»

This paper presents an optical receiver with a monolithically integrated photodetector in 0.18-μm CMOS technology using a combination of spatially modulated light (SML) detection and an analog equalizer. A transimpedance amplifier employing negative Miller capacitance is introduced to increase its bandwidth without causing gain peaking. To provide sufficient reverse-bias voltage to the phot... View full abstract»

For a ring oscillator with an arbitrary voltage swing, core transistors in delay cells typically move between saturation and triode region This can result in the overall timing jitter being dominated by timing jitter accumulated within a particular region. Based on multiple thresholds crossing concept, a new and more accurate way of handling such region change is developed. Specifically any crossi... View full abstract»

This paper presents a 10-bit 5-5 segmented current- steering digital-to-analog converter implemented in a standard 130-nm CMOS technology. It achieves full-Nyquist performance up to 1 GS/s and maintains 54-dB SFDR over a 550-MHz output bandwidth up to 1.6 GS/s. The power consumption for a near-Nyquist output signal sampled at 1.6 GS/s equals 27 mW. To enable the presented performance a design stra... View full abstract»

Supply noise affects the jitter performance of ring oscillator-based phase-locked loops (PLLs) significantly. While the focus of much of the prior art is on supply noise in oscillators, this paper illustrates that supply noise in other building blocks also contribute significantly to PLL output jitter. Analytical expressions for supply-noise sensitivities are derived for each of the circuit blocks... View full abstract»

This paper presents a self-reconfigurable channel data buffering scheme and circuit design for next-generation network-on-chips (NoCs). The design is optimized for power efficiency and data throughput, from system to circuit level. During network congestion, the buffering scheme realizes adaptive flow control by reconfiguring the channel buffers for online data storage. Once congestion is alleviat... View full abstract»

Periodic nonuniform sampling of second order (PNS2) involves two periodic sequences with the same period. This sampling scheme has been shown to remove aliasing. Moreover, under particular conditions on their spectral band (or spectral support), exact reconstruction of functions can be derived from their PNS2. This paper more generally deals with the best mean-square interpolation for stationary p... View full abstract»

We present a software simulation and a hardware proof of concept for a compact low-power lightweight ultrasonic echolocation design that is capable of imaging a 120 field of view with a single ping. The sensor uses a single transmitter and a linear array of ten microphones, followed by a bank of eight spatiotemporal filters to determine the bearing angle of returned echoes. The sensor is capable o... View full abstract»

This paper presents the closed-form designs of an infinite-impulse-response (IIR) Hilbert transformer with an integer delay. The maximally flat criterion is applied at the midband frequency π/2. These designs are further categorized into eight types according to the filter orders and the delay values being even or odd. Their coefficients can be explicitly solved in closed form. A recursive ... View full abstract»

In this paper, we describe the design of a silicon neuron that exhibits type-I neural excitability, i.e., the frequency of spiking of the neuron approaches arbitrarily close to zero as the input current is reduced. Our design creates a conductance-based silicon model that can exhibit a saddle-node bifurcation. We present simulations and measured data from circuits fabricated in 0.35-μm CMOS... View full abstract»

This paper establishes a discrete-time model and presents an exact method of stability analysis for periodic orbits containing a segment of sliding orbit for switched linear systems. Sliding dynamical equations are obtained by using Utkin's equivalent control method. Sliding mapping and impact mapping are obtained by solving the respective differential equations. A generalized discrete-time mappin... View full abstract»

This paper describes an original method to estimate the locking ranges of injection-locked frequency dividers (ILFDs) and their sensitivity to variations in parameter values. The synchronization capability of a given oscillator architecture with respect to possible injection points is explored by applying small-amplitude signals and adopting a phase-domain macromodel based on the paradigm of the p... View full abstract»

This paper studies the local and global exponential synchronization of a complex dynamical network with switching topology and time-varying coupling delays. By using stability theory of switched systems and the network topology, the synchronization of such a network under some special switching signals is investigated. Firstly, under the assumption that all subnetworks are self-synchronizing, a de... View full abstract»

Trajectory piecewise-linearization-based reduced- order macromodeling methods have been proposed to characterize the time-domain behaviors of large strongly nonlinear systems. However, all these methods rely on frequency-domain model-order-reduction (MOR) methods for linear systems. Therefore, the accuracy of the reduced-order models in time domain cannot always be guaranteed and controlled. In th... View full abstract»

In this paper, a new scheme for synchronization between two or more complex networks is proposed using scalar signals under pinning control. Unlike common synchronization schemes, where all states of the driving networks are transmitted to the response network and all the nodes in the response network are required to be controlled, here, it is suggested that only a few nodes in the response networ... View full abstract»

This paper investigates a type of systems controlled over a communication network that can only accommodate a subset of actuators at any time. The medium-access status of actuators is event driven by a stochastic process modeled as a Markov chain. A methodology of analysis and control synthesis is established using theories in time-delay systems and Markovian jumping systems. Specifically, in the ... View full abstract»

A discrete-time (DT) fast Fourier transform (FFT) processor which enables an architectural improvement to ultrawide-bandwidth orthogonal frequency-division multiplexing (OFDM) receivers for use in low-power handheld applications is presented. The new architecture performs FFT demodulation of the OFDM signal in the DT signaling domain before analog-to-digital conversion. The approach significantly ... View full abstract»

This paper analyzes the dynamics of reference tracking in switched-mode power converters in terms of both large-signal and small-signal perspectives. Common control schemes, namely, voltage mode, current mode, and V2-control, are compared for their performance in reference tracking. For small-signal analysis, loop gains and reference-to-output transfer functions are analytically derived... View full abstract»