# IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Displaying Results 1 - 19 of 19

Publication Year: 2009, Page(s): C1
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• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

Publication Year: 2009, Page(s): C2
| PDF (39 KB)
• ### Editorial Appointments for the 2009-2010 Term

Publication Year: 2009, Page(s):453 - 469
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• ### Introduction to the Special Section on Nanocircuits and Systems

Publication Year: 2009, Page(s):470 - 472
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• ### Fault Secure Encoder and Decoder for NanoMemory Applications

Publication Year: 2009, Page(s):473 - 486
Cited by:  Papers (52)
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Memory cells have been protected from soft errors for more than a decade; due to the increase in soft error rate in logic circuits, the encoder and decoder circuitry around the memory blocks have become susceptible to soft errors as well and must also be protected. We introduce a new approach to design fault-secure encoder and decoder circuitry for memory designs. The key novel contribution of thi... View full abstract»

• ### Tunneling-Based Cellular Nonlinear Network Architectures for Image Processing

Publication Year: 2009, Page(s):487 - 495
Cited by:  Papers (22)
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The resonant tunneling diode (RTD) has found numerous applications in high-speed digital and analog circuits due to the key advantages associated with its folded back negative differential resistance (NDR) current-voltage (I-V) characteristics as well as its extremely small switching capacitance. Recently, the RTD has also been employed to implement high-speed and compact cellular neural/nonlinear... View full abstract»

• ### Application Exploration for 3-D Integrated Circuits: TCAM, FIFO, and FFT Case Studies

Publication Year: 2009, Page(s):496 - 506
Cited by:  Papers (17)  |  Patents (1)
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3-D stacking and integration can provide system advantages. This paper explores application drivers and computer-aided design (CAD) for 3-D integrated circuits (ICs). Interconnect-rich applications especially benefit, sometimes up to the equivalent of two technology nodes. This paper presents physical-design case studies of ternary content-addressable memories (TCAMs), first-in first-out (FIFO) me... View full abstract»

• ### Analyzing the Inherent Reliability of Moderately Sized Magnetic and Electrostatic QCA Circuits Via Probabilistic Transfer Matrices

Publication Year: 2009, Page(s):507 - 516
Cited by:  Papers (19)
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As computing technology delves deeper into the nanoscale regime, reliability is becoming a significant concern, and in response, Teramac-like systems will be the model for many early non-CMOS nanosystems. Engineering systems of this type requires understanding the inherent reliability of both the functional cells and the interconnect used to build the system, and which components are most critical... View full abstract»

• ### A Novel Adaptive Design Methodology for Minimum Leakage Power Considering PVT Variations on Nanoscale VLSI Systems

Publication Year: 2009, Page(s):517 - 528
Cited by:  Papers (19)
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This paper proposes a novel design method to minimize the leakage power during standby mode using a novel adaptive supply voltage and body-bias voltage generating technique for nanoscale VLSI systems. The process, voltage, and temperature (PVT) variations are monitored and controlled independently by their own dedicated systems. The minimum level of V DD and the optimum body-bias... View full abstract»

• ### Analysis of Defect Tolerance in Molecular Crossbar Electronics

Publication Year: 2009, Page(s):529 - 540
Cited by:  Papers (9)
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Molecular electronics such as silicon nanowires (NW) and carbon nanotubes (CNT) demonstrate great potential for continuing the technology advances toward future nano-computing paradigm. However, excessive defects from bottom-up stochastic assembly have emerged as a fundamental obstacle for achieving reliable computation using molecular electronics. In this paper, we present an information-theoreti... View full abstract»

• ### On Efficient Implementation of Accumulation in Finite Field Over $GF(2^{m})$ and its Applications

Publication Year: 2009, Page(s):541 - 550
Cited by:  Papers (22)
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Finite field accumulation is the simplest of all the finite field operations, but at the same time, it is one of the most frequently encountered operations in finite field arithmetic. In this paper, we present a simple but highly useful modification of the conventional hardware implementation of accumulation in finite field over GF(2m) . The critical path, as well as, the hardwar... View full abstract»

• ### Efficient On-Chip Crosstalk Avoidance CODEC Design

Publication Year: 2009, Page(s):551 - 560
Cited by:  Papers (34)
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Interconnect delay has become a limiting factor for circuit performance in deep sub-micrometer designs. As the crosstalk in an on-chip bus is highly dependent on the data patterns transmitted on the bus, different crosstalk avoidance coding schemes have been proposed to boost the bus speed and/or reduce the overall energy consumption. Despite the availability of the codes, no systematic mapping of... View full abstract»

• ### A Highly Parameterized and Efficient FPGA-Based Skeleton for Pairwise Biological Sequence Alignment

Publication Year: 2009, Page(s):561 - 570
Cited by:  Papers (61)
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This paper presents the design and implementation of the most parameterisable field-programmable gate array (FPGA)-based skeleton for pairwise biological sequence alignment reported in the literature. The skeleton is parameterised in terms of the sequence symbol type, i.e., DNA, RNA, or protein sequences, the sequence lengths, the match score, i.e., the score attributed to a symbol match, mismatch... View full abstract»

• ### A Low-Noise Multi-GHz CMOS Multiloop Ring Oscillator With Coarse and Fine Frequency Tuning

Publication Year: 2009, Page(s):571 - 577
Cited by:  Papers (39)
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A 7-GHz CMOS voltage controlled ring oscillator that employs multiloop technique for frequency boosting is presented in this paper. The circuit permits lower tuning gain through the use of coarse/fine frequency control. The lower tuning gain also translates into a lower sensitivity to the voltage at the control lines. Fabricated in a standard 0.13-mum CMOS process, the proposed voltage-controlled ... View full abstract»

• ### Total Power Modeling in FPGAs Under Spatial Correlation

Publication Year: 2009, Page(s):578 - 582
Cited by:  Papers (5)
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This work describes a novel approach for total power estimation in field-programmable gate arrays (FPGAs) while considering spatial correlation among the different signals in the design. The signal probabilities under spatial correlations are used to properly model the dynamic power dissipation and the state-dependency of the leakage power dissipation in the logic and routing resources of FPGAs. M... View full abstract»

• ### High-Throughput Layered LDPC Decoding Architecture

Publication Year: 2009, Page(s):582 - 587
Cited by:  Papers (25)  |  Patents (62)
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This paper presents a high-throughput decoder architecture for generic quasi-cyclic low-density parity-check (QC-LDPC) codes. Various optimizations are employed to increase the clock speed. A row permutation scheme is proposed to significantly simplify the implementation of the shuffle network in LDPC decoder. An approximate layered decoding approach is explored to reduce the critical path of the ... View full abstract»

• ### Wafer-Level Defect Screening for “Big-D/Small-A” Mixed-Signal SoCs

Publication Year: 2009, Page(s):587 - 592
Cited by:  Papers (2)
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Product cost is a key driver in the consumer electronics market, which is characterized by low profit margins and the use of a variety of ldquobig-D/small-Ardquo mixed-signal system-on-chip (SoC) designs. Packaging cost has recently emerged as a major contributor to the product cost for such SoCs. Wafer-level testing can be used to screen defective dies, thereby reducing packaging cost. We propose... View full abstract»

• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

Publication Year: 2009, Page(s): C3
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• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

Publication Year: 2009, Page(s): C4
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## Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu