IEEE Micro

What are the symptoms of health in an innovative industry? This seemingly simple question isn't so easy to answer in the midst of a downturn, nor will it be easy to answer over the next year as high tech consolidates through exit and merger. Consolidation will lead to concentration, or what we might call pockets of monopoly. Monopolies tend not to be the most innovative organizations on the planet... View full abstract»

The Larrabee many-core visual computing architecture uses multiple in-order x86 cores augmented by wide vector processor units, together with some fixed-function logic. This increases the architecture's programmability as compared to standard GPUs. The article describes the Larrabee architecture, a software renderer optimized for it, and other highly parallel applications. The article analyzes per... View full abstract»

Uncontrolled interthread interference in main memory can destroy individual threads' memory-level parallelism, effectively serializing the memory requests of a thread whose latencies would otherwise have largely overlapped, thereby reducing single-thread performance. The parallelism-aware batch scheduler preserves each thread's memory-level parallelism, ensures fairness and starvation freedom, and... View full abstract»

It is more efficient to use increasing pin bandwidth by creating high-radix routers with a large number of narrow ports instead of low-radix routers with fewer wide ports. building networks using high-radix routers lowers cost and improves performance, but also presents many challenges. the dragonfly topology minimizes network cost by reducing the number of global channels required. View full abstract»

The enormous scale of warehouse-computing environments leads to unique requirements in which cost and power figure prominently. Models and metrics quantifying these requirements, along with a benchmark suite to capture workload behavior, help identify bottlenecks and evaluate solutions. A holistic approach leads to a new system architecture incorporating volume non-server-class components in novel... View full abstract»

Server storage systems use numerous disks to achieve high performance, thereby consuming a significant amount of power. This paper discussed the intradisk parallelism that can significantly reduce such systems' power consumption by letting disk drives exploit parallelism in the I/O request stream. By doing so, it's possible to match, and even surpass, a storage array's performance for these worklo... View full abstract»

Instruction-grain lifeguards monitor executing programs at the granularity of individual instructions to quickly detect bugs and security attacks, but their fine-grain nature incurs high monitoring overheads. This article identifies three common sources of these overheads and proposes three techniques that together constitute a general-purpose hardware acceleration framework for lifeguards. View full abstract»

Hardware can play a significant role in improving reliability of multithreaded software. Recent architectural proposals arbitrarily group consecutive dynamic memory operations into atomic blocks to enforce coarse-grained memory ordering, providing implicit atomicity. The authors of this article observe that implicit atomicity probabilistically hides atomicity violations by reducing the number of i... View full abstract»

Many code analysis techniques for optimization, debugging, and parallelization must perform runtime disambiguation of address sets. Hardware signatures support such operations efficiently and with low complexity. SoftSig exposes hardware signatures to software through instructions that control which addresses to collect and which to disambiguate against. The Memoise algorithm demonstrates SoftSig'... View full abstract»

Two proposed techniques let microprocessors operate at low voltages despite high memory-cell failure rates. They identify and disable defective portions of the cache at two granularities: individual words or pairs of bits. Both techniques use the entire cache during high-voltage operation while sacrificing cache capacity during low-voltage operation to reduce the minimum voltage below 500 mV. View full abstract»

As transistors shrink and processors trend toward low power, maintaining precise digital behavior grows more expensive. Replacing digital units with analog equivalents sometimes allows similar computation to be performed at higher speed using less power. As a case study in mixed-signal approximate computation, the authors describe an enhanced neural prediction algorithm and its efficient analog im... View full abstract»

Increased variability affects the efficiency of dynamic power and thermal management. Existing on-chip sensor infrastructure can be used to improve the inherent thermal imbalances among cores in a multicore architecture. Experimental analysis based on live measurements on a special test chip shows reduced on-chip heating with no performance loss. View full abstract»

Process variations will significantly degrade the performance benefits of future microprocessors as they move toward nanoscale technology. Device parameter fluctuations can introduce large variations in peak operation among chips, cores on a single chip, and microarchitectural blocks within one core. The revival technique combines the post-fabrication tuning techniques voltage interpolation (VI) a... View full abstract»