IEE Proceedings I - Solid-State and Electron Devices

A comparison of semiconductor technologies for VLSI is presented with particular reference to the limitations imposed by fundamental, technological and circuit-design considerations. Unichannel MOS and CMOS on single-crystal silicon or insulating substrates are the primary subjects for discussion. View full abstract»

The paper reviews the various approaches to the modelling of small-geometry MOS devices. The physics and interaction of device properties in small MOSFETs are discussed as they apply to device and circuit design for VLSI. It is shown that statistical fluctuation of device geometry and the effect of parasitics is the primary determinant of circuit performance. Scaling theory for MOSFETs and limits ... View full abstract»

Performance of one-device cells for dynamic random-access memories is described in terms of signal, noise, speed, soft error and process complexity. From an examination of areal layout and cross-section, five kinds of cells used in commercially available 64 Kbit DRAMs are compared, placing stress on the concept of the folded-data and open-data lines. Somes new DRAM cell concepts, such as a vertica... View full abstract»

Results of an n-MOS process with minimum feature sizes in the submicron range are reported. Lithography is realised by 10:1 optical printing with step-and repeat exposure. Minimum linewidths of 0.7µm have been achieved using a high numerical aperture projection optics with 0.42NA. In order to obtain high fidelity in pattern transfer, anisotropic dry-etching techniques have been used for al... View full abstract»

New kinds of hot-carrier injection mechanisms, which are different from channel hot-electron and substrate hot-electron injection mechanisms already reported by Ning, et al., are presented. These are first drain avalanche hot-carrier (DAHC) injection and secondly substrate current induced hot-electron (SCHE) injection. DAHC injection is due to the emission of electrons and holes heated in the drai... View full abstract»

The main objective of the work is to study the effects of the physical and technology parameters on the delay times of bipolar transistors in a VLSI environment. Expressions for the transit time in a very narrow base, and the storage time due to the minority charge in the emitter region will be derived. The analysis will be performed using typical substrate (which is the emitter in I2 L structures... View full abstract»