# IEEE Transactions on Electron Devices

## Filter Results

Displaying Results 1 - 25 of 43

Publication Year: 2008, Page(s):C1 - 2534
| PDF (65 KB)
• ### IEEE Transactions on Electron Devices publication information

Publication Year: 2008, Page(s): C2
| PDF (57 KB)
• ### Expanding the Editorial Board

Publication Year: 2008, Page(s):2535 - 2536
| PDF (72 KB) | HTML
• ### Technology Circuit Co-Design for Ultra Fast InSb Quantum Well Transistors

Publication Year: 2008, Page(s):2537 - 2545
Cited by:  Papers (3)
| | PDF (1378 KB) | HTML

Indium antimonide (InSb)-based quantum-well field- effect transistors (QWFETs) are conceived as a promising candidate for low-voltage high-performance applications. In this paper, we show complete technology-circuit assessment of InSb-based QWFETs. The codesign approach spans from the device/SPICE models, logic/memory circuit analysis, to technology requirements. We show the feasibility of the use... View full abstract»

• ### Lateral and Vertical Scaling of $\hbox{In}_{0.7} \hbox{Ga}_{0.3}\hbox{As}$ HEMTs for Post-Si-CMOS Logic Applications

Publication Year: 2008, Page(s):2546 - 2553
Cited by:  Papers (45)
| | PDF (1465 KB) | HTML

In this paper, we have experimentally investigated the impact of lateral and vertical scaling of In0.7Ga0.3As high-electron-mobility transistors (HEMTs) onto their logic performance. We have found that reducing the In0.52Al0.48As insulator thickness results in much better electrostatic integrity and improved short-channel behavior down to a gate length o... View full abstract»

• ### Simulation of Life Testing Procedures for Estimating Long-Term Degradation and Lifetime of AlGaN/GaN HEMTs

Publication Year: 2008, Page(s):2554 - 2560
Cited by:  Papers (10)
| | PDF (576 KB) | HTML

Finite element 3-D thermal simulations of long-term degradation in AlGaN/GaN HEMTs for high-power applications are reported on, in which temperature evolves over time as the local degradation rate varies within the modeled device based on the local temperature of the degrading region (i.e., the channel). Specifically, hotter regions within a device are modeled as degrading faster due to a thermal ... View full abstract»

• ### Modeling of Short-Channel Effects in Organic Thin-Film Transistors

Publication Year: 2008, Page(s):2561 - 2567
Cited by:  Papers (19)
| | PDF (703 KB) | HTML

We propose a model for short-channel organic thin-film transistors, which accounts for Poole-Frenkel field-dependent mobility and space-charge-limited current effects. The model is developed for devices operating in the linear regime, as well as in depletion and saturation regimes. Super linear output curves for low drain voltages, as well as nonsaturating currents, can be adequately described. Ex... View full abstract»

• ### Tunable Capacitor Based on Polymer-Dispersed Liquid Crystal for Power Harvesting Microsystems

Publication Year: 2008, Page(s):2568 - 2573
Cited by:  Papers (3)  |  Patents (4)
| | PDF (722 KB) | HTML

A tunable capacitor based on polymer-dispersed liquid-crystal (PDLC) technology is presented in this paper. Its application for robust power harvesting microsystems was investigated. The power harvesting device utilized a piezoelectric microcantilever excited by ambient random vibrations to convert mechanical energy into electric power. For improving the power harvesting efficiency, the PDLC tunab... View full abstract»

• ### Performance Modeling for Single- and Multiwall Carbon Nanotubes as Signal and Power Interconnects in Gigascale Systems

Publication Year: 2008, Page(s):2574 - 2582
Cited by:  Papers (91)
| | PDF (954 KB) | HTML

Using physics-based circuit models, the performances of carbon nanotube (CNT) interconnects, both single- and multiwall (SWNT and MWNT), are benchmarked against their copper counterparts at a realistic operating temperature (100degC). The models used capture various electron phonon scattering mechanisms and the dependence of quantum conductance on temperature and diameter. It is demonstrated that ... View full abstract»

• ### Temperature Coefficient of Poly-Silicon TFT and its Application on Voltage Reference Circuit With Temperature Compensation in LTPS Process

Publication Year: 2008, Page(s):2583 - 2589
Cited by:  Papers (3)
| | PDF (766 KB) | HTML

The temperature coefficient (TC) of n-type polycrystalline silicon thin-film transistors (poly-Si TFTs) is investigated in this paper. The relationship between the TC and the activation energy is observed and explained. From the experimental results, it is also found that TC is not sensitive to the deviation of the laser crystallization energy. On the contrary, channel width can effectively modula... View full abstract»

• ### A Dual-Capture Wide Dynamic Range CMOS Image Sensor Using Floating-Diffusion Capacitor

Publication Year: 2008, Page(s):2590 - 2594
Cited by:  Papers (16)  |  Patents (2)
| | PDF (799 KB) | HTML

A dual-capture wide dynamic range CMOS image sensor using an in-pixel floating-diffusion (FD) storage capacitor is proposed. The proposed structure uses the FD as a storage capacitor. The potential of the FD node is read out using a floating-gate capacitor without a contact metallization of the FD node to reduce the leakage. The proposed sensor was fabricated using a 0.35-mum CMOS process. The chi... View full abstract»

• ### Negative Sustain Waveform for Improving Discharge Characteristics in AC Plasma Display Panel

Publication Year: 2008, Page(s):2595 - 2601
Cited by:  Papers (3)
| | PDF (1274 KB) | HTML

The discharge characteristics produced by a negative sustain waveform were examined in comparison with those produced by a positive sustain waveform. An image-intensified charge-coupled device (ICCD) revealed that the negative sustain waveform produced a faster and stronger sustain discharge than the positive sustain waveform. Simulation results also showed that the fast and strong sustain dischar... View full abstract»

• ### TCAD Assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET and Its Multilayered Gate Architecture—Part I: Hot-Carrier-Reliability Evaluation

Publication Year: 2008, Page(s):2602 - 2613
Cited by:  Papers (19)
| | PDF (1775 KB) | HTML

This paper discusses a hot-carrier-reliability assessment, using ATLAS device simulation software, of a gate electrode workfunction engineered recessed channel (GEWE-RC) MOSFET involving an RC and GEWE design integrated onto a conventional MOSFET. Furthermore, the impact of gate stack architecture and structural design parameters, such as gate length, negative junction depth, substrate doping (... View full abstract»

• ### Development of an Ultrafast On-the-Fly $I_{\rm DLIN}$ Technique to Study NBTI in Plasma and Thermal Oxynitride p-MOSFETs

Publication Year: 2008, Page(s):2614 - 2622
Cited by:  Papers (19)
| | PDF (751 KB) | HTML

An ultrafast on-the-fly technique is developed to study linear drain current (I DLIN) degradation in plasma and thermal oxynitride p-MOSFETs during negative-bias temperature instability (NBTI) stress. The technique enhances the measurement resolution (ldquotime-zerordquo delay) down to 1 mus and helps to identify several key differences in NBTI behavior between plasma and thermal... View full abstract»

• ### Semianalytical Modeling of Short-Channel Effects in Lightly Doped Silicon Trigate MOSFETs

Publication Year: 2008, Page(s):2623 - 2631
Cited by:  Papers (32)
| | PDF (528 KB) | HTML

A simple analytical expression of the 3-D potential distribution along the channel of lightly doped silicon trigate MOSFETs in weak inversion is derived, based on a perimeter-weighted approach of symmetric and asymmetric double-gate MOSFETs. The analytical solution is compared with the numerical solution of the 3-D Poisson's equation in the cases where the ratios of channel length/silicon thicknes... View full abstract»

• ### Impact of Shear Strain and Quantum Confinement on $\langle\hbox{110}\rangle$ Channel nMOSFET With High-Stress CESL

Publication Year: 2008, Page(s):2632 - 2640
Cited by:  Papers (3)
| | PDF (488 KB) | HTML

In this paper, we propose a new analytical electron mobility model in strained Si inversion layers suitable for implementation in a drift-diffusion simulator. Using our new model, a numerical study in conjunction with comprehensive bending experiments has demonstrated that (100)-Si has the optimum channel direction along <110> in terms of the device performance of strained 65-nm-node nMOSFET... View full abstract»

• ### Determination of Work Functions in the $\hbox{Ta}_{1 - x}\hbox{Al}_{x}\hbox{N}_{y}/\hbox{HfO}_{2}$ Advanced Gate Stack Using Combinatorial Methodology

Publication Year: 2008, Page(s):2641 - 2647
Cited by:  Papers (5)
| | PDF (707 KB) | HTML

Combinatorial methodology enables the generation of comprehensive and consistent data sets, compared with the ldquoone-composition-at-a-timerdquo approach. We demonstrate, for the first time, the combinatorial methodology applied to the work function (Phim) extraction for Ta1-xAlxNy alloys as metal gates on HfO2, for complementary metal-oxide-... View full abstract»

• ### Effective Work Function Control With Aluminum Postdoping in the Ni Silicide/HfSiON Systems

Publication Year: 2008, Page(s):2648 - 2656
Cited by:  Papers (8)
| | PDF (1082 KB) | HTML

A simplified method of effective work function (Phieff) control to near the Si conduction band edge (Ec) was demonstrated in the Ni fully silicided (Ni-FUSI) gate/HfSiON system. The Phieff of NiSi (4.51 eV) decreased and saturated at 4.27 eV, owing to the use of an Al postdoping process, in which the implantation of Al ions into the upper part of the Ni silicide gate e... View full abstract»

• ### Forward Body Biasing as a Bulk-Si CMOS Technology Scaling Strategy

Publication Year: 2008, Page(s):2657 - 2664
Cited by:  Papers (15)
| | PDF (1421 KB) | HTML

Forward body biasing is a promising approach for realizing optimum threshold-voltage (V TH) scaling in the era when gate dielectric thickness can no longer be scaled down. This is confirmed experimentally and by simulation of a 10-nm gate length MOSFET. Because forward body bias (VF) decreases the depletion width (X DEP) in the channel region, it reduces ... View full abstract»

• ### A Comparative Study of Dopant-Segregated Schottky and Raised Source/Drain Double-Gate MOSFETs

Publication Year: 2008, Page(s):2665 - 2677
Cited by:  Papers (45)  |  Patents (2)
| | PDF (1021 KB) | HTML

The performance of symmetric double-gate MOSFETs with dopant-segregated Schottky (DSS) source/drain (S/D) regions is investigated through a TCAD modeling study and compared to the performance of raised S/D (RSD) MOSFETs. It is shown that, while the doped extension region adjacent to the S/D Schottky barrier (SB) improves drive current by shrinking the SB, it is fundamentally limited by its dual ro... View full abstract»

• ### Precise Modeling Framework for Short-Channel Double-Gate and Gate-All-Around MOSFETs

Publication Year: 2008, Page(s):2678 - 2686
Cited by:  Papers (40)
| | PDF (561 KB) | HTML

A precise modeling framework for short-channel nanoscale double-gate (DG) and gate-all-around (GAA) MOSFETs is presented. For the DG MOSFET, the modeling is based on a conformal mapping analysis of the potential distribution in the device body arising from the interelectrode capacitive coupling, combined with a self-consistent procedure to include the effects of the inversion charge. The DG intere... View full abstract»

• ### Thickness Dependence of Hole Mobility in Ultrathin SiGe-Channel p-MOSFETs

Publication Year: 2008, Page(s):2687 - 2694
Cited by:  Papers (30)
| | PDF (1194 KB) | HTML

A fundamental understanding of the mechanisms responsible for the dependence of hole mobility on SiGe channel layer thickness is presented for channel thicknesses down to 1.8 nm. This understanding is critical to the design of strained SiGe p-MOSFETs, as lattice mismatch limits the thickness of SiGe that can be grown on Si and as Ge outdiffusion during processing reduces the Ge fraction. Temperatu... View full abstract»

• ### Ultimate Accuracy for the nand Flash Program Algorithm Due to the Electron Injection Statistics

Publication Year: 2008, Page(s):2695 - 2702
Cited by:  Papers (41)
| | PDF (267 KB) | HTML

This paper investigates the ultimate accuracy of the NAND flash program algorithm that is determined by the statistical injection of electrons from the substrate to the floating gate. The granular nature of the electron flow during a constant-current Fowler-Nordheim program operation is shown to spread the programmed threshold-voltage distribution of the array cells. The electron injection statist... View full abstract»

• ### Gate Influence on the Layout Sensitivity of $\hbox{Si}_{1 - x}\hbox{Ge}_{x}\ \hbox{S/D}$ and $\hbox{Si}_{1 - y}\hbox{C}_{y}\ \hbox{S/D}$ Transistors Including an Analytical Model

Publication Year: 2008, Page(s):2703 - 2711
Cited by:  Papers (17)
| | PDF (646 KB) | HTML

We present a simulation study on the effect of the gate module on the channel stress in Si1-xGex and Si1-yCy S/D MOS transistors. Stiff gate materials, such as titanium nitride, lead to a decreased channel stress, while a replacement-gate scheme allows the increase of the effectiveness of the Si1-xGex and Si1-yCy View full abstract»

• ### Effects of Parasitic Capacitance, External Resistance, and Local Stress on the RF Performance of the Transistors Fabricated by Standard 65-nm CMOS Technologies

Publication Year: 2008, Page(s):2712 - 2717
Cited by:  Papers (9)
| | PDF (587 KB) | HTML

Effects of parasitic capacitance, external resistance, and local stress on the radio-frequency (RF) performance of the transistors fabricated by 65-nm CMOS technology have been investigated. The effect of parasitic capacitance, particularly Cgb, becomes significant due to the reduced spacing between the gate and the substrate contact (SC) in proportion to scaling down. Current drivabili... View full abstract»

## Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy