# IEEE Transactions on Circuits and Systems II: Express Briefs

## Filter Results

Displaying Results 1 - 25 of 26

Publication Year: 2008, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

Publication Year: 2008, Page(s): C2
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• ### A Gate Leakage Feedback Element in an Adaptive Amplifier Application

Publication Year: 2008, Page(s):101 - 105
Cited by:  Papers (4)
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This brief presents a method to exploit gate leakage (GL) to create a feedback element for an input offset insensitive and output offset programmable inverting amplifier. Measurements are shown from a test circuit produced in a 90-nm multithreshold CMOS process where a GL element uses thin oxide and a amplifier input stage uses thick oxide. The feedback element has very high nonlinear impedance fr... View full abstract»

• ### Performance Analysis of a Robust Photometer Circuit

Publication Year: 2008, Page(s):106 - 110
Cited by:  Papers (5)
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In this brief, the performance analysis of a photometer circuit based on a robust two degrees-of-freedom controller is presented. Here, the closed-loop transfer function of the complex feedback system is shown as a function of the operational amplifier parameters. Also, the stability region of the robust photometer circuit is calculated, and the performance of this circuit is compared against the ... View full abstract»

• ### DAC Quantization-Noise Cancellation in an Echo-Canceling Transceiver

Publication Year: 2008, Page(s):111 - 115
Cited by:  Papers (4)
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Data converters, in particular, the transmit digital-to-analog converter (DAC), should not limit performance in a full-duplex digital-communication transceiver. Typically, the number of DAC bits is chosen to be large enough so that the effect of DAC quantization noise on the local receiver is negligibly small. As described in this brief, the DAC quantization noise can be cancelled in an echo-cance... View full abstract»

• ### A 0.004-mm$^{2}$ Portable Multiphase Clock Generator Tile for 1.2-GHz RISC Microprocessor

Publication Year: 2008, Page(s):116 - 120
Cited by:  Papers (8)  |  Patents (1)
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Portable multiphase clock generators capable of adjusting its clock phase according to input clock frequencies have been developed both in a 0.18-mum and in a 0.13-mum CMOS technologies. They consist of a full-digital CMOS circuit design that leads to a simple, robust, and portable IP. In addition, their open-loop architecture lead to no jitter accumulation and one-cycle lock characteristic that e... View full abstract»

• ### MOS Translinear Principle for All Inversion Levels

Publication Year: 2008, Page(s):121 - 125
Cited by:  Papers (9)
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In this brief, we derive a translinear principle for alternating loops of saturated MOS transistors that is valid at all levels of inversion starting from a simplified version of the Enz-Krummanacher-Vittoz model of the MOS transistor. This generalized translinear principle reduces to the conventional one when all transistors in a translinear loop are biased in weak inversion and it reduces to the... View full abstract»

• ### A Low-Noise CMOS Distributed Amplifier for Ultra-Wide-Band Applications

Publication Year: 2008, Page(s):126 - 130
Cited by:  Papers (34)
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To employ the distributed amplification technique for the design of ultra-wide-band low-noise amplifiers, the poor noise performance of the conventional distributed amplifiers (DAs) needs to be improved. In this work, the terminating resistor of the gate transmission line, a main contributor to the overall DA's noise figure, is replaced with a resistive-inductive network. The proposed terminating ... View full abstract»

• ### Class-AB Fully Differential Voltage Followers

Publication Year: 2008, Page(s):131 - 135
Cited by:  Papers (3)
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Two fully differential class-AB voltage followers with essentially enhanced slew rate are introduced. The first one is based on the crossquad cell. The second one is based on the conventional voltage follower. Class-AB operation with accurate control of the quiescent current and extended bandwidth is achieved in both cases with minimal additional circuitry, zero extra static power dissipation and ... View full abstract»

• ### A 0.18-$mu{hbox {m}}$ CMOS 1.25-Gbps Automatic-Gain-Control Amplifier

Publication Year: 2008, Page(s):136 - 140
Cited by:  Papers (19)
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A 1.25-Gbps automatic-gain-control (AGC) amplifier is presented and it has been fabricated in 0.18-mum CMOS technology. To achieve a constant settling time, this AGC amplifier with the proposed variable gain amplifier (VGA) is presented. The measured VGA has a gain tuning range of 28.5 dB from -10 to 18.5 dB, and its measured group delay is about 12.15 ns. For the bit-error rate of 10-12 View full abstract»

• ### Single-Phase SP-Domino: A Limited-Switching Dynamic Circuit Technique for Low-Power Wide Fan-in Logic Gates

Publication Year: 2008, Page(s):141 - 145
Cited by:  Papers (15)
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The high switching activity of wide fan-in dynamic domino gates introduces significant power overhead that poses a limitation on using these compact high-speed circuits. This paper presents a new limited-switching clock-delayed dynamic circuit technique, called SP-Domino, which achieves static-like switching behavior, while maintaining the low-area and high-performance characteristics of wide fan-... View full abstract»

• ### An Indexed-Scaling Pipelined FFT Processor for OFDM-Based WPAN Applications

Publication Year: 2008, Page(s):146 - 150
Cited by:  Papers (30)
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In this brief, a high-throughput and low-complexity fast Fourier transform (FFT) processor for wideband orthogonal frequency division multiplexing communication systems is presented. A new indexed-scaling method is proposed to reduce both the critical-path delay and hardware cost by employing shorter wordlength. Together with the mixed-radix multipath delay feedback structure, the proposed FFT pro... View full abstract»

• ### Hardware-Efficient Systolic-Like Modular Design for Two-Dimensional Discrete Wavelet Transform

Publication Year: 2008, Page(s):151 - 155
Cited by:  Papers (10)  |  Patents (1)
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A systolic-like modular architecture is presented for hardware-efficient implementation of two-dimensional (2-D) discrete wavelet transform (DWT). The overall computation is decomposed into two distinct stages; where column processing is performed in stage-1, while row processing is performed in stage-2. Using a new data-access scheme and a novel folding technique, the computation of both the stag... View full abstract»

• ### A Single-Data-Bit Blind Oversampling Data-Recovery Circuit With an Add-Drop FIFO for USB2.0 High-Speed Interface

Publication Year: 2008, Page(s):156 - 160
Cited by:  Papers (11)
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A compact blind oversampling data-recovery circuit was implemented by using a coarse data-recovery block and an add-drop first-in first out, and it was successfully applied to the universal serial bus (USB)2.0 high-speed packet data transmission. The proposed circuit recovered the serial input data by selecting the sampled data among the 5X oversampled data of a single data bit. It reduced the num... View full abstract»

• ### A Class of SIC Circuits: Theory and Application in BIST Design

Publication Year: 2008, Page(s):161 - 165
Cited by:  Papers (11)
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This paper proposes a simplified algebraic model to present the complex configurations of single input change (SIC) circuits, and investigates the relationship between the SIC sequence and its generating circuit. Furthermore, several key properties of the studied sequence are provided and theoretically proved. Based on the above, we discover the commonness of different configurations of SIC circui... View full abstract»

• ### An Attack Against the Revised Murthy–Swamy Cryptosystem

Publication Year: 2008, Page(s):166 - 167
Cited by:  Papers (3)
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Murthy and Swamy proposed a symmetric key encryption system based on Brahmagupta-Bhaskara equation over . In response to a known plaintext attack presented by the author, Murthy and Swamy modified their system to resist this attack. In this correspondence, we show that the modified cryptosystem can still be broken by a low complexity known plaintext attack. View full abstract»

• ### Representations of Linear Dual-Rate System Via Single SISO LTI Filter, Conventional Sampler and Block Sampler

Publication Year: 2008, Page(s):168 - 172
Cited by:  Papers (10)
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In this brief, it is proved that a linear dual-rate system can be represented via a series cascade of: 1) a conventional expander, a single-input single-output (SISO) linear time-invariant (LTI) filter and a block decimator, or 2) a block expander, an SISO LTI filter and a conventional decimator. Hence, incompatible nonuniform filter banks could achieve perfect reconstruction via LTI filters, conv... View full abstract»

• ### Design of Multiplierless Lattice QMF: Structure and Algorithm Development

Publication Year: 2008, Page(s):173 - 177
Cited by:  Papers (10)
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In this brief, efficient multiplierless design of lattice quadrature mirror filter bank is presented. Previous work by the authors has shown that splitting each lattice stage into cascade of subrotations results in larger stopband attenuation of filter than the conventional direct quantization. This brief extends the work further by exploiting the subrotations which yield more flexible sum of sign... View full abstract»

• ### Improved Delay-Dependent $H_{infty }$ Filtering Design for Discrete-Time Polytopic Linear Delay Systems

Publication Year: 2008, Page(s):178 - 182
Cited by:  Papers (78)
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This brief revisits the problem of delay-dependent robust Hinfin filtering design for discrete-time polytopic linear systems with interval-like time-varying delay. Under the condition whether the unknown parameters can be measured online or not, a parameter-dependent or a parameter-independent filter is respectively developed which guarantees the asymptotic stability of the resulting fi... View full abstract»

• ### Adaptive Feedback Synchronization of a General Complex Dynamical Network With Delayed Nodes

Publication Year: 2008, Page(s):183 - 187
Cited by:  Papers (135)
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In the past decade, complex networks have attracted much attention from various fields of sciences and engineering. Synchronization is a typical collective behavior of complex networks that has been extensively investigated in recent years. To reveal the dynamical mechanism of synchronization in complex networks with time delays, a general complex dynamical network with delayed nodes is further st... View full abstract»

• ### On the External Positivity of Linear Time-Invariant Dynamic Systems

Publication Year: 2008, Page(s):188 - 192
Cited by:  Papers (1)
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This brief is devoted to present a general method to characterize precisely the external positivity property of linear time-invariant continuous-time dynamic systems which is based on the Post formula for Laplace inversion. View full abstract»

• ### Constrained Control of Positive Discrete-Time Systems With Delays

Publication Year: 2008, Page(s):193 - 197
Cited by:  Papers (47)
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This brief addresses the control problem of linear time-invariant discrete-time systems with delays. The control is under positivity constraint, which means that the resulting closed-loop systems are not only stable, but also positive. The contribution lies in three aspects. First, a necessary and sufficient condition is established for the existence of such controllers for discrete-time delayed s... View full abstract»

• ### A Fast, Sigma–Delta $(Sigma Delta)$ Boost DC–DC Converter Tolerant to Wide LC Filter Variations

Publication Year: 2008, Page(s):198 - 202
Cited by:  Papers (10)
| | PDF (898 KB) | HTML

Power supplies in portable electronics must adapt to their highly integrated environments and, more intrinsically, respond quickly to fast load dumps. However, frequency compensation must cater to the worst case design LC combination, be it because of tolerance and/or variable design targets, limiting speed and regulation performance to the worst-case scenario, even under best case conditions. Sig... View full abstract»

• ### Order form for reprints

Publication Year: 2008, Page(s): 203
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• ### IEEE Transactions on Circuits and Systems—II: Express Briefs Information for authors

Publication Year: 2008, Page(s): 204
| PDF (33 KB)

## Aims & Scope

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Chi K. Michael Tse
Dept. of Electronic and Information Engineering
Hong Kong Polytechnic University
Hunghom, Hong Kong
cktse@ieee.org