IEEE Transactions on Circuits and Systems I: Regular Papers

This paper studies the process scalability of pulse-mode CMOS circuits for analog 2-D convolution in computer vision systems. A simple, scalable architecture for an integrate and fire neuron is presented for implementing weighted addition of pulse-frequency modulated (PFM) signals. Sources of error are discussed and modeled in a detailed behavioral simulation and compared with equivalent transisto... View full abstract»

In this paper, a hardware-realized neuromorphic system for pattern recognition is presented. The system directly captures images from the environment, and then conducts classification using a single layer neural network. Metal-oxide resistive random access memory (RRAM) is used as electronic synapses, and threshold-controlled neurons are proposed as postsynaptic neurons to save the system area and... View full abstract»

This paper studies the fixed-order piecewise-affine (PWA) output-feedback control of PWA systems in an H∞ setup. In particular, the conventional output-feedback closed-loop system is first augmented with the introduction of the input vector, and a descriptor presentation of PWA system is acquired. Then, a bounded real lemma is derived for the resulting PWA system, which is realized by the c... View full abstract»

A new complex network model, called q-snapback network, is introduced. Basic topological characteristics of the network, such as degree distribution, average path length, clustering coefficient, and Pearson correlation coefficient, are evaluated. The typical 4-motifs of the network are simulated. The robustness of both state and structural controllabilities of the network against targeted and rand... View full abstract»

In this paper, signal-to-noise ratio (SNR) degradation from random clock jitter in a current-steering digital-to-analog converter (CS-DAC) is analyzed based on a timing-to-amplitude error conversion method. A closed-form equation is derived to predict SNR for white noise clock jitter (WN-J) and low-pass filtered clock jitter (LPF-J) in non-return-to-zero (NRZ) and return-to-zero (RZ) DAC. Especial... View full abstract»

Analog integrated circuit designers always use closed-form design equations in design reasoning. However, most of the time, they have to derive all equations by hand. When high-order effects are of interest, manual derivation would become much harder. Although the art of symbolic circuit analysis has been making steady progress, symbolically generating closed-form equations for high-order effect i... View full abstract»

In this paper, we show that amplitude transitions that are inherent to the multilevel outphasing radio transmitter architecture distort the transmitted signal due to time-domain discontinuities. In order to address this challenge, we propose a new transmitter architecture called tri-phasing which avoids discontinuities in signal waveforms and thus achieves significantly better linearity than multi... View full abstract»

This paper presents a systematic method to analyze N-path mixers and filters consisting of periodically switched RC-networks of arbitrary order. It is assumed that each capacitor periodically exchanges charge with the rest of the network during the on-phase of the switching clock, then samples its charge, and holds it perfectly until the next on-phase. This assumption allows for using the adjoint ... View full abstract»

Mismatches among frequency control elements in digitally-controlled oscillators can be a significant source of phase error in digital phase-locked loops (PLLs). This paper presents a multi-rate dynamic element matching technique and an adaptive mismatch-noise cancellation (MNC) technique that work together to address this problem. The two techniques operate in background during normal PLL operatio... View full abstract»

Linear periodically time-varying (LPTV) circuits are finding increased prominence in reconfigurable transceiver applications. Impedance matching of such circuits to the antenna impedance is essential for fully on-chip receiver topologies. However, deriving the S₁₁ of an LPTV circuit is non-trivial in general. Moreover, reflections at harmonic offsets from input frequencies can also b... View full abstract»

This paper reports a 24x57 correlation filter system for object tracking applications. While digital interfacing of the input and output data enabled a standard and flexible way of communication with pre- and post-processing digital blocks, the multiply-accumulate (MAC) operations were performed in the analog domain to save power and area. The proposed system utilizes non-volatile floating-gate me... View full abstract»

Traditional wireless power transfer (WPT) systems usually adopt the single-phase-shift (SPS) control method to maintain a constant output current or a constant output voltage for various applications. However, the current-stress on one side is much higher than that of the other side especially under operating conditions with high voltage conversion ratio and light-load. This phenomenon actually ca... View full abstract»

In this paper, the fault detection problem for a class of switched nonlinear systems with unknown functions is solved. First, the unknown internal dynamics are approximated by the radial basis function neural networks due to their powerful approximation capabilities. Then, a switched nonlinear observer is developed. Based on the observer, a fault detection scheme is set up with a switched fault de... View full abstract»

This paper presents a CMOS broadband millimeter wave power amplifier (PA) based on magnetically coupled resonator (MCR) matching network. The MCR matching network is analyzed theoretically. Design method for MCR-based broadband PA is proposed. For the PA's output matching network, the inductance ratio should be equal to the load/source resistance ratio to achieve broadband impedance transformation... View full abstract»

Fractional-N frequency synthesizers contain a divider controller which implements the fractional division. The interaction between the quantization noise from the divider controller and nonlinearities within the synthesizer will cause undesirable degradation of the output phase noise performance. The most common divider controller architecture is the Multi-stAge noiSe sHaping Digital Delta-Sigma M... View full abstract»

The Gallager B (GaB), among the hard-decision class of low-density-parity-check (LDPC) algorithms, is an ideal candidate for designing high-throughput decoder hardware. However, GaB suffers from poor error-correction performance. We introduce a probabilistic GaB (PGaB) algorithm that disturbs the decisions made during the decoding iterations randomly with a probability value determined based on ex... View full abstract»

This paper presents a low-voltage low-phase-noise LC voltage-controlled-oscillator (VCO) with a novel two-tank transformer-feedback topology. The flicker noise up-conversion is suppressed by making the drain impedance of the cross-coupled transistors to be a real number at the second harmonic of the oscillation. The loaded quality factor is boosted and the noise contribution from the transconducto... View full abstract»

An ultrasound transmitter based on a high-voltage digital-to-analog converter (HVDAC) is presented in this paper. The transmitter is implemented in a 0.25-μm high-voltage CMOS process provided by foundry, integrating the digital control circuitry and HVDAC on a single chip. By employing a fast-slewing DAC in conjunction with a standard DAC, the proposed circuit is optimized for high-speed o... View full abstract»

The RF section of a software-defined-radio receiver front-end with harmonic rejection is presented. The proposed mixer-based receiver provides two programmable notches that can be located in any desired frequencies, e.g., the third and fifth harmonics of the sampling frequency in the proposed receiver. These rejections at the third and fifth harmonics are implemented using two RF-signal paths with... View full abstract»

Multiple-clock-cycle, signal adaptive, and fully pipelined hardware design of the optimal (Wiener) space/spatial-frequency (S/SF) filter is developed in this paper. All implementation and verification details, as well as the extensive comparative analysis, are provided. The developed solution optimizes critical design performances related to the hardware complexity, in line with multiple-clock-cyc... View full abstract»

This paper proposes a self-powered disposable supply-sensing biosensor platform for big-data-based healthcare applications. The proposed supply-sensing biosensor platform is based on bio fuel cells and a 0.23-V 0.25-μm zero-Vth all-digital CMOS supply-controlled ring oscillator with a current-driven pulse-interval-modulated inductive-coupling transmitter. The fully digital, and current-driv... View full abstract»

A common source RF amplifier can be designed to be either power or conjugately matched at the output but not both, since the required load impedances are distinct. In this paper, we have shown that using a drain-gate feedback network brings the power and conjugate match impedances closer together, up to a point where they coincide at a cost of slightly decreased efficiency. We have thoroughly anal... View full abstract»

Subthreshold and near-threshold operations are viable approaches towards reducing both static and dynamic power in Static Random Access Memory (SRAM). However, supply scaling in SRAM cells is severely limited by process variations. Additionally, cell performance is greatly affected by local mismatch in subthreshold region, thereby prohibiting low voltage operation. In order to mitigate these issue... View full abstract»

Rate compatible modulations (RCMs) are attractive for achieving seamless and blind rate adaptation under time varying channel. Although the decoding of RCM is inherently parallel, the highly complex processing nodes, and routing congestion have prohibited the implementation of fully-parallel decoders for high throughput. In this paper, we propose a new stochastic decoding algorithm for RCM to achi... View full abstract»

The implementation of a 25.6-Gb/s four-level pulse-amplitude-modulation (4-PAM) reduced-state sliding-block Viterbi detector (VD) is presented. The power consumption of the VD is 105,mW at a supply voltage of 0.7 V, corresponding to an energy efficiency of 4.1 pJ/b. A data rate of 30.4 Gb/s is achieved with an energy efficiency of 5.3 pJ/b at a supply voltage of 0.8 V. The VD, implemented in an ex... View full abstract»