IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

To successfully design spiral inductors in increasingly complex and integrated mixed-signal systems, effective design automation techniques must be created. In this paper, the authors develop an automated synthesis methodology for integrated spiral inductors to efficiently generate Pareto-optimal designs based on application requirements. At its core, the synthesis approach employs a scalable mult... View full abstract»

The predictability of memory access patterns in embedded systems can be successfully exploited to devise effective application-specific cache optimizations. In this paper, an improved indexing scheme for direct-mapped caches, which drastically reduces the number of conflict misses by using application-specific information, is proposed. The indexing scheme is based on the selection of a subset of t... View full abstract»

Due to the shrinking of feature size and the significant reduction in noise margins, nanoscale circuits have become more susceptible to manufacturing defects, noise-related transient faults, and interference from radiation. Traditionally, soft errors have been a much greater concern in memories than in logic circuits. However, as technology continues to scale, logic circuits are becoming more susc... View full abstract»

This paper proposes a design exploration framework that considers impreciseness in design specification. In high-level synthesis, imprecise information is often encountered. Two types of impreciseness are considered, namely: 1) impreciseness underlying on functional unit specifications and 2) impreciseness due to system constraints, i.e., latency and register constraints. The framework is iterativ... View full abstract»

Deep submicrometer technology scaling has two major ramifications on the design process. First, reduced feature size significantly increases wire delay, thus resulting in critical paths being dominated by global interconnect rather than gate delays. Second, an ultrahigh level of integration mandates design of systems-on-chip that encompass numerous design blocks of decreased functional granularity... View full abstract»

Transformations using retiming and resynthesis operations are the most important and practical (if not the only) techniques used in optimizing synchronous hardware systems. Although these transformations have been studied extensively for over a decade, questions about their optimization capability and verification complexity are not answered fully. Resolving these questions may be crucial in devel... View full abstract»

Recently, design reuse has emerged as a dominant design and system-integration paradigm for modern systems on silicon. However, the intellectual-property-business model is vulnerable to many dangerous obstructions, such as misappropriation and copyright fraud. The authors propose a new method for intellectual-property protection that relies upon design watermarking at the combinational-logic-synth... View full abstract»

This paper presents a method to combine memory resizing and disk shutdown to achieve better energy savings than can be achieved individually. The method periodically adjusts the size of physical memory and the timeout value to shut down a hard disk to reduce the average energy consumption. Pareto distributions are used to model the disk idle time. The parameters of the distributions are estimated ... View full abstract»

This paper advances the state of the art by presenting a well-founded mathematical framework for modeling and manipulating Markov processes. The key idea is based on the fact that a Markov process can be decomposed into a collection of directed cycles with positive weights, which are proportional to the probability of the cycle traversals in a random walk. Two applications of this new formalism in... View full abstract»

Previous repeater-insertion algorithms for power minimization of realistic interconnect trees under given timing budgets are often time consuming. In this paper, the problem of runtime reduction for low-power repeater insertion is investigated. Specifically, a power-sensitivity analysis that links the algorithm runtime and the power dissipation result to the selection of repeater library and candi... View full abstract»

The dynamic voltage and frequency scaling technique in CPUs is an example of adjusting a device's control variable to trade off power consumption and performance. This idea of energy optimization through speed control has been subsequently applied to other components of electronic systems such as disk drives and wireless transceivers. In this paper, the energy-optimal speed profile (a function of ... View full abstract»

Depth of focus is the major contributor to lithographic process margin. One of the major causes of focus variation is imperfect planarization of fabrication layers. Presently, optical proximity correction (OPC) methods are oblivious to the predictable nature of focus variation arising from wafer topography. As a result, designers suffer from manufacturing yield loss as well as loss of design quali... View full abstract»

A new methodology is presented to assure numerically reliable integration of the magnetization slope in the Jiles-Atherton model of ferromagnetic core hysteresis. Two hardware description language (HDL) implementations of the technique are presented: one in SystemC and the other in very-high-speed integrated circuit (VHSIC) HDL (VHDL) analog and mixed signal (AMS). The new model uses timeless disc... View full abstract»

An analytical model is proposed to compute the fringe capacitance between two nonoverlapping interconnects in different layers using a conformal mapping technique. With this technique, electric field lines are geometrically approximated to separately model the different capacitive components. These components are finally combined to obtain the equivalent fringe capacitance. Using the aforementione... View full abstract»

Multipoint projection methods have gained much notoriety in model-order reduction of linear, nonlinear, and parameter-varying systems. A well-known difficulty with such methods lies in the need for clever point selection to attain model compactness and accuracy. In this paper, the authors present a method for sample point selection in multipoint projection-based model-order reduction. The proposed... View full abstract»

As the clock frequencies used in industrial applications increase, the timing requirements imposed on routing problems become tighter. Therefore, it becomes important to route the nets within tight minimum and maximum length bounds. Although the problem of routing nets to satisfy maximum length constraints is a well-studied problem, there exists no sophisticated algorithm in literature that ensure... View full abstract»

Modern field-programmable gate arrays (FPGAs) have multimillions of gates and future generations of FPGAs will be even more complex. This means that floorplanning tools will soon be extremely important for the physical design of FPGAs. Due to the heterogeneous logic and routing resources of an FPGA, FPGA floorplanning is very different from the traditional floorplanning for application-specific in... View full abstract»

In this paper, the authors introduce the concept of zero-change netlist transformations (ZCNTs) to: 1) quantify the suboptimality of existing placers on artificially constructed instances and 2) "partially" quantify the suboptimality of placers on synthesized netlists from arbitrary netlists by giving lower bounds to the suboptimality gap. Given a netlist and its placement from a placer, a class o... View full abstract»

Static power consumption due to subthreshold, gate, and junction leakages has become a significant component of the total power consumption. For nanoscale circuits, leakage poses one of the most important challenges to the continuation of Moore's law. The leakage of a logic gate varies by an order of magnitude over its Boolean input space. Thus, one way to minimize leakage in a circuit during stan... View full abstract»

A new multiple-probe method is presented for the simulation of highly nonlinear ring oscillators using the harmonic-balance method. This method is robust compared to the conventional single-probe method and readily converges for a wide range of single-ended and differential ring oscillators. Furthermore, it is computationally more efficient for ring oscillators in which the conventional single-pro... View full abstract»

The simulation of high-Q oscillators in the frequency domain is difficult due to a very small region of convergence. In this paper, globally convergent homotopy methods are combined with the harmonic balance method for simulation of high-Q oscillators. Various homotopy options have been evaluated, and an algorithm has been developed that is robust in simulating a wide range of oscillator circuits View full abstract»

A statistical sampling-based parametric analysis is presented for analyzing large power grids in a "localized" fashion. By combining random walks with the notion of "importance sampling," the proposed technique is capable of efficiently computing the impacts of multiple circuit parameters on selected network nodes. A "new localized" sensitivity analysis is first proposed to solve not only the nomi... View full abstract»

In this paper, the Newton-Krylov method is explored for robust and efficient time-domain simulation of integrated circuits with large amount of parasitic elements. Different from LU-factorization-based direct methods used in SPICE-like circuit simulators, the Newton-Krylov method uses a preconditioned Krylov-subspace iterative method for solving linearized-circuit equations. A key contribution of ... View full abstract»