IEEE Electron Device Letters

Poly-Si resistors with an unimplanted channel region (and with n-type source/drain regions) can exhibit a nonhyperbolic sine (non-sinh) I-V characteristic at low V/sub DS/ and an activation energy which is not simply decreasing monotonically with increasing V/sub DS/. These phenomena are not explained by conventional poly-Si resistor models. To describe these characteristics, a self-consistent mod... View full abstract»

Some holes created from band-to-band (B-B) tunneling in the deep-depletion region of the drain can be injected into the gate oxide and reduce the vertical field there. As a result, gate-induced drain leakage (GIDL) current decreases. This kind of hot-hole injection depends on the voltage difference between the drain and gate, due to nitridation-induced lowering of the barrier height for hole injec... View full abstract»

Amorphous silicon thin-film transistors (TFTs), in a top-gate staggered electrode structure have been prepared using selectively deposited doped silicon contact layers, formed in-situ by plasma-enhanced chemical vapor deposition (PECVD). Selective deposition reduces the number of processing steps and assures the formation of low-resistance contacts. Devices fabricated with two photomasks and one p... View full abstract»

Electron cyclotron resonance (ECR) hydrogen (H) and nitrogen (N) plasma surface passivation on an AlGaAs/GaAs heterojunction bipolar transistor (HBT) is reported. As a result of the plasma processing, the base current ideality factor is improved from 2.67 to 1.96, and the maximum current gain is increased from 720 to 1000. In the low-current regime, the base current is reduced by two orders of mag... View full abstract»

Ultrathin dielectric materials that provide high capacitance values are needed for 64- and 256-Mb stacked DRAMs. It is shown that capacitance values as high as 12.3 fF/ mu m/sup 2/ can be obtained with ultrathin nitride-based layers deposited on rugged polysilicon storage electrodes. These films present the reliability and low leakage current levels required for 3.3-V applications. The nitride thi... View full abstract»

A theoretical model that explains the programming window degradation and the corresponding high- and low-state threshold voltage shifts as a function of the number of write-erase operations in FLOTOX EEPROM cells is proposed. The collapse of the programming window is quantitatively related to the oxide charge buildup in the FLOTOX tunnel region as the cycling of the memory cell is increased. The s... View full abstract»

A simple yet accurate semi-empirical analytical model for simulating the anomalous threshold voltage behavior in submicrometer MOSFETs is reported. The increase in the threshold voltage with decreasing channel length has been modeled by assuming a bias-independent, but channel-length-dependent, fixed charge at the source and drain ends. The new model requires two extra parameters in addition to th... View full abstract»

Proposed are two doping profiles of the conducting channel in bipolar-mode static induction transistors (BSITs) that improve the current handling capability. By using the results obtained from two-dimensional device simulations, it is shown that BSITs with the proposed profiles exhibit higher drain current density and DC current gain than conventional BSITs. Also discussed is the tradeoff between ... View full abstract»

The ramp recovery method for the measurement of carrier lifetime in p-i-n diodes is analyzed to show that B. Tien and C. Hu's (1988) formula tau =(t/sub A/(t/sub A/+t/sub B/))/sup 1/2/, where t/sub A/ and t/sub B/ are the two intervals for the recovery, gives a good estimate of the lifetime. The recovery can be assumed to be complete at a time t/sub 2/ at which the reverse current has reduced to 1... View full abstract»

A pseudo-MOS transistor can be activated in as-grown silicon-on-insulator (SOI) structures without any device processing by using point-contact probes. The measurement setup for in-situ operation and typical transistor characteristics are presented. Parameters are extracted which relate to minority and majority carriers, buried oxide, and the Si-SiO/sub 2/ interface.<> View full abstract»

Large-area photochemical selective dry etching has been developed for use in InGaAs/InAlAs heterojunction fabrication involving CH/sub 3/Br gas and a low-pressure mercury lamp. The etch rate of the InGaAs layer was 17 nm/min and the etch ratio of InGaAs to InAlAs was around 25 to 1. The dry recess was performed for N-InAlAs/InGaAs HEMT's on a 3-in wafer using photochemical etching. The standard de... View full abstract»

A split field-effect transistor (SFET) is proposed for measuring source and drain series resistances. This device is made by splitting a conventional thin-film transistor (TFT) from the source to the drain in such a way that the gate width of each half is a linear function of the distance from the source. The analysis shows that the intrinsic current-voltage characteristics of such a device should... View full abstract»

The performance and reliability of p-channel MOSFETs utilizing ultrathin ( approximately 62 AA) gate dielectrics grown in pure N/sub 2/O ambient are reported. Unlike (reoxidized) NH/sub 3/-nitrided oxide devices, p-MOSFETs with N/sub 2/O-grown oxides show improved performance in both linear and saturation regions compared to control devices with gate oxides grown in O/sub 2/. Because both electron... View full abstract»

A new phenomenon, the perforated emitter contact effect, is described. It arises when numerous extremely small gaps or perforations are introduced to an interfacial oxide layer in the emitter region of a bipolar transistor. Two-dimensional simulation of a novel emitter structure that incorporates a perforated interfacial layer indicates that such a layer can provide significant current gain enhanc... View full abstract»

Furnace nitridation of thermal SiO/sub 2/ in pure N/sub 2/O ambient for MOS gate dielectric application is presented. N/sub 2/O-nitrided thermal SiO/sub 2/ shows much tighter distribution in time-dependent dielectric breakdown (TDDB) characteristics than thermal oxide. MOSFETs with gate dielectric prepared by this method show improved initial performance and enhanced device reliability compared to... View full abstract»

A robust transistor configuration is described for high-frequency pulse operation of fluorescent lighting, eliminating the need for clamping diode wastage of the turn-off spike energy, and facilitating the use of ferrite yoked autotransformers to couple the transistors to the lamps. Significant improvement in light output, for the same electrical power input, is gained by utilizing autotransformer... View full abstract»

In/sub 0.52/Al/sub 0.48/As/n/sup +/-In/sub 0.53/Ga/sub 0.47/As HFETs have been fabricated with different channel thicknesses. It is shown that by reducing the channel thickness from 350 to 100 AA, the reverse gate breakdown voltage improves from 9 to 19 V. This is partially attributed to the increased effective bandgap that results from energy quantization in the channel. This bandgap enhancement ... View full abstract»

Low-resistance ohmic contacts have been fabricated on a natural IIb semiconducting diamond crystal and on undoped polycrystalline diamond films by B ion implantation and subsequent metallization with a Ti-Au bilayer metallization. A high B concentration of approximately 7*10/sup 20/ cm/sup -3/ at the surface was obtained by ion implantation, a post-implant anneal, and a subsequent chemical removal... View full abstract»

The storage times of FET-accessed GaAs dynamic RAM cells are limited to less than 1 min at room temperature by gate leakage in the access transistor. These transistor leakage mechanisms have been eliminated by designing a vertically integrated DRAM cell in which an n-p-n bipolar access transistor is merged with a p-n-p storage capacitor. Storage times of 4.5 h are obtained at room temperature, a 1... View full abstract»

For the original article see ibid., vol.11, no.9, p.373-5 (1990). The commenters give reasons for the discrepancy between measured and calculated currents for quantum barrier varactors proposed in the above-titled paper, based on the well-known intervalley transfer phenomenon in direct Al/sub x/Ga/sub 1-x/As barriers. Suggestions for improving the Q of the varactors are also included. In their rep... View full abstract»