IEEE Transactions on Computers

The automated design of multilayer printed circuit boards is of great importance in the physical design of complex electronic systems. Wire routing is a crucial step in the design process. In this paper, the single row routing problem is considered. First, we discuss the relevance of single row routing in the context of the general routing problem. Then, we show that relaxing the restriction that ... View full abstract»

In this paper, we show that the simple file allocation problem in computer science is isomorphic to the single commodity warehouse location problem in operations research. In simple file allocation, costs due to query and update accesses and storage are considered. Design requirements such as reliability, availability, and delay are not taken into account. Due to this isomorphism, many techniques ... View full abstract»

An algorithm is presented to determine locations for the storage of copies of files in store-and-forward computer communications networks. The algorithm determines storage locations which minimize the sum of network file storage costs and message transmission costs. Networks that use adaptive routing techniques are the primary focus. Feasible file locations must satisfy network performance require... View full abstract»

A new approximation model for the analysis of a finite buffer GI/G/1 system is presented. The approach consists of formulating the computer node mean waiting time from a discrete time marginal overflow customer per time slot solution of a continuous marginal overflow time per customer solution. The key to the model solution is the quantization of the distribution (fu(u)) of the difference between ... View full abstract»

An algorithm is presented to merge two subfiles of size n/2 each, stored in the left and the right halves of a linearly connected processor array, in 3n/2 route steps and log n compare-exchange steps. This algorithm is extended to merge two horizontally adjacent subfiles of size m × n/2 each, stored in an m × n mesh-connected processor array in row-major order, in m + 2n route steps and ... View full abstract»

An algorithm for the parallel solution of large sparse sets of linear equations, given their factor matrices, is developed. It is aimed at efficient practical implementation on a processor of the multiple instruction multiple data stream (MIMD) type. The software required to implement the algorithm is described. In addition, the amount of memory necessary for data retention during execution is con... View full abstract»

The paper presents a new method for designing efficient TSC checkers for m-out-of n codes. The method is based on the partitioning of the input code variables into an arbitrary number of r classes. The paper establishes the necessary design conditions that must hold among m, n and r. The checker is basically composed of an m/n to l/z subchecker concatenated with an l/z to 1/2 subchecker. A cost an... View full abstract»

A central issue in the design of multiprocessor systems is the interconnection network which provides communication paths between the processors. For large systems, high bandwidth interconnection networks will require numerous "network chips" with each chip implementing some subnetwork of the original larger network. Modularity and growth are important properties for such networks since multiproce... View full abstract»

We introduce a property of Boolean functions, called transitivity which consists of integer, polynomial, and matrix products as well as of many interesting related computational problems. We show that the area of any circuit computing a transitive function grows quadratically with the circuit's maximum data rate, expressed in bits/S. This result provides a precise analytic expression of an area-ti... View full abstract»

In this paper, a parallel-pipeline, radix-2 architecture is proposed to implement the fast polynomial transform (FPT). It is shown that such a structure can be used to efficiently compute a two-dimensional convolution of d1× d2complex number points, where d1 = 2^m-r+1and d2= 2^mfor 1 ≤ r ≤ m. View full abstract»

This paper examines the use of binary trees in the design of efficient parallel algorithms. Using binary trees, we develop efficient algorithms for several scheduling problems. The shared memory model for parallel computation is used. Our success in using binary trees for parallel computations, indicates that the binary tree is an important and useful design tool for parallel algorithms. View full abstract»

A tree representation of a combinational network is developed. An algorithm is proposed for finding the functional expression realized by the network. The tree representation has storage requirement linear with respect to the number of input-output paths in the network. It is shown that rmding the complementary function and generating network SPOOF can be performed efficiently on the tree structur... View full abstract»

By augmenting a given sequential machine M with two extra input symbols Ie1 and Ie2 and with one extra output terminal Z', a method is developed in this paper for designing an efficient checking experiment for the machine M and for its fault diagnosis to cover the types of faults which may result in an increase in the number of states of the original machine M. The method is an extension of the wo... View full abstract»

This paper presents a new class of AN codes of high efficiency capable of correcting single errors in radix-r arithmetic with the binary coded digits—BCr—system. The errors corrected within a single radix-r digit are single errors of the binary digits with weight ±wi≤ r–1,i=1,2,···, m, which are used to encode the BCr digits. The corresponding... View full abstract»