IEEE Transactions on Electron Devices

Using Shockley's diffusion/drift model we calculate the quasi-Fermi level (imref) bending in the depleted AIGaAs barrier layer of GaAs/AIGaAs MODFET's. We show that the assumption of a constant imref from the heterointerface through the barrier layer is not justified when the gate is moderately forward biased. Once the barrier-layer conduction band edge at the gate interface fails below that at th... View full abstract»

Since power densities in integrated circuits and power semiconductor devices are continuously increasing due to miniaturization of circuitry, the design of optimum heat spreaders and heat sinks for these applications requires rather sophisticated calculational methods. The chips and spreaders are usually rectangular in shape and although the problem is three-dimensional in nature, it is usually ap... View full abstract»

Fast double-Schottky-interdigitated diodes have been fabricated by evaporating Al-Schottky contacts on lowly doped n-GaAs (n=1014cm-3), These detectors have a relatively large light-sensitive area of 400 µm2. Rise and fall times are in the order of 10 ps. The external quantum efficiency is 25 percent at λ = 820 nm. The frequency response of the diodes is ... View full abstract»

GaAs MESFET ring oscillators were fabricated on a Si substrate and successfully operated. Epitaxial techniques to grow a GaAs layer on a Si substrate were investigated. The device-quality GaAs epitaxial layer was obtained by introducing a Ge layer (by ionized cluster-beam deposition) and alternating GaAs/GaAIAs layers (by MOCVD). The typical transconductance of 140 mS/mm was obtained for the FET w... View full abstract»

A LO/HI/LO resist system has been developed to produce sub-half-micrometer T-shaped cross section metal lines using e-beam lithography. The system provides T-shaped resist cavities with undercut profiles. T-shaped metal lines as narrow as 0.15 µm have been produced. GaAs MESFET's with 0.25-µm T-shaped Ti/Pt/Au gates have also been fabricated on MBE wafers using this resist technique. Mea... View full abstract»

The noise manifested by impact-ionization-generated substrate current in fine-line NMOS transistors is studied. It is found that this noise can be considerably above the shot noise level for high drain voltages. The magnitude of this noise is interpreted in terms of an avalanche gain produced by a multistep impact-ionization process involving both holes and electrons. The device structure imposes ... View full abstract»

A new Josephson multiplexer is designed and analyzed. Experimentally, the multiplexer is fabricated by standard Pb alloy technology with 5-µm line width, and its operation is successfully performed. The typical operating margin is ±16 percent for the gate current. The multiplexer is a four-way multiplexer with a 2-4 decoder consisting of functional AND gates. The functional gates are com... View full abstract»

In this work, a new formula for the impact-ionization process in silicon is derived. Compared with former descriptions, e.g., Chynoweth's law, this model offers the advantage to accurately calculate the ionization rates even in the case of nonhomogeneous electric fields. The idea of this model takes advantage of Shockley's "lucky-electron" model and the resulting formula is suited for implementati... View full abstract»

First-order analytical calculations were made for the energy-band diagrams for n-AlxGa1-xAs/p-GaAs heterojunctions for x = 0.15, 0.3, and 0.5 employing different compositional gradings and doping densities specifically for heterojunction-bipolar-transistor (HBT)applications. In the calculations most recently determined, conduction-band discontinuity ΔECof 65 p... View full abstract»

Gummel's integral charge-control relation (ICCR) IC= (const/Qp).exp (VBE/VT) is an important basis for developing self-consistent compact transistor models for the high-current region (including quasi-saturation). Such models are required for the simulation of future high-speed IC's with a high integration level. Unfortunately, the simplifying assumption... View full abstract»

A bidirection shift technique has been successfully demonstrated on a 512 × 120 cell array of a standard ac plasma panel. The key features of the bidirection shift technique are: electron transport for efficient information transfer, preset wall voltage for select-shift and timed select-erasure for automatic error clearing. The technique reduces the number Of line drivers to 2 four-phase driv... View full abstract»

A receiver circuit for the transmission of logic signals through package connectors in a Josephson computer is developed. It utilizes new circuit construction. This construction gives operation unaffected by the noise which is induced on the signal transmission paths by high-frequency and high-level ac power current at the connectors. The power current noise reduction ratio at a power frequency of... View full abstract»

Switching performance is simulated for GaAs/GaAlAs heterojunction bipolar transistors (HBT's) by combining a realistic physical device model that involves numerical solutions for carrier transport equations and Poisson's equation with our own circuit simulator that enables direct access to the device model embedded in arbitrary circuits. Based on simulated results for five-stage ring oscillators, ... View full abstract»

We develop a model for the high electron mobility transistor (HEMT) in which we include both hot-electron effects and conduction outside the quantum subband system using hydrodynamic-like transport equations. With such a model we can assess the significance of the various physical phenomena involved in the operation of the HEMT. We calculate results with a two-dimensional numerical technique for b... View full abstract»

This paper describes a compact model for bipolar transistors which includes quasi-saturation effects. The assumptions used in the formulation of this model are clearly stated and justified, and a step by step derivation of the model equations is presented. These equations model both de and charge storage effects. Parameter extraction techniques are qualitatively described and the compact model is ... View full abstract»

This paper describes the basic properties of the source coupled FET logic (SCFL) in terms of the dc characteristics, the speed and power performance, and other inherent features. Simulation results are compared to those for the direct coupled FET logic (DCFL), demonstrating that the SCFL has a wide allowable threshold voltage range, an excellent fan-out capability, a small input capacitance, a hig... View full abstract»

The specific contact resistance ρcof Ni/Au-Ge/Ni and Ni/Au-Sn/Ni layers on n-GaInAs and Ni/Au-Mg/Ni and Ni/Au-Zu/Ni on p-GaInAs are measured for different alloying temperatures and times using an extended transmission line model. Specific contact resistances of 4.10-8Ω cm2for Ni/Au-Sn/Ni on n-GaInAs (n = 1018cm-3) and 2.10-5 View full abstract»

Undoped semi-insulating GaAs crystals were grown in a low pressure LEC system using quartz and pyrolytic boron nitride (PBN) crucibles. Crystals grown in PBN crucibles are consistently semi-insulating from the seed end to the tail end. Crystals grown in quartz crucibles have lower Hall mobility. Other properties such as dislocation etch-pit of conductive material beginning from the seed end of the... View full abstract»

This paper discusses the development of high-performance gallium arsenide Schottky rectifiers for power switching applications. These diodes are shown to exhibit superior turn-on and turn-off dynamic switching characteristics when compared with silicon p-i-n rectifiers. The theoretical analysis presented in the paper indicates that the gallium arsenide Schottky power rectifier will be attractive f... View full abstract»

A novel GaAs FET structure, the shallow recessed-gate structure, has been proposed and applied to a 1-kbit static RAM. In order to decrease the source resistance Rsand gate capacitance Cg, the shallow n+implanted layer was formed between the gate and source/drain region; then the gate region was slightly recessed. This FET has a high transconductance gm,... View full abstract»

A six-mask process that yields stacked CMOS structures with the source and drain of both transistors self-aligned to a joint-gate electrode has been developed. The features that permit full self-alignment are an edge-defined silicon nitride "filament," used as an oxidation mask, and overlapping polysilicon "handles," used to form the top transistor source and drain regions. The individual NMOS and... View full abstract»

A simple formula allows an accurate dopant concentration profile to be calculated for a Gaussian buried layer with back diffusion into an epitaxial layer. The formula is valid when the drive-in diffusion is dominant, when the back diffusion is dominant, and for intermediate cases. View full abstract»

Two techniques are described which serve to minimize the problem of slow Newton convergence and, at times, divergence sometimes experienced in applying this iterative technique to the solution of nonlinear semiconductor equations. The truncated correction method limits the wide excursions in the solution parameters which can occur during the Newton iterative procedure and thereby permits fewer vol... View full abstract»