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IEEE Journal of Solid-State Circuits

Volume 25 Issue 3 • June 1990

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Displaying Results 1 - 25 of 40
  • Front cover - IEEE Journal of Solid-State Circuits

    Publication Year: 1990, Page(s): c1
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    Freely Available from IEEE
  • A new low-noise 100-MHz balanced relaxation oscillator

    Publication Year: 1990, Page(s):692 - 698
    Cited by:  Papers (19)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (592 KB)

    A novel fully balanced architecture for high-frequency, low-noise relaxation oscillators is presented. Differential operation is achieved with the use of two grounded capacitors utilizing the circuit parasitics. Bypassing of the regenerative memory function in the oscillator benefits both high-speed and low-noise operation. A detailed analysis of phase noise in relaxation oscillators is performed.... View full abstract»

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  • A high slew-rate CMOS amplifier for analog signal processing

    Publication Year: 1990, Page(s):885 - 889
    Cited by:  Papers (22)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    The performances of several types of analog VLSI circuits are limited by the setting behavior of CMOS amplifiers. An amplifier with a nonsaturated input stage which achieves a high slew-rate response is presented. The impact of this slew-rate amplifier on switched-capacitor circuits is described. Prototyping amplifier circuits were fabricated by the MOSIS service using a 2-μm scalable CMOS tech... View full abstract»

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  • Class AB CMOS amplifiers with high efficiency

    Publication Year: 1990, Page(s):684 - 691
    Cited by:  Papers (35)  |  Patents (27)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (704 KB)

    A new class AB CMOS operational-amplifier principle is presented. A transconductance amplifier based on this principle exhibits small-signal characteristics comparable to those of a conventional OTA. It has, however, a superior current efficiency and its settling time is not slew-rate limited. The new class AB principle can also be used in an output stage with a well-defined quiescent current, a r... View full abstract»

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  • An 8-b 1.3-MHz successive-approximation A/D converter

    Publication Year: 1990, Page(s):880 - 885
    Cited by:  Papers (24)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    A novel successive-approximation analog-to-digital (A/D) converter is described. It combines a string of equal-valued polysilicon resistors and a set of ratioed capacitors in a unique circuit configuration so that high sampling rate is achieved. The comparator is realized by a chopper-stabilized amplifier to reduce the effect of the offset voltages of MOS amplifiers. The converter performs an 8-b ... View full abstract»

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  • A flexible module library for custom DSP applications in a multiprocessor environment

    Publication Year: 1990, Page(s):720 - 729
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (864 KB)

    The module library for the Cathedral-II synthesis environment is discussed. The underlying architectural style of the environment is defined as a hierarchical composition of flexible and parameterizable data paths, microcoded control units, interprocessor communication protocols, and input/output interfaces. A data path is called an execution unit (EXU), which consists of three parts: an input blo... View full abstract»

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  • A 700-V interface IC for power bridge circuits

    Publication Year: 1990, Page(s):677 - 683
    Cited by:  Papers (5)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (556 KB)

    A 700-V integrated interface circuit is presented. It provides the gate drive for the high-side and the ground-side power MOS transistor in an offline half-bridge circuit. Ground separation for good intersystem electromagnetic compatibility (EMC) and a number of new provisions to alleviate control requirements on the low-power system control section are included. An electronic ballast for gas disc... View full abstract»

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  • Testing of zipper CMOS logic circuits

    Publication Year: 1990, Page(s):877 - 880
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    Zipper CMOS is a dynamic CMOS circuit technique which also provides protection against instability and charge-sharing problems; this is achieved by using a special driver circuit. A method for testing of zipper CMOS circuits is presented. The testing is done with the help of a single stuck-at-fault test set derived from the gate-level model of the circuit in which the vectors have to be properly a... View full abstract»

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  • Multilevel design and verification of hardware/software systems

    Publication Year: 1990, Page(s):714 - 719
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (616 KB)

    It is pointed out that most real systems in information technology are based on cooperating hardware and software, and the hardware is more than a single chip. System design can be viewed as a massively multidimensional optimization problem for which the solution set is only partially known. Experimental exploration of the design space is the only available approach. A number of projects carried o... View full abstract»

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  • Transistor-only frequency-selective circuits

    Publication Year: 1990, Page(s):821 - 832
    Cited by:  Papers (54)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1104 KB)

    The possibility of implementing frequency-selective circuits using only MOS transistors is considered. The advantages of such circuits are small chip area, good matching properties for individual elements, a potential for very high frequency of operation, and suitability for fabrication using standard digital VLSI processes. Disadvantages include the implementation of automatic tuning schemes that... View full abstract»

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  • A 500-nA sixth-order bandpass SC filter

    Publication Year: 1990, Page(s):669 - 676
    Cited by:  Papers (30)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (648 KB)

    A sixth-order bandpass switched-capacitor (SC) filter that requires only 500 nA of total supply current has been designed and fabricated in a 2-μm CMOS technology. The filter is part of an implantable device powered by a ±1.2-V battery; it can drive up to 30 pF of capacitive load and uses a 2-kHz sampling frequency. A substantial reduction in the power consumption has been achieved by us... View full abstract»

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  • Testing of multiple-output domino logic (MODL) CMOS circuits

    Publication Year: 1990, Page(s):800 - 805
    Cited by:  Papers (10)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB)

    Techniques for testing MODL circuits are presented. It is shown that, due to the greater observability of MODL circuits, their test sets can be considerably small than those derived for the conventional domino CMOS circuits. Tests for faults are derived from a comprehensive fault model which includes stuck-at, stuck-open, and stuck-on faults. Test sets for MODL circuits are inherently robust in th... View full abstract»

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  • A total solution for a 9600-b/s modem transmitter chip

    Publication Year: 1990, Page(s):644 - 652
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (636 KB)

    A single-chip analog transmitter (TX chip) for a V29-V32 9600-b/s modem has been implemented in a 3-μm CMOS n-well process. A high level of integration permits a low-cost, high-performance modem to be built. The TX chip is composed of analog, switched capacitor, and digital circuits. The important functions realized are the phase-point generator, the cosine roll-off low-pass filter, the modulat... View full abstract»

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  • Implementation of switch network logic in SOI

    Publication Year: 1990, Page(s):874 - 877
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    Implementation of switch network logic (SNL) in silicon-on-insulator (SOI) technology is examined. The effect of substrate connection is considered in order to examine the behavior of MOSFET as a switch. A situation that causes an extremely high leakage current through the substrate is discussed. This large current through the substrate restricts the switch-level modeling for SOI MOSFETs and hence... View full abstract»

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  • A 1.544-Mb/s CMOS line driver for a 22.8-Ω load

    Publication Year: 1990, Page(s):760 - 763
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    A CMOS line driver for high-speed data communication according to the T1 and CEPT recommendations is presented. The differential output swing is 7.2 Vpp on a load of 22.8 Ω from a single 5-V supply. A novel quiescent current control scheme is used. The driver occupies an area of 6.5 mm2 using a 2-μm p-well CMOS technology View full abstract»

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  • Analog circuit design optimization based on symbolic simulation and simulated annealing

    Publication Year: 1990, Page(s):707 - 713
    Cited by:  Papers (133)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (612 KB)

    A methodology for the automatic design optimization of analog integrated circuits is presented. A non-fixed-topology approach is realized by combining the optimization program OPTIMAN with the symbolic simulator ISAAC. After selecting a circuit topology, the user invokes ISAAC to model the circuit. ISAAC generates both exact and simplified analytic expressions, describing the circuit's behavior. T... View full abstract»

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  • Realization of a three-valued logic built-in testing structure

    Publication Year: 1990, Page(s):814 - 820
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    It is argued that the practical realization of n-valued logic (n⩾3) built-in testing circuits is not an obvious extension of the binary case. To support this claim, the implementation of a testing technique for ternary CMOS VLSI circuits is presented. A three-valued logic built-in logic block observer (BILBO) has been engineered to operate in four modes: reset, normal, scan p... View full abstract»

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  • Integrated mixed-mode digital-analog filter converters

    Publication Year: 1990, Page(s):660 - 668
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (648 KB)

    Alternative architectures have been investigated for the integrated realization of DAFICs (digital-analog filter converters), taking into account such important design parameters as capacitance spread and total capacitor area, conversion speed and resolution, and the hardware complexity of the analog and digital parts. To demonstrate the feasibility of this novel building block, an experimental pr... View full abstract»

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  • Quaternary logic circuits in 2-μm CMOS technology

    Publication Year: 1990, Page(s):790 - 799
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (744 KB)

    Novel quaternary logic circuits, designed in 2-μm CMOS technology, are presented. These include threshold detector circuits with an improved output voltage swing and a simple binary-to-quaternary encoder circuit. Based on these, the literal circuits, the quaternary-to-binary decoder, and the quaternary register are derived. A novel scheme for improving the power-delay product of pseudo-NMOS cir... View full abstract»

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  • A single-chip 5-V 2400-b/s modem

    Publication Year: 1990, Page(s):632 - 643
    Cited by:  Papers (1)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (888 KB)

    A single-chip split-band 2400-b/s modem has been implemented in a 3-μm CMOS process. A high-level of integration results in a low-cost, high-performance modem. Single-ended analog switched-capacitor circuitry and an application-specific digital signal processor (DSP) combine to perform all modem signal processing. The transmit processing is performed almost entirely in the analog domain. The re... View full abstract»

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  • Artificial neural networks using MOS analog multipliers

    Publication Year: 1990, Page(s):849 - 855
    Cited by:  Papers (58)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (628 KB)

    A neural network implementation that uses MOSFET analog multipliers to construct weighted sums is described. The scheme permits asynchronous analog operation of Hopfield-style networks with fully programmable digital weights. This approach avoids the use of components that waste chip area of require special processing. Two small chips have been fabricated and tested-one implementing a fully connec... View full abstract»

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  • A 70-MHz 32-b microprocessor with 1.0-μm BiCMOS macrocell library

    Publication Year: 1990, Page(s):770 - 777
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (664 KB)

    A custom 529 K-transistor microprocessor with a five-stage pipeline has been implemented on a 12.98-mm2 die. Employing BiCMOS macrocells, a 32-b execution unit, extensible ROM, RAM, a PLL (phase-locked loop) clock generator with bipolar drivers, and sense circuits, and a peak performance of 70 MIPS (million instructions per second) are achieved. Power consumption is 2.1 W at 40 MHz View full abstract»

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  • Ganged CMOS: trading standby power for speed

    Publication Year: 1990, Page(s):870 - 873
    Cited by:  Papers (22)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    The authors present ganged-CMOS logic (GCMOS), a technique employing CMOS inverters with their outputs shorted together, driving one or more encoding inverters. These encoding inverters, serving to quantize the nonbinary signal at the ganged node, effectively buffer it from external circuitry, thus allowing locally smaller noise margins. As demonstrated by two novel adders, GCMOS achieves higher s... View full abstract»

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  • Integrated selectivity for narrow-band FM IF systems

    Publication Year: 1990, Page(s):757 - 760
    Cited by:  Papers (13)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    An 18th-order all-pole continuous-time bandpass filter for IF (intermediate frequency) filtering purposes has been designed and integrated in a 3-μm CMOS process. Implemented using nine fully balanced, transconductor-capacitor coupled resonators, the filter features a 20-kHz bandwidth at 200-kHz center frequency and 54-dB dynamic range (IM3<-40 dB) and consumes 300 μA from a single 4-V su... View full abstract»

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  • Analysis and improvements of accurate dynamic current mirrors

    Publication Year: 1990, Page(s):699 - 706
    Cited by:  Papers (39)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (676 KB)

    The possibility of realizing highly accurate dynamic current mirrors based on dynamic analog techniques and improvements thereof is considered. These current mirrors, which memorize the input current, are insensitive to transistor mismatch, whereas for conventional current mirrors, the accuracy is limited by the achievable matching. Different current mirror structures are presented, the interfacin... View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Jan Craninckx 
Imec
Kapeldreef 75
B-3001 Leuven, Belgium 
jssc.craninckx@gmail.com