IEEE Micro

A series of experiments and analyses on five types of hypercube and grid-topology multicomputers, carried out to evaluate interprocessor communication performance, is described. The effects on the system of communication speed, message routing, interprocessor connectivity, and message-passing software/hardware protocols were studied. The experimental results clearly show the difference in interpro... View full abstract»

The implementation of a coherence protocol and the cache-memory architecture for a Clipper-based multiprocessor prototype is described. The Clipper was chosen for its high-performance features: fast clock speed, internal caches, internal dual buses, sophisticated pipelining system, and integrated execution units. Previous experience in which a common bus caused the main performance bottleneck moti... View full abstract»

An efficient simulator of Petri nets, suitable for both loosely and tightly coupled parallel systems and featuring high-execution speed, is proposed. This speed is obtained through an optimized software structure on an original hardware architecture that is based on digital signal processors of the TMS320 family. The Petri net class outlined compactly represents a wide range of processes by restri... View full abstract»