IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Recent study shows that the nonuniform thermal distribution not only has an impact on the substrate but also interconnects. Hence, three-dimensional (3-D) thermal analysis is crucial to analyze these effects. In this paper, the authors present and develop an efficient 3-D transient thermal simulator based on the alternating direction implicit (ADI) method for temperature estimation in a 3-D enviro... View full abstract»

In this paper, the authors propose an algorithm to find all the minimal signed digit (MSD) representations of a constant and present an algorithm to synthesize digital filters based on the MSD representation. The hardware complexity of a digital signal processing system is dependent on the number system used for the implementation. Although the canonical signed digit (CSD) representation is widely... View full abstract»

Dynamic logic is increasingly becoming a logic type of choice for designs requiring high speed and low area. Charge sharing is one of many problems that may cause failure in dynamic logic circuits due to their low noise immunity. The authors address the charge-sharing noise issue. Specifically, they develop an accurate but tractable model for analyzing charge sharing that avoids costly Hspice simu... View full abstract»

This paper presents a new method to discretize the equations for the physical modeling of semiconductor devices and back-end patterns. The method assembles planes in two dimensions and cubes in three dimensions and allows for adaptive meshing without the occurrence of spurious nodes due to mesh smoothing. Whereas the applications that are discussed focus on the design of microelectronic devices, t... View full abstract»

A formulation of core-based system-on-chip (SoC) test scheduling as a network transportation problem is presented. Given a set of tests, with demands for transportation of test bits (either for test stimuli or test response) and unrelated parallel test resources (e.g., test access mechanisms or built-in self-test engines), the authors determine the start times and resource mappings of all the test... View full abstract»

Electrostatic discharge (ESD) is a critical reliability concern for microchips. This paper presents a comprehensive computer-aided design tool for ESD applications. Specifically, the authors develop an improved and robust MOS model and implement such a model into the industry standard Cadence SPICE for ESD circuit simulation. The key components relevant to ESD in the MOS model are studied and the ... View full abstract»

This paper addresses the problem of layout automation of datapath cells. It presents an analytical approach to transistor placement under full custom design style and demonstrates that it can be applied to practical datapath designs. The presented approach is based on a mathematical model which employs a mixed integer linear programming technique. The placement algorithm adopts the custom design t... View full abstract»

The dynamic programmable logic array (PLA) style has become popular in designing high-performance microprocessors because of its high speed and predictable routing delay. However, like all other dynamic circuits, dynamic PLAs have suffered from the crosstalk noise problem. The main reason is that the regularity of the PLA design style causes a product line parallel to the adjacent product lines on... View full abstract»

In this paper, an efficient test pattern generation (TPG) algorithm for combinational circuits based on the Boolean satisfiability method (SAT) is presented. The authors propose a new data structure for the complete implication graph that increases the precision of implication process. Next, they examine approaches like a single-cone processing, single path-oriented propagation, and backward justi... View full abstract»

This paper introduces the concept of hierarchical cellular automata (HCA). The theory of HCA is developed over the Galois extension field GF(2(pqr..)), where each cell of the CA can store and process a symbol in the extension field GF (2(pqr..)). The hierarchical field structure of GF(2(pqr..)) is employed for design of an HCA-based test pattern generator (HCATPG). The HCATPG is ideally suited for... View full abstract»

Fault-based side-channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy-based concurrent error detection (CED) architectures can be used to thwart such attacks, they entail significant overheads (either area or performance). The authors investigate systematic approaches to low-cost low-latency CED techni... View full abstract»

As very large scale integration (VLSI) circuit speed rapidly increases, the inductive effects of interconnect lines strongly impact the signal integrity of a circuit. Since these inductive effects make the signal integrity problems much more serious as well as intricate, they become one of the critical issues in today's high-speed/high-density VLSI circuit design. In this paper, a generalized trav... View full abstract»

Current memory testing methods rely on fault models that are inadequate to accurately represent potential defects that occur in modern, often specialized, memories. To remedy this, the authors present a formal framework for modeling and testing special-purpose memories. Their approach uses three models: the transistor circuit, the event-sequence model, and finite-state machines. The methodology is... View full abstract»

Many tasks in computer-aided design (CAD), such as equivalence checking, property checking, logic synthesis, and false paths analysis, require efficient Boolean reasoning for problems derived from circuits. Traditionally, canonical representations, e.g., binary decision diagrams (BDDs), or structural satisfiability (SAT) methods, are used to solve different problem instances. Each of these techniq... View full abstract»

Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints such as area, power, or delay. Recently, automated test pattern generation (ATPG)-based design rewiring techniques for technology-dependent logic optimization have gained increasing popularity. In this paper, the authors propo... View full abstract»

The paper proposes a novel software-pipelining algorithm, Register-Sensitive Force-Directed Retiming Algorithm (RS-FDRA), suitable for optimizing compilers targeting embedded very large instruction word processors. The key difference between RS-FDRA and previous approaches is that this algorithm can handle code-size constraints along with latency and resource constraints. This capability enables t... View full abstract»