Volume 24 Issue 4 • Oct. 2001
Filter Results
-
-
Abstracts
Publication Year: 2001, Page(s):239 - 242|
PDF (37 KB)
-
Author index
Publication Year: 2001, Page(s):359 - 361|
PDF (49 KB)
-
Subject index
Publication Year: 2001, Page(s):361 - 366|
PDF (60 KB)
-
Flip chip interconnect systems using copper wire stud bump and lead free solder
Publication Year: 2001, Page(s):261 - 268
Cited by: Papers (16) | Patents (5)This research focuses on flip chip interconnect systems consisting of wire stud bumps and solder alloy interconnects. Conventional gold (Au) wire stud bumps and new copper (Cu) wire stud bumps were formed on the chip by wire stud bumping. Cu wire studs were bumped by controlling the ramp rate of ultrasonic power to eliminate the occurrence of under-pad chip cracks that tend to occur with high stre... View full abstract»
-
Application assessment of high throughput flip chip assembly for a high lead-eutectic solder cap interconnect system using no-flow underfill materials
Publication Year: 2001, Page(s):307 - 312
Cited by: Papers (4)Flip chip on board (FCOB) is one of the most quickly growing segments in advanced electronic packaging. In many cases, assembly processes are not capable of providing the high throughputs needed for integrated surface mount technology (SMT) processing (Tummala et al, 1997). A new high throughput process using no-flow underfill materials has been developed that has the potential to significantly in... View full abstract»
-
Characterization of the melting and wetting of Sn-Ag-X solders
Publication Year: 2001, Page(s):255 - 260
Cited by: Papers (14)There is tremendous interest at present with Pb-free solder assembly in the surface mount assembly industry in response to recent Japanese and European initiatives and proposed governmental restrictions regarding Pb usage and disposal. Many different solder alloys have been proposed as potential Pb-free solder replacements and the most promising of these fall into the general alloy families of tin... View full abstract»
-
Flip chip die attach development for multichip mechatronics power packages
Publication Year: 2001, Page(s):300 - 306
Cited by: Papers (11)New package innovations are needed to address the next generation system requirements of the automotive market. Enhanced system functionality from semiconductor components and overall cost reduction demands drive multichip package solutions. The use of semiconductor devices to switch, control and monitor high current loads will integrate logic and power devices on a common substrate with requireme... View full abstract»
-
Understanding the process window for printing lead-free solder pastes
Publication Year: 2001, Page(s):249 - 254
Cited by: Papers (15)Solder paste is primarily used as a bonding medium for surface mount assemblies (SMA) in the electronics industry, and is typically deposited using the stencil printing process. Stencil printing is a very important and critical stage in the reflow soldering of surface mount devices, and a high proportion of all SMA defects are related to this process. This is likely to continue with the drive towa... View full abstract»
-
Underfilling fine pitch BGAs
Publication Year: 2001, Page(s):293 - 299
Cited by: Papers (17)Fine pitch BGAs and chip scale packages have been developed as an alternative to direct flip chip attachment for high-density electronics. The larger solder sphere diameter and higher standoff of CSPs and fine pitch BGAs improve thermal cycle reliability while the larger pitch relaxes wiring congestion on the printed wiring board. Fine pitch BGAs and CSPs also allow rework to replace defective dev... View full abstract»
-
Neural network modeling with confidence bounds: a case study on the solder paste deposition process
Publication Year: 2001, Page(s):323 - 332
Cited by: Papers (15) | Patents (2)The formation of reliable solder joints in electronic assemblies is a critical issue in surface mount manufacturing. Stringent control is placed on the solder paste deposition process to minimize soldering defects and achieve high assembly yield. Time series process modeling of the solder paste quality characteristics using neural networks (NN) is a promising approach that complements traditional ... View full abstract»
-
The current status of lead-free solder alloys
Publication Year: 2001, Page(s):244 - 248
Cited by: Papers (22)The issue of lead-free soldering has gripped the electronics assembly industry as of late. What was once something that appeared to be too far away to worry about now has become a pressing reality. In order to avoid confusion, panic, and a misunderstanding of how the issue of lead-free soldering will affect the industry and individuals, it is necessary for all suppliers and assemblers to become ed... View full abstract»
-
Lead-free solder flip chip-on-laminate assembly and reliability
Publication Year: 2001, Page(s):282 - 292
Cited by: Papers (6)This paper examines the assembly process for flip chip die with SnAgCu solder bumps and the results of liquid-to-liquid thermal shock testing. The SnAgCu alloy required a thicker dip layer of flux to achieve good wetting compared to the SnPb eutectic alloy. A liquid spray flux yielded more consistent solder wetting with the SnAgCu alloy. With both fluxes, a nitrogen reflow atmosphere was necessary... View full abstract»
-
Manufacturer assessment procedure and criteria for parts selection and management
Publication Year: 2001, Page(s):351 - 358
Cited by: Papers (7)Parts selection and management is a process designed to evaluate the risks inherent in the use of an electronic part (e.g., a resistor, diode, or integrated circuit), and then facilitate informed decisions regarding its selection and future management activities. One step in the process is the assessment of the part manufacturer, which involves comparing data acquired for the manufacturer with pre... View full abstract»
-
Comparison of electroplated eutectic Bi/Sn and Pb/Sn solder bumps on various UBM systems
Publication Year: 2001, Page(s):269 - 274
Cited by: Papers (15)The effect of a reflow process and under bump metallurgy (UBM) systems on the growth of intermetallic compounds (IMC) of the 57Bi/43Sn and 37Pb/63Sn solder bump/UBM interfaces was investigated. The selected UBM systems were sputtered Al/Ti/Cu, sputtered Al/NiV/Cu, Al/electroless Ni/immersion Au, and Al/Ti/electroless Cu. An alloy electroplating method was used for the solder bumping process. The m... View full abstract»
-
Characteristics extraction of Pb free solder fillet profile for external feature inspection
Publication Year: 2001, Page(s):313 - 322
Cited by: Papers (3)First, the light intensity (luminance) distributions reflected from quad flat package (QFP) gull wing lead solder fillets were calculated by a simple geometrical model, using a modified diffusion equation. The dependence of the microscope angle θ (= incident angle of light) on the highlight distribution from specular surfaces was obtained. Luminance distributions from top to toe fillets were... View full abstract»
-
Integrated capacitors for conductive lithographic film circuits
Publication Year: 2001, Page(s):333 - 338
Cited by: Papers (5)This paper reports on fabrication of low-value embedded capacitors in conductive lithographic film (CLF) circuit boards. The CLF process is a low-cost and high speed manufacturing technique for flexible circuits and systems. We report on the construction and electrical characteristics of CLF capacitor structures printed onto flexible substrates. These components comprise a single polyester dielect... View full abstract»
-
Eutectic Sn-Ag solder bump process for ULSI flip chip technology
Publication Year: 2001, Page(s):275 - 281
Cited by: Papers (22) | Patents (15)A novel eutectic Pb-free solder bump process, which provides several advantages over conventional solder bump process schemes, has been developed. A thick plating mask can be fabricated for steep wall bumps using a nega-type resist with a thickness of more than 50 μm by single-step spin coating. This improves productivity for mass production. The two-step electroplating is performed using two s... View full abstract»
-
Part assessment guidelines and criteria for parts selection and management
Publication Year: 2001, Page(s):339 - 350
Cited by: Papers (7)Parts selection and management is a process designed to evaluate the risks inherent in the use of an electronic part (e.g., a resistor, diode, or integrated circuit), and then facilitate informed decisions regarding its selection and future management activities. One step in the process is part assessment, which evaluates a part's quality and integrity. This involves comparing data acquired for th... View full abstract»
Aims & Scope
IEEE Transactions on Electronics Packaging Manufacturing addresses design for manufacturability, cost and process modeling, process control and automation, factory analysis and improvement, information systems, statistical methods, environmentally friendly processing, and computer-integrated manufacturing for the production of electronic assemblies and products.
This Transactions ceased production in 2010. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.
Meet Our Editors
Editor-in-Chief
R. Wayne Johnson
Auburn University