IEE Proceedings - Computers and Digital Techniques

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Displaying Results 1 - 8 of 8
• Efficient synthesiser for generation of fast parallel multipliers

Publication Year: 2000, Page(s):49 - 52
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An automatic generator is developed which can synthesise fixed-point multipliers of any bit accuracy with a speed performance comparable to other recently proposed full-custom results. This synthesiser performs global optimisation for the interconnection of compression elements to minimise the delay in the partial product summation tree (PPST). Also, the final adder following the PPST is carefully... View full abstract»

• Reducing test application time by scan flip-flops sharing

Publication Year: 2000, Page(s):42 - 48
Cited by:  Papers (4)  |  Patents (1)
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The test application time is reduced while preserving the test quality or the fault coverage for circuit testing. The goal is achieved by reducing the number of scan flip-flops required for a scan-based design, and the basic procedure is to look for groups of “s-independent inputs.” The s-independent inputs in a group have the property that, when these inputs are combined together to s... View full abstract»

• In-line test of synthesised systems exploiting latency analysis

Publication Year: 2000, Page(s):33 - 41
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During normal operation, there are periods of time in which units in a digital system (adders, multipliers etc.) are inactive (i.e. are not processing any useful data). These latent periods' may be exploited to continually perform sets of unit tests, thus providing a dynamic indication of the healthiness of the system with little or no effect on its performance. The paper details an analysis tech... View full abstract»

• Optimally distributed computation in augmented networks

Publication Year: 2000, Page(s):27 - 31
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The concept is introduced of optimally distributed computation' in feedforward neural networks via regularisation of weight saliency. By constraining the relative importance of the parameters, computation can be distributed thinly and evenly throughout the network. It is proposed that this will have beneficial effects on fault-tolerance performance and generalisation ability in augmented network ... View full abstract»

• State assignment of finite-state machines

Publication Year: 2000, Page(s):15 - 22
Cited by:  Papers (2)  |  Patents (4)
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The state assignment problem of finite state machines (FSMs) is addressed. State assignment is a mapping from the set of states (symbolic names) of an FSM to the set of binary codes with the objective of minimising the area of the combinational circuit required to realise the FSM. It is one of the most important optimisation problems in the automatic synthesis of sequential circuits, since it has ... View full abstract»

• Teaching M/G/1 theory with extension to priority queues

Publication Year: 2000, Page(s):23 - 26
Cited by:  Papers (5)
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The derivation of sojourn time distribution is easily understood in M/M/1 queues in terms of numbers of service completions, using the random observer property. The same approach does not generalise directly to the M/G/1 queue because of a subtle dependence between the random variables involved, and an entirely different approach is usually taught in most courses on queueing theory. The M/M/1 appr... View full abstract»

• Asynchronous group mutual exclusion in ring networks

Publication Year: 2000, Page(s):1 - 8
Cited by:  Papers (7)
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In group mutual exclusion solutions, shared memory models and complete message passing networks have been proposed. These solutions, however, cannot be straightforwardly and efficiently converted to ring networks where each process can only communicate directly with its two neighbouring processes. As rings are also a popular network topology, the paper is focused on ring networks. An efficient and... View full abstract»

• Fault-tolerant wormhole routing algorithm for mesh networks

Publication Year: 2000, Page(s):9 - 14
Cited by:  Papers (5)
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A multicomputer system can hardly avoid having faulty components in the real world. A good fault-tolerant routing scheme should tolerate as many fault patterns as possible and, hence, reduce the number of disabled functional nodes. The authors consider disconnected unsurrounded faults, i.e. all disconnected faults discussed in the literature. In disconnected unsurrounded fault models, there is no ... View full abstract»

Aims & Scope

Published from 1994-2006, IEE Proceedings - Computers and Digital Techniques contained significant and original contributions on computers, computing and digital techniques. It contained technical papers describing research and development work in all aspects of digital system-on-chip design and the testing of electronic and embedded systems, including the development of design automation tools. It was aimed at researchers, engineers and educators in the fields of computer and digital systems design and testing.

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