2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

This paper describes a low-voltage and low-power transconductance amplifier and its application to third-order elliptic low-pass filter. The bulk-driven MOS transistor technique is used to provide low supply voltage operation and rail-to-rail input voltage common mode. The performance of the proposed filter is expressed through PSPICE simulators using TSMC 0.18 μm n-well CMOS process. Simulation r... View full abstract»

This paper proposes an area-efficient serial DAC, namely serial-differential serial DAC (SDS-DAC). To compose a differential DAC, a serial DAC with complementary switching requires four capacitors, two sample-and-hold circuits, and two averaging circuits. In this design, only four capacitors are necessary to perform the functions of D/A conversion and mismatch compensation. The chip measurement re... View full abstract»

This paper presents a new high-resolution pulse-position modulator (HR-PPM) circuit based on two different designs. The proposed high-resolution PPM is presented for time-based serial communication links. The proposed HR-PPM has been combined with a lower-resolution PPM to achieve a dual-resolution PPM (DRPPM) circuit for time-based serial link communications. An example of 2-bit 2Gbps high-resolu... View full abstract»

This paper presents a hybrid adjusted temperature compensation circuit for reducing the temperature drift of the bandgap reference. Combining first-order bandgap current, nonlinear compensation current, and temperature curvature compensation current together, a temperature insensitive reference voltage can be obtained in proposed circuit. Designed and verified in UMC 28nm CMOS technology with Cade... View full abstract»

This paper presents an 11b 80MS/s successive approximation register (SAR) analog-to-digital converter (ADC) in 65nm CMOS with a speed-enhanced control logic. The accelerated SAR logic leads to more settling time of the capacitive digital-to-analog converter (CDAC) and reduces decoupling capacitance area. A high-linearity CDAC using custom-designed unit capacitor with small interconnection parasiti... View full abstract»

Analog-to-digital converters (ADCs) using voltage-controlled oscillators (VCOs) digitize analog signals in the phase domain, requiring no analog comparators and resistor ladders. This VCO-based ADC can be implemented with only digital standard cells provided by process vendors to maximize the advantages of technology scaling and design automation. A conventional VCO-based ADC consisting of the sta... View full abstract»

This paper presents a low-voltage low-power four-quadrant analog multiplier using subthreshold MOS devices. The proposed design requires six transistors and two current sources in order to form a cross-coupling connection of four body-driven exponential cells. Circuit simulation using 0.35-μm CMOS process parameters in Cadence environment shows that the proposed circuit consumes 480 nW static powe... View full abstract»

This paper presents a 25-GS/s 4-bit flash analog-to-digital converter (ADC) designed in a 28 nm FDSOI CMOS process. A comprehensive analysis of the track-and-hold (T/H) bandwidth requirement is performed, providing design guideline for a single-core ADC targeting the leading-edge speed performance. A 1-to-2 StrongArm latch based demux comparator structure with a fat tree thermometer code-to-binary... View full abstract»

This paper presents a 12-bit 20-MS/s SAR ADC incorporating the window-switching technique. The proposed fast-binary-window DAC switching scheme can effectively remove the major capacitor-DAC transition error to improve the DAC linearity and suppress DAC switching errors to improve the SNR. To maintain a good production yield, a dual-reference capacitor-DAC is applied to have a small total capacita... View full abstract»

This paper presents a novel digitally-controlled DC offset calibration (DCOC) circuit for the chopper instrumentation amplifiers that offers better robustness, faster calibration speed, and lower average input noise than traditional integrator-based structures. Different from the traditional analog method, the proposed structure adopts digital circuit to cancel most of the offset introduced by the... View full abstract»

This paper presents a 9-bit 400-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with hybrid arranged capacitor array. High-speed operation is achieved by introducing a redundant weighting method into the hybrid arranged SAR CDAC and using a fast control logic which shorten the critical path. By using a custom-designed unit capacitor which minimizes top plate parasiti... View full abstract»

This paper presents a novel noise-shaping SAR ADC for bio-potential signal detection application. Its area and power consumption are greatly reduced compared to the conventional SAR ADC with the same effective number of bits. With the help of a proposed low power integrator, the comparator noise and quantization noise are greatly attenuated by 21dB in the band of interest. With such an aggressive ... View full abstract»

This paper presents a digital low-dropout regulator (DLDO) with bisection method (BM) tuning for fast transient response. Different from conventional DLDOs, the proposed DLDO employs adders instead of shift registers to tune binary distributed PMOS power switches. When a load-transient is detected, the BM tunes power switches within constant steps to stabilize the output voltage in a short setting... View full abstract»

A background second order compensation calibration for timing skew in time-interleaved (TI) analog-to-digital converters (ADCs) is proposed in this paper. With an autocorrelation function applied, the sign of timing skew is acquired. And then a second order compensation calibration with Lagrange interpolation is employed to minimize the timing skew. Compared to the conventional calibration model, ... View full abstract»

This paper presents a bandwidth-tracking wideband and low-jitter clock generator (CLG) circuit designed in a 55 nm CMOS technology. Based on a self-biased phase-locked loop (PLL) structure, bias currents of the charge pump (CP), the voltage-controlled oscillator (VCO) and the differential-to-singled-ended (DTS) converter are synergetically generated and are designed to be proportionally scaled in ... View full abstract»

This paper proposes an improved pseudo-resistor structure with wide operation voltage. In bio-potential signal acquisition system, pseudo-resistors are always employed to realize very large RC time constant to suppress the input electrode DC offset voltage. With simple combination of two complementary back-to-back pseudo resistors, the resistance lifting across operating voltage is reduced. Accord... View full abstract»

This paper presents a constant-power inductive-coupling transmitter for power reduction. By applying a newly proposed auxiliary driving technique, which involves connecting additional transistor in parallel with a driving transistor, we realized the constant-power characteristics of the inductive-coupling transmitter. The auxiliary driving transistor functions only at low supply voltages, thereby ... View full abstract»

This paper presents a bit error rate (BER)-modulated inductive-coupling transceiver using dynamic intermediate interference control technique for the first time. By controlling interference from the intermediate writer, BER can be modulated. SPICE simulation is performed in 65-nm CMOS. The simulation results show that the proposed approach is effective for power and cost reduction of the writer. View full abstract»