# IEEE Transactions on Circuits and Systems I: Regular Papers

## Volume 65 Issue 8 • Aug. 2018

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## Filter Results

Displaying Results 1 - 25 of 32

Publication Year: 2018, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I:Regular Papers publication information

Publication Year: 2018, Page(s): C2
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• ### A 0.49–13.3 MHz Tunable Fourth-Order LPF with Complex Poles Achieving 28.7 dBm OIP3

Publication Year: 2018, Page(s):2353 - 2364
Cited by:  Papers (3)
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A novel switched-capacitor low-pass filter architecture is presented. In the proposed scheme, a feedback path is added to a charge-rotating real-pole filter to implement complex poles. The selectivity is enhanced, and the in-band loss is reduced compared with the real-pole filter. The output thermal noise level and the tuning range are both close to those of the real-pole filter. These features ma... View full abstract»

• ### A 53 dB$\Omega~7$-GHz Inductorless Transimpedance Amplifier and a 1-THz+ GBP Limiting Amplifier in 0.13-$\mu$m CMOS

Publication Year: 2018, Page(s):2365 - 2377
Cited by:  Papers (1)
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An inductorless 10-Gb/s optical receiver including a novel transimpedance amplifier (TIA) with dual feedback loop and a limiting amplifier with third-order nested feedback is presented. The current-buffer-based TIA employs an active CherryHooper stage in the auxiliary amplifier and reuses the tail current source to achieve 10 Gb/s operation in the presence of a 1 pF photodiode input capacitance. S... View full abstract»

• ### Low-Power Single-Ended SAR ADC Using Symmetrical DAC Switching for Image Sensors With Passive CDS and PGA Technique

Publication Year: 2018, Page(s):2378 - 2388
Cited by:  Papers (3)
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An integrated, power-saving SAR analog-to-digital converter suitable for image sensor applications is presented in this paper. In comparison with previous works, the proposed, build-in passive correlated double sampling (CDS) and programmable gain amplifying (PGA) technique is superior in power, as it achieves correlated noise cancellation and signal amplification without additional OTAs. Furtherm... View full abstract»

• ### A Systematic Design Method for Direct Delta-Sigma Receivers

Publication Year: 2018, Page(s):2389 - 2402
Cited by:  Papers (1)
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Next generation receivers, such as the direct ΔΣ receiver (DDSR), shift the boundary between analog and digital closer to the antenna by merging the functionalities of different sub-blocks. In the DDSR, the analog components are used to their maximum potential as each stage participates in amplification, blocker filtering, anti-aliasing, and quantization noise shaping simultaneously, resulting in ... View full abstract»

• ### Theoretical Analysis of Circuit Non-Idealities in a Passive Spectrum Scanner Based on Periodically Time-Varying Circuit Components

Publication Year: 2018, Page(s):2403 - 2410
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Spectrum scanners based on passive, linear periodically time-varying RC circuits have been shown to be highly linear and consume low power. They rely on the Filtering by Aliasing technique to achieve sharp filtering from a continuous-time input to a discrete-time output. The presence of circuit parasitics can adversely affect scanner performance. Hence, this paper presents a theoretical analysis o... View full abstract»

• ### Optimal Design for Realizing a Grounded Fractional Order Inductor Using GIC

Publication Year: 2018, Page(s):2411 - 2421
Cited by:  Papers (3)
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This paper addresses the issue of the optimal design of a grounded fractional order inductor using a generalized impedance converter. The nonidealities of the op amps have been taken into account while formulating the approximate frequency characteristics of the fractional order inductor for both Type-I and Type-II realizations. Based on these formulations a set of design guidelines is proposed to... View full abstract»

• ### Integrated ExG, Vibration and Temperature Measurement Front-End for Wearable Sensing

Publication Year: 2018, Page(s):2422 - 2430
Cited by:  Papers (1)
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This paper presents a programmable CMOS integrated front-end ASIC targeting the acquisition of signals in biomedical applications, including rehabilitation and treadmill exercise monitoring. The analog front-end is combined with a commercial microcontroller for clock generation, signal processing, and feedback generation. The ASIC provides a unique combination of sensing interfaces, including a dc... View full abstract»

• ### A Scalable Optoelectronic Neural Probe Architecture With Self-Diagnostic Capability

Publication Year: 2018, Page(s):2431 - 2442
Cited by:  Papers (2)
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There is a growing demand for the development of new types of implantable optoelectronics to support both basic neuroscience and optogenetic treatments for neurological disorders. Target specification requirements include multi-site optical stimulation, programmable radiance profile, safe operation, and miniaturization. It is also preferable to have a simple serial interface rather than large numb... View full abstract»

• ### A 0.2 V 32-Kb 10T SRAM With 41 nW Standby Power for IoT Applications

Publication Year: 2018, Page(s):2443 - 2454
Cited by:  Papers (2)
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This paper proposes a new 10-transistor (10T) bitcell for robust operations at subthreshold voltages without any boost circuitry. Features of the proposed bitcell include: 1) differential pre-discharged bit-lines and a pair of decoupled access ports to resist disturbance; 2) footed latch for write assist; 3) spare latch-foot to fight against half-select disturbances; and 4) highly stacked pull-dow... View full abstract»

• ### Low Complexity Implementation of Unified Systolic Multipliers for NIST Pentanomials and Trinomials Over$\textit{GF}(2^{m})$

Publication Year: 2018, Page(s):2455 - 2465
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Systolic finite field multiplier over GF(2m) based on the National Institute of Standards and Technology (NIST) recommended pentanomials or trinomials can be used as a critical component in many cryptosystems. In this paper, for the first time, we propose a novel low-complexity unified (hybrid field size) systolic multiplier for NIST pentanomials and trinomials over GF(2m). W... View full abstract»

• ### Efficient Mapping of Boolean Functions to Memristor Crossbar Using MAGIC NOR Gates

Publication Year: 2018, Page(s):2466 - 2476
Cited by:  Papers (2)
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Memristor is considered as a promising circuit element which can be used in many applications. Various synthesis methods for Boolean functions have been explored in the literature using memristor-based design styles. Memristor crossbar is considered as one of the most preferred structures for implementing logic functions as well as memory. In this paper, a general synthesis flow has been proposed ... View full abstract»

• ### Faster Residue Multiplication Modulo 521-bit Mersenne Prime and an Application to ECC

Publication Year: 2018, Page(s):2477 - 2490
Cited by:  Papers (1)
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We present faster algorithms for the residue multiplication modulo 521-bit Mersenne prime on 32- and 64-bit platforms by using Toeplitz matrix-vector product. The total arithmetic cost of our proposed algorithms is less than that of existing algorithms, with algorithms for 64- and 32-bit residue multiplication giving the best timing results on our test machine. The transition from 64- to 32-bit im... View full abstract»

• ### Efficient Progressive Radiance Estimation Engine Architecture and Implementation for Progressive Photon Mapping

Publication Year: 2018, Page(s):2491 - 2502
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We propose a progressive radiance estimation engine (PREE) hardware architecture to accelerate the processing of the progressive photon mapping with satisfactory graphic quality. The presented PREE architecture consists of four progressive radiance estimation units (PREUs), approximate full task schedule-oriented hit-point update operation controller (AFTSO-HpUOC) and approximate data-independent ... View full abstract»

• ### All-Digital Blind Background Calibration Technique for Any Channel Time-Interleaved ADC

Publication Year: 2018, Page(s):2503 - 2514
Cited by:  Papers (2)
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This paper proposes a novel digital adaptive blind background calibration technique for the gain, timing skew, and offset mismatch errors in a time-interleaved analog-to-digital converter (TI-ADC). Based on the frequency-shifted basis functions generated only from the measured TI-ADC output, the three mismatch errors can be represented, extracted, and then subtracted from the TI-ADC output adaptiv... View full abstract»

• ### Low-Cost Lifting Architecture and Lossless Implementation of Daubechies-8 Wavelets

Publication Year: 2018, Page(s):2515 - 2523
Cited by:  Papers (1)
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This paper presents three lifting structures of Daubechies-8 (also known as D8) wavelet transform using efficient factorization of the polyphase matrix. All new filter coefficients are optimally mapped with integers resulting in low cost hardware implementation. We first derive the polyphase matrices using a factorization algorithm, which forms the basis of multiple lifting structures of D8. A the... View full abstract»

• ### An Area-Efficient Column-Parallel Digital Decimation Filter With Pre-BWI Topology for CMOS Image Sensor

Publication Year: 2018, Page(s):2524 - 2533
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This paper presents an area-efficient design of a column-parallel second-order digital decimation filter for a $\Sigma \Delta$ analog-to-digital converter-based CMOS image sensor. By using the proposed pre-bitwise-inversion topology having the same mathematical function, the chip area could be curtailed, where the bit-wise-in... View full abstract»

• ### Phase Transition Analysis of Dual-Mode Standing-Rotary Traveling-Wave Oscillator

Publication Year: 2018, Page(s):2534 - 2546
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In this paper, a dual-mode standing-rotary traveling-wave oscillator (S-RTWO) is analyzed. In order to force the conventional RTWO to oscillate in the standing wave mode, an ideal switch is used for shorting two differential nodes of the RTWO circuit. The closed-form equations, which describe the transitions of phases between the standing wave mode and the rotary traveling wave mode of the oscilla... View full abstract»

• ### Efficient Modeling of Crosstalk Noise on Power Distribution Networks for Contactless 3-D ICs

Publication Year: 2018, Page(s):2547 - 2558
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An efficient and frequency-dependent model describing the crosstalk noise on power distribution networks due to inductive links in contactless 3-D ICs is presented. A two-step approach is followed to model the crosstalk effect. During the first step, the mutual inductance between the power distribution network and the inductive link is analytically determined. Due to the weak dependence of mutual ... View full abstract»

• ### Device and Compact Circuit-Level Modeling of Graphene Field-Effect Transistors for RF and Microwave Applications

Publication Year: 2018, Page(s):2559 - 2570
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Graphene field-effect transistors (GFETs) are promising candidates for future nano-electronic circuitry with excellent radio frequency (RF) and microwave performance due to the ultra-high carrier mobility, large saturation velocity, and good electrical conductivity of the graphene channel. In this paper, a compact circuit-level model of GFETs is proposed for RF and microwave high-frequency applica... View full abstract»

• ### Model Reduction Using Parameterized Limited Frequency Interval Gramians for 1-D and 2-D Separable Denominator Discrete-Time Systems

Publication Year: 2018, Page(s):2571 - 2580
Cited by:  Papers (3)
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In this paper, we propose model reduction algorithms based on the frequency-domain interval Gramians for 1-D and separable denominator 2-D discrete-time systems using balanced truncation as a parameterized combination of unweighted and the limited-frequency interval Gramians. The values of free parameters are computed using a line search optimization. The proposed algorithms provide a substantial ... View full abstract»

• ### 40-nm CMOS Wideband High-IF Receiver Using a Modified Charge-Sharing Bandpass Filter to Boost Q-Factor

Publication Year: 2018, Page(s):2581 - 2591
Cited by:  Papers (1)
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A 40-nm CMOS wideband high-IF receiver is presented in this paper. The low-noise transconductance amplifier (LNTA) uses dual noise cancellation in order to improve its noise figure. The LNTA has also a folded-cascode structure to increase its output impedance and prepare for a current-mode passive mixer. This structure is merged into the output stage of the LNTA, so there is no need for extra tran... View full abstract»

• ### A Novel Transmitter Architecture for Spectrally-Precoded OFDM

Publication Year: 2018, Page(s):2592 - 2605
Cited by:  Papers (1)
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Frequency nulling spectral precoding is an approach that suppresses the out-of-band emission in orthogonal frequency division (OFDM) systems. In this paper, we discuss the transmitter architecture of the spectrally precoded OFDM systems. We design a novel precoder that matches the practical implementation of the OFDM modulator. We show that spectral precoding can relax the analog low pass filterin... View full abstract»

• ### A Low-Latency and Area-Efficient Gram–Schmidt-Based QRD Architecture for MIMO Receiver

Publication Year: 2018, Page(s):2606 - 2616
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Despite a low algorithmic complexity, Gram-Schmidt (GS) method has not been widely employed in the dedicated hardware architecture of matrix decomposition due to its expensive square-root and division operations. This paper presents a low-latency and area-efficient QR decomposition (QRD) architecture based on the modified GS method. The low complexity architecture is enabled by efficiently substit... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK