# IEEE Transactions on Very Large Scale Integration (VLSI) Systems

## Volume 26 Issue 6 • June 2018

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## Filter Results

Displaying Results 1 - 21 of 21

Publication Year: 2018, Page(s):C1 - C4
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• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Publication Year: 2018, Page(s): C2
| PDF (81 KB)
• ### Contactless Testing for Prebond Interposers

Publication Year: 2018, Page(s):1005 - 1014
| | PDF (2120 KB) | HTML

Interposers play an important role in integrating multiple dies in a staked-die product. Prebond testing of interposers is an essential process for improving production yield. However, the traditional testing mechanism via probing is not appropriate, since it could destroy the fragile interposers. To this end, we propose a contactless testing methodology for prebond interposers. The testing method... View full abstract»

• ### All-Digital Process-Variation-Calibrated Timing Generator for ATE With 1.95-ps Resolution and Maximum 1.2-GHz Test Rate

Publication Year: 2018, Page(s):1015 - 1025
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In this paper, an all-digital process-variation-calibrated high-performance timing generator for an automatic test equipment is proposed. The proposed timing generator generates process-variation-tolerant variable delays for high and wide-range testing clock frequency. In order to increase the testing clock frequency, a channel of the proposed timing generator consists of four subtiming generators... View full abstract»

• ### Reliability-Aware Test Methodology for Detecting Short-Channel Faults in On-Chip Networks

Publication Year: 2018, Page(s):1026 - 1039
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With the advent of rapidly evolving nanoelectronic systems, compact implementation of versatile and dense network-on-chips (NoCs) on a die has emerged as technology-of-choice for multicore computing. However, because of the increased density, NoCs often suffer from various types of manufacturing faults, which degrade the yield and jeopardize the reliability of the overall system. For example, shor... View full abstract»

Publication Year: 2018, Page(s):1040 - 1050
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In this paper, we propose a novel memory architecture with the capability of single-cycle row-wise/column-wise accesses. Such an architecture is highly suitable for workloads featuring spatial locality in multiple dimensions, which is a characteristic of many matrix and array operations. We describe in detail the circuit design techniques enabling the proposed architectures, as well as the viabili... View full abstract»

• ### Offset-Compensated High-Speed Sense Amplifier for STT-MRAMs

Publication Year: 2018, Page(s):1051 - 1058
Cited by:  Papers (1)
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Spin-transfer torque magnetic random access memory (STT-MRAM) has emerged as a promising candidate for next generation computing systems. However, with increasing process variation and decreasing supply voltage, a big design challenge of embedded STT-MRAMs is to guarantee negligible read disturbance and high yield. To deal with the read reliability challenge, an offset compensated, high-speed sens... View full abstract»

• ### Performance and Energy-Efficient Design of STT-RAM Last-Level Cache

Publication Year: 2018, Page(s):1059 - 1072
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Recent research has proposed having a die-stacked last-level cache (LLC) to overcome the memory wall. Lately, spin-transfer-torque random access memory (STT-RAM) caches have received attention, since they provide improved energy efficiency compared with DRAM caches. However, recently proposed STT-RAM cache architectures unnecessarily dissipate energy by fetching unneeded cache lines (CLs) into the... View full abstract»

• ### A Reliable Strong PUF Based on Switched-Capacitor Circuit

Publication Year: 2018, Page(s):1073 - 1083
Cited by:  Papers (1)
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This paper presents a highly reliable and invasiveattack-resistant switched-capacitor (SC) strong physical unclonable function (PUF), which can offer an extremely large number of challenge-response pairs. Two symmetrical capacitor arrays that are controlled by challenges are used to realize the strong ability of SC PUF. The mismatch created by the capacitor arrays in real fabrication is sampled by... View full abstract»

• ### DVFT: A Lightweight Solution for Power-Supply Noise-Based TRNG Using Dynamic Voltage Feedback Tuning System

Publication Year: 2018, Page(s):1084 - 1097
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True random number generators (TRNGs) are central to many computing applications, particularly in security domains such as cryptography. In this paper, we consider the design and implementation of a low-cost and lightweight TRNG. In the interest of being thorough, we examined six different power supplies in order to verify the noncyclostationary behavior of the voltage sources. Our novel TRNG mode... View full abstract»

• ### Stream Processing Dual-Track CGRA for Object Inference

Publication Year: 2018, Page(s):1098 - 1111
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With the development of machine learning technology, the exploration of energy-efficient and flexible architectures for object inference algorithms is of growing interest in recent years. However, not many publications concentrate on a coarsegrained reconfigurable architecture (CGRA) for object inference algorithms. This paper provides a stream processing, dual-track programming CGRA-based approac... View full abstract»

• ### A Simple Yet Efficient Accuracy-Configurable Adder Design

Publication Year: 2018, Page(s):1112 - 1125
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Approximate computing is a promising approach for low-power IC design and has recently received considerable research attention. To accommodate dynamic levels of approximation, a few accuracy-configurable adder (ACA) designs have been developed in the past. However, these designs tend to incur large area overheads as they rely on either redundant computing or complicated carry prediction. Some of ... View full abstract»

• ### A Fully Synthesized 77-dB SFDR Reprogrammable SRMC Filter Using Digital Standard Cells

Publication Year: 2018, Page(s):1126 - 1138
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This paper presents a fully synthesized 0.4-V analog biquad filter in a 0.13-μm CMOS technology using digital standard cells. In contrast to a custom-designed inverter-based amplifier in the conventional design, a new NAND-/NOR-gate-based microoperational amplifier (uOP) operating in weak inversion is proposed in this paper. Furthermore, by employing feedforward compensation for loop stability, a ... View full abstract»

• ### Clocked Hysteresis Control Scheme With Power-Law Frequency Scaling in Buck Converter to Improve Light-Load Efficiency for IoT Sensor Nodes

Publication Year: 2018, Page(s):1139 - 1150
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A clocked hysteresis control scheme with power-law frequency scaling is proposed to improve the conversion efficiency at a light load current, and it is applied to a buck converter design. By replacing a continuously on comparator used in conventional hysteresis control by a clocked comparator with power-law frequency scaling, the buck converter consumes no direct current (dc) in the comparators. ... View full abstract»

• ### A Design of Fast-Settling, Low-Power 4.19-MHz Real-Time Clock Generator With Temperature Compensation and 15-dB Noise Reduction

Publication Year: 2018, Page(s):1151 - 1158
Cited by:  Papers (1)
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This paper presents a fast-settling, low-power, lownoise real-time clock (RTC) generator for a 4.194304-MHz crystal oscillator. The fast settling reduces the startup time of the proposed RTC generator using a negative transcondutance booster and a crystal energy booster. The low power is only operated to reduce the total power consumption in the standby mode with the use of a peak-and-low detector... View full abstract»

• ### Thermal Management of Batteries Using Supercapacitor Hybrid Architecture With Idle Period Insertion Strategy

Publication Year: 2018, Page(s):1159 - 1170
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Thermal analysis and management of batteries have been an important research issue for battery-operated systems, such as electric vehicles and mobile devices. Nowadays, battery packs are designed considering heat dissipation, and external cooling devices, such as a cooling fan, are also widely used to enforce the reliability and extend the lifetime of a battery. However, this type of approaches ca... View full abstract»

• ### A 1-Gb/s 6–10-GHz, Filterless, Pulsed UWB Transmitter With Symmetrical Waveform Analysis and Generation

Publication Year: 2018, Page(s):1171 - 1182
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This paper presents a fully integrated, regulation-aware pulsed ultra wideband (UWB) transmitter (TX) for low-cost, high-data-rate applications. Waveform nonidealities have been systematically analyzed for the first time, demonstrating that envelope asymmetry may cause spectrum regulation violations. In order to generate regulation-compliant UWB pulses without costly filters, the proposed high-dat... View full abstract»

• ### Efficient Spectrum Sensing for Aeronautical LDACS Using Low-Power Correlators

Publication Year: 2018, Page(s):1183 - 1191
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Air traffic has seen tremendous growth over the past decade pushing the need for enhanced air traffic management schemes. The $L$ -band digital aeronautical communication system (LDACS) is gaining traction as a scheme of choice, and aims to exploit the capabilities of modern digital communication techniques and computing architectures. Cognitive radio-based approaches have also been proposed for L... View full abstract»

• ### A 128-Tap Highly Tunable CMOS IF Finite Impulse Response Filter for Pulsed Radar Applications

Publication Year: 2018, Page(s):1192 - 1203
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A configurable-bandwidth (BW) filter is presented in this paper for pulsed radar applications. To eliminate dispersion effects in the received waveform, a finite impulse response (FIR) topology is proposed, which has a measured standard deviation of an in-band group delay of 11 ns that is primarily dominated by the inherent, fully predictable delay introduced by the sample-and-hold. The filter ope... View full abstract»

• ### VOSsim: A Framework for Enabling Fast Voltage Overscaling Simulation for Approximate Computing Circuits

Publication Year: 2018, Page(s):1204 - 1208
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Approximate computing emerges as a new design paradigm for generating energy-efficient computing systems. Voltage overscaling (VOS) forms a very promising technique to generate approximate circuits, and its application in cooperation to other approximate techniques is proven to lead to more efficient solutions. However, the existing design tools fail to provide effective voltage-aware simulation f... View full abstract»

• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Publication Year: 2018, Page(s): C3
| PDF (48 KB)

## Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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## Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty

Department of Electrical Engineering

Duke University

Durham, NC 27708 USA

Krish@duke.edu