# IEEE Transactions on Circuits and Systems I: Regular Papers

## Volume 65 Issue 3 • March 2018

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## Filter Results

Displaying Results 1 - 25 of 33

Publication Year: 2018, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I:Regular Papers publication information

Publication Year: 2018, Page(s): C2
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• ### Guest Editorial Special Issue on the 2017 IEEE International Symposium on Circuits and Systems (ISCAS 2017)

Publication Year: 2018, Page(s):857 - 858
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• ### Analysis and Demonstration of an IIP3 Improvement Technique for Low-Power RF Low-Noise Amplifiers

Publication Year: 2018, Page(s):859 - 869
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This paper describes a linearization method to enhance the third-order distortion performance of a subthreshold common-source cascode low-noise amplifier (LNA) without extra power consumption by using passive components. An inductor between the gate of the cascode transistor and the power supply in combination with a digitally programmable capacitor between the gate and the drain of the cascode tr... View full abstract»

• ### A Self-Test on Wafer Level for a MEM Gyroscope Readout Based on $\Delta \Sigma$ Modulation

Publication Year: 2018, Page(s):870 - 880
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This paper presents the implementation of a self-test for a gyroscope readout based on electro-mechanical ΔΣ modulation. Commonly, sensor element and readout ASIC are fabricated on separate wafers. Therefore, the ability to separately characterize the sensor element and the ASIC before packaging is desirable in order to reduce unnecessary expense. For the proposed self-test, a charge integrator wi... View full abstract»

• ### A 12-b 40-MS/s Calibration-Free SAR ADC

Publication Year: 2018, Page(s):881 - 890
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This paper presents a new circuit technique named residue oversampling, which is suitable for high-resolution analog-to-digital converters (ADCs). By adopting this technique and simplifying the dynamic element matching, the impacts of capacitor mismatch and noise upon the successive-approximation register ADCs are reduced significantly without calibrations. The proof-of-concept prototype was fabri... View full abstract»

• ### Design and Analysis of 2.4 GHz $30~\mu \text{W}$ CMOS LNAs for Wearable WSN Applications

Publication Year: 2018, Page(s):891 - 903
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To meet the requirements of wearable wireless sensor networks, the power dissipation of the RF transceiver has to be drastically reduced. This paper presents two ultralow power low noise amplifiers (LNAs) with RF performance exceeding the requirement of the intended application. In the first LNA, by reusing the current several times and employing passive gm boosting, the LNA input impedance is red... View full abstract»

• ### A Sub-1ppm/°C Current-Mode CMOS Bandgap Reference With Piecewise Curvature Compensation

Publication Year: 2018, Page(s):904 - 913
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This paper presents a low temperature coefficient (TC) CMOS BGR for high-performance multi-channel analog-to-digital converter (ADC) working under wide temperature range. Besides the logarithmic compensation, both leakage and piecewise curvature compensation are implemented to extend its operating temperature range and keep its low TC. A β-compensation technique is used to cancel the PTAT and non-... View full abstract»

• ### PLL-Based Wideband Frequency Modulator: Two-Point Injection Versus Pre-Emphasis Technique

Publication Year: 2018, Page(s):914 - 924
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This paper analyzes and compares two popular methods to widen the modulation bandwidth of a phase-locked loop, i.e., the pre-emphasis and the two-point injection technique. The analysis reveals that both architectures have the same sensitivity to gain errors and nonlinearity in the loop, though, compared with the pre-emphasis, the two-point injection scheme features less sources of error and does ... View full abstract»

• ### Real-Time Depth From Focus on a Programmable Focal Plane Processor

Publication Year: 2018, Page(s):925 - 934
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Visual input can be used to recover the 3-D structure of a scene by estimating distances (depth) to the observer. Depth estimation is performed in various applications, such as robotics, autonomous driving, or surveillance. We present a low-power, compact, passive, and static imaging system that computes a semi-dense depth map in real time for a wide range of depths. This is achieved by using a fo... View full abstract»

• ### A 0.4-V 0.66-fJ/Cycle Retentive True-Single-Phase-Clock 18T Flip-Flop in 28-nm Fully-Depleted SOI CMOS

Publication Year: 2018, Page(s):935 - 945
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In this paper, we propose an 18-transistor true-single-phase-clock (TSPC) flip-flop (FF) with static data retention based on two forward-conditional feedback loops, without increasing the clock load, in comparison to the baseline TSPC architecture. The proposed FF was implemented for ultralow-voltage operation in 28-nm fully-depleted Silicon-on-Insulator (FDSOI) CMOS. The performance of the propos... View full abstract»

• ### A Generalized Approach to Implement Efficient CMOS-Based Threshold Logic Functions

Publication Year: 2018, Page(s):946 - 959
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An integer linear programming-based framework to identify the current-mode threshold logic functions is presented. The approach minimizes the transistor count and benefits from a generalized definition of threshold logic functions. It is shown that the threshold logic functions can be implemented in CMOS-based current mode logic with reduced transistor count when the input weights are not restrict... View full abstract»

• ### On Enhancing Reliability of Weak PUFs via Intelligent Post-Silicon Accelerated Aging

Publication Year: 2018, Page(s):960 - 969
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SRAM-based weak physically unclonable functions (PUFs) have shown promise regarding tamper sensitive key storage and device ID generation. Weak PUFs rely on intrinsic process variations to produce repeatable and unique start-up behavior. However, noise in the system can affect the start-up behavior and introduce errors. A number of solutions, such as fuzzy extraction and error correcting codes hav... View full abstract»

• ### Expected Value and Variance of the Indirect Time-of-Flight Measurement With Dead Time Afflicted Single-Photon Avalanche Diodes

Publication Year: 2018, Page(s):970 - 981
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Indirect time-of-flight (TOF) measurement with single-photon avalanche diodes (SPADs) is performed by counting incident photons in several time windows. Since SPADs exhibit dead time not all incident photons can be counted within a given time window. This affects the expected values and, hence, the variance of the distance measurement. For photon detection rates close to the inverse of the dead ti... View full abstract»

• ### Design of Least-Squares and Minimax Composite Filters

Publication Year: 2018, Page(s):982 - 991
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We study a class of composite FIR filters (C-filters), each is composed of a prototype filter and a shaping filter in cascade, where the shaping filter is constructed by cascading several complementary comb filters. In particular, the problems of designing C-filters that are optimal in least-squares, equiripple passband and lease-squares stopband, and minimax sense are formulated, and three algori... View full abstract»

• ### Single Underwater Image Restoration Using Adaptive Attenuation-Curve Prior

Publication Year: 2018, Page(s):992 - 1002
Cited by:  Papers (1)
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Underwater imaging is an important topic in maritime research. Due to the existence of dust-like particles in water medium, underwater images are vulnerable to the effect of low contrast and color cast. In this paper, we propose a novel underwater image restoration method based on a non-local prior, namely, adaptive attenuation-curve prior. This prior relies on the statistical distribution of pixe... View full abstract»

• ### Anomaly Detection in Moving-Camera Video Sequences Using Principal Subspace Analysis

Publication Year: 2018, Page(s):1003 - 1015
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This paper presents a family of algorithms based on sparse decompositions that detect anomalies in video sequences obtained from slow moving cameras. These algorithms start by computing the union of subspaces that best represents all the frames from a reference (anomaly free) video as a low-rank projection plus a sparse residue. Then, they perform a low-rank representation of a target (possibly an... View full abstract»

• ### Adaptive Matrix Design for Boosting Compressed Sensing

Publication Year: 2018, Page(s):1016 - 1027
Cited by:  Papers (1)
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Compressed sensing (CS) has been proposed to reduce operating cost (e.g., energy requirements) of acquisition devices by leveraging its capability of sampling and compressing an input signal at the same time. This paper aims at increasing CS performance (i.e., either achieving a better compression or allowing a higher signal reconstruction quality) and proposes two novel methods. Our first approac... View full abstract»

• ### Design of Synthetic Central Pattern Generators Producing Desired Quadruped Gaits

Publication Year: 2018, Page(s):1028 - 1039
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This paper is concerned with a method for design and analysis of specific neuronal networks, called central pattern generators (CPGs), which produce primary rhythmic patterns in animals. In particular, the paper is focused on synthetic CPGs made up of few basic elements and governing quadrupeds' gaits and gait transitions, under the control of an external drive. The method combines the principles ... View full abstract»

• ### Complex Dynamics in Arrays of Memristor Oscillators via the Flux–Charge Method

Publication Year: 2018, Page(s):1040 - 1050
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The key intent of the work is to analyze complex dynamics and synchronization phenomena in a 1-D array of N diffusively coupled memristor-based oscillatory/chaotic circuits, i.e., each uncoupled oscillator is a 3rd-order memristor-based Chua's circuit obtained by replacing the nonlinear resistor with an ideal flux-controlled memristor. It is shown that the state space R4N in the voltage-current do... View full abstract»

• ### Factoring Integers With a Brain-Inspired Computer

Publication Year: 2018, Page(s):1051 - 1062
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The bound to factor large integers is dominated by the computational effort to discover numbers that are B-smooth, i.e., integers whose largest prime factor does not exceed B. Smooth numbers are traditionally discovered by sieving a polynomial sequence, whereby the logarithmic sum of prime factors of each polynomial value is compared to a threshold. On a von Neumann architecture, this requires a l... View full abstract»

• ### An ATPG Method for Double Stuck-At Faults by Analyzing Propagation Paths of Single Faults

Publication Year: 2018, Page(s):1063 - 1074
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As fabricated circuitry becomes larger and denser, the modern industrial automatic test pattern generation techniques, which focus on the detection of single faults, become more likely to overlook multiple (simultaneous) faults. Although there are exponentially more multiple faults than single faults in any given circuit design, only a few additional test patterns are needed to cover all of the mu... View full abstract»

• ### Mono3D: Open Source Cell Library for Monolithic 3-D Integrated Circuits

Publication Year: 2018, Page(s):1075 - 1085
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Monolithic 3-D (M3-D) integrated circuits (ICs) provide vertical interconnects with comparable size to on-chip metal vias, and therefore, achieve ultra-high density device integration. This fine-grained connectivity enabled by monolithic inter-tier vias reduces the silicon area, overall wirelength, and power consumption. An open source standard cell library for design automation of large-scale tra... View full abstract»

• ### A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits

Publication Year: 2018, Page(s):1086 - 1095
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In this paper, a variation-aware simulation framework for hybrid circuits comprising MOS transistors and magnetic tunnel junction (MTJ) devices is presented. The framework is based on one-time characterization via micromagnetic multidomain simulations, overcoming the inaccuracies introduced by single-domain analysis, which most of the existing frameworks are based on. As further distinctive capabi... View full abstract»

• ### A 5 pJ/pulse at 1-Gpps Pulsed Transmitter Based on Asynchronous Logic Master–Slave PLL Synthesis

Publication Year: 2018, Page(s):1096 - 1109
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This paper presents an ultralow power asynchronous logic transmitter operating at 1 Gpps that achieves pulse synthesis using a double phase-locked loop (PLL) architecture for applications exploiting large-scale neuronal interfacing with CMOS probes. The 4 GHz center frequency OOK transmitter synthesizes 500 ps duration pulses from a 31.25 MHz crystal oscillator using a cascade of a master and a sl... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK