IEEE Transactions on Circuits and Systems I: Regular Papers

A conventional periodic LC ladder circuit forms a transmission line that has a regular band edge between a passband and a stopband. Here for the first time, we develop the theory of simple yet unconventional double ladder circuit that exhibits a special degeneracy condition referred to as a degenerate band edge (DBE). The degeneracy occurs when four independent eigenstates coalesce into a single e... View full abstract»

This paper describes a four-element multiple-input multiple-output (MIMO) transmitter (TX) system that features an analog spatial de-interleaver to simplify the baseband-input complexity and increase the spatial matching of the sub-TXs. The MIMO diversity gain and power-combining gain are jointly exploited to relax the output power of the four power amplifiers and eliminate their output matching n... View full abstract»

Two inductorless low-power differential low-noise amplifiers (LNAs) are designed for multiband wireless communication applications. Both LNAs are based on the combination of common-gate (CG) and shunt feedback topologies. In the first LNA, the cross-coupled push-pull structure with separated bias for nMOS and pMOS CG transistors is utilized to realize gm enhancement, partial noise cancellation, an... View full abstract»

A 1.5-3.3 GHz, 7 mW, all-digital delay-locked loop (ADDLL) designed in a UMC 130-nm CMOS technology is presented in this paper. The proposed ADDLL uses the modified successive approximation register to control a NAND-based coarse delay line, which enables wider operating frequency range and small intrinsic delay. The inverter-based fine delay line is controlled by an XOR-based up/down counter with... View full abstract»

An asynchronous successive approximation register analog-to-digital converter (ADC) for wideband multi-standard systems is presented. The ADC can be configured as an 80-MS/s 10-b, 40-MS/s 11-b, or 20-MS/s 12-b converter. Time-interleaved technique is applied to expand sampling bandwidth exponentially while resolution scales down. The channel mismatches are cancelled by the digital calibration tech... View full abstract»

This paper presents a low-power, area-efficient 11-b single-ended successive-approximation-register (SAR) analog-todigital converter (ADC) targeted for biomedical applications. The design features an energy-efficient switching technique with an error cancelling capacitor network. The input range is twice the reference voltage. The ADC's loading of the previous stage is reduced by using a single-en... View full abstract»

A high-resolution, high-bandwidth, and noise-scrambling, time-to-digital converter (TDC) is presented. Its architecture, which exploits harmonics in ring oscillators, provides a sample-and-hold mechanism in the form of relative phase. This storage mechanism is highly insensitive to noise and allows for oversampling between input events, therefore, can be designed for very high bandwidth. It can ac... View full abstract»

This paper presents a low noise CMOS image sensor using conventional 3T active pixel with Nwell/Psub diode as photo detector. Both fixed pattern noise (FPN) and temporal noise are suppressed by the proposed digital correlated multiple sampling (DCMS) technology. FPN and temporal noise from pixel, buffer circuit, and column-parallel ADC are analyzed in detail, and the total noise with DCMS is deriv... View full abstract»

This paper proposes an ultralow power, high precision sub bandgap voltage reference (sub-BGR) for low-voltage self-powered devices. A novel ultralow power curvature compensation circuit is proposed to improve the temperature coefficient over a wide temperature range. A switch capacitor voltage divider with improved leakage current reduction switches is used to obtain a high accuracy and a low powe... View full abstract»

A monolithic airflow detection chip is proposed for respiration rate monitoring, and it integrates MEMS sensors with their CMOS signal processing circuits into a single chip. In fact, one major issue of integrating resistive MEMS sensors with CMOS circuits is how to deal with the dc offset caused by the inherent resistance mismatches in the sensors. In this paper, an airflow detection chip with au... View full abstract»

This paper presents a reconfigurable fast Fourier transform (FFT) hardware architecture, supporting 46 different FFT sizes defined in 3GPP-LTE applications. Our proposed design concept is mainly based on combined radix-5, radix-32, and radix24 single-path delay feedback FFT design approaches. In addition, in order to elaborate our hardware design, we also develop three design... View full abstract»

This paper introduces a computationally efficient hardware architecture for reconfigurable multiple constant multiplication block, which functions according to the canonical signed digit (CSD)-based vertical and horizontal common sub-expression elimination (VHCSE) algorithm. In the proposed architecture, the CSD decoded coefficient along with 4-b common sub-expressions (CSs) in the vertical direct... View full abstract»

Ultra-low-voltage (ULV) satisfies the energy-constraint on-die acceleration of parallel processing in battery-powered Internet-of-Things applications. However, ULV brings serious leakage energy, throughput reduction, and delay variation issues. Parallel bit-serialization remarkably reduces leakage energy and enhances area efficiency; however, extremely reduced critical path aggravates delay variat... View full abstract»

The conversion from an integer scalar to a short and sparse τ-adic nonadjacent form (τNAF) is crucial for efficient elliptic curve scalar multiplication over Koblitz curves. Currently the conversion is costly both in time and area, limiting the application of Koblitz curves. In this paper, we propose improved algorithms and implementations for both the single-digit and double-digit s... View full abstract»

In the spin-transfer-torque random access memory design, the sensing scheme has become a bottleneck from the viewpoints of performance and read energy, because the required read current and time are too large to satisfy a target read yield. When the target read yield is greater than the fundamental read-yield limit determined by bit-to-bit data-cell variation, the conventional data-cell-variation-... View full abstract»

A high accuracy Mitchell-based logarithmic conversion method for integrated circuit design is presented in this paper. A novel technique named range mapping is proposed to perform the conversion with a fresh approach that compresses the range of approximation to smaller than one-third of the range of the Mitchell fraction m. After mapping, the compressed range possesses three favorable properties.... View full abstract»

An on-chip implementable algorithm for allocation of an X-ray photon imprint, called a hit, to a single pixel in the presence of charge sharing in a highly segmented pixel detector is described. Its proof-of-principle implementation is also given supported by the results of tests using a highly collimated X-ray photon beam from a synchrotron source. The algorithm handles asynchronous arrivals of X... View full abstract»

Convolutional neural network (CNN) offers significant accuracy in image detection. To implement image detection using CNN in the Internet of Things (IoT) devices, a streaming hardware accelerator is proposed. The proposed accelerator optimizes the energy efficiency by avoiding unnecessary data movement. With unique filter decomposition technique, the accelerator can support arbitrary convolution w... View full abstract»

With increasing capabilities of energy efficient systems, computational technology can be deployed, virtually everywhere. Machine learning has proven a valuable tool for extracting meaningful information from measured data and forms one of the basic building blocks of ubiquitous computing. In high-throughput applications, measurements are rapidly taken to monitor physical processes. This brings mo... View full abstract»

In this paper, a new efficient circuit level analysis is introduced considering the effect of all harmonics and multi-injection for locking and pulling phenomena in N-stage differential and single-ended ring oscillators with the RC-load. Analytical equations are derived for the locking range in both single- and multi-injection cases. At the beginning, using a nonlinear approach, the voltage amplit... View full abstract»

Motivated by the concept of circuit design in digital circuit, this paper proposes a one-dimensional (1D) nonlinear model (1D-NLM) for producing 1D discrete-time chaotic maps. Our previous works have designed four nonlinear operations of generating new chaotic maps. However, they focus only on discussing individual nonlinear operations and their properties, but fail to consider their relationship ... View full abstract»

Many secure-critical systems rely on true random number generators that must guarantee their operational functionality during its intended life. To this end, these generators are subject to intensive online testing in order to discover any flaws in their operation. The dependability of the different blocks that compose the system is crucial to guarantee the security. In this paper, we provide some... View full abstract»