IEEE Transactions on Computers

Volume 66 Issue 12 • 1 Dec. 2017

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Displaying Results 1 - 11 of 11
• Introduction to the Special Issue on Computer Arithmetic

Publication Year: 2017, Page(s):1991 - 1993
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• High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes

Publication Year: 2017, Page(s):1994 - 2004
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A parallel decimal multiplier with improved performance is proposed in this paper by exploiting the properties of three different binary coded decimal (BCD) codes, namely the redundant BCD excess-3 code (XS-3), the overloaded decimal digit set (ODDS) code and the BCD-4221/5211 code. The signed-digit radix-10 recoding is used to recode the BCD multiplier to the digit set [-5, 5] from [0, 9]. The re... View full abstract»

• Arithmetical Improvement of the Round-Off for Cryptosystems in High-Dimensional Lattices

Publication Year: 2017, Page(s):2005 - 2018
Cited by:  Papers (1)
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With Lattice-based cryptography (LBC), ciphertexts are represented as points near a lattice, and Babai's round-off algorithm allows to decrypt them when one knows the secret-key. Recently, an accelerated variant of the round-off, based on Residue Number Systems (RNSs), has been proposed. Herein, we combine this technique with the use of lattices of Optimal Hermite Normal Form (OHNF) and propose fu... View full abstract»

• Fast Modular Arithmetic on the Kalray MPPA-256 Processor for an Energy-Efficient Implementation of ECM

Publication Year: 2017, Page(s):2019 - 2030
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The Kalray MPPA-256 processor is based on a recent low-energy manycore architecture. In this article, we investigate its performance in multiprecision arithmetic for number-theoretic applications. We have developed a library for modular arithmetic that takes full advantage of the particularities of this architecture. This is in turn used in an implementation of the ECM, an algorithm for integer fa... View full abstract»

• Single Precision Logarithm and Exponential Architectures for Hard Floating-Point Enabled FPGAs

Publication Year: 2017, Page(s):2031 - 2043
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In this article we present a novel method for implementing floating point (FP) elementary functions using the new FP single precision addition and multiplication features of the Arria&#x00A0;10 and Stratix&#x00A0;10 DSP Block architecture. Our application examples are <inline-formula><tex-math notation="LaTeX">$\log (x)$</tex-math><alternatives> <inline-graphic x... View full abstract»

• Exponential Sums and Correctly-Rounded Functions

Publication Year: 2017, Page(s):2044 - 2057
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The 2008 revision of the IEEE-754 standard, which governs floating-point arithmetic, recommends that a certain set of elementary functions should be correctly rounded. Successful attempts for solving the Table Maker's Dilemma in binary64 made it possible to design CRlibm, a library which offers correctly rounded evaluation in binary64 of some functions of the usual libm. It evaluates functions usi... View full abstract»

• Exact Lookup Tables for the Evaluation of Trigonometric and Hyperbolic Functions

Publication Year: 2017, Page(s):2058 - 2071
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Elementary mathematical functions are pervasively used in many applications such as electronic calculators, computer simulations, or critical embedded systems. Their evaluation is always an approximation, which usually makes use of mathematical properties, precomputed tabulated values, and polynomial approximations. Each step generally combines error of approximation and error of evaluation on fin... View full abstract»

• Optimization of Constant Matrix Multiplication with Low Power and High Throughput

Publication Year: 2017, Page(s):2072 - 2080
Cited by:  Papers (1)
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Constant matrix multiplication (CMM), i.e., the multiplication of a constant matrix with a vector, is a common operation in digital signal processing. It is a generalization of multiple constant multiplication (MCM) where a single variable is multiplied by a constant vector. Like MCM, CMM can be reduced to additions/subtractions and bit shifts. Finding a circuit with minimal number of add/subtract... View full abstract»

• Efficient Multibyte Floating Point Data Formats Using Vectorization

Publication Year: 2017, Page(s):2081 - 2096
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We propose a scheme for reduced-precision representation of floating point data on a continuum between IEEE-754 floating point types. Our scheme enables the use of lower precision formats for a reduction in storage space requirements and data transfer volume. We describe how our scheme can be accelerated using existing hardware vector units on two general-purpose processor (GPP) microarchitectures... View full abstract»

• Hardware Division by Small Integer Constants

Publication Year: 2017, Page(s):2097 - 2110
Cited by:  Papers (1)
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This article studies the design of custom circuits for division by a small positive constant. Such circuits can be useful for specific FPGA and ASIC applications. The first problem studied is the Euclidean division of an unsigned integer by a constant, computing a quotient and remainder. Several new solutions are proposed and compared against the state-of-the-art. As the proposed solutions use sma... View full abstract»

• Correctly Rounded Arbitrary-Precision Floating-Point Summation

Publication Year: 2017, Page(s):2111 - 2124
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We present a fast algorithm together with its low-level implementation of correctly rounded arbitrary-precision floating-point summation. The arithmetic is the one used by the GNU MPFR library: radix 2; no subnormals; each variable (each input and the output) has its own precision. We also give a worst-case complexity of this algorithm and describe how the implementation is tested. View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24
10129 Torino - Italy
e-mail: pmo@computer.org