# IEEE Transactions on Circuits and Systems I: Regular Papers

## Volume 64 Issue 7 • July 2017

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## Filter Results

Displaying Results 1 - 25 of 34

Publication Year: 2017, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I:Regular Papers publication information

Publication Year: 2017, Page(s): C2
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• ### Design Methodology for Phase-Locked Loops Using Binary (Bang-Bang) Phase Detectors

Publication Year: 2017, Page(s):1637 - 1650
Cited by:  Papers (1)
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We present a linearized analysis of bang-bang phase-locked loops (PLLs) in the frequency domain that is complete and self-consistent. It enables the manual design of frequency synthesis PLLs for loop bandwidth, output phase noise and minimum jitter. Tradeoffs between various parameters of the loop become clear. The analysis is validated against measurements on four very different loops, and helps ... View full abstract»

• ### Reference Injected Phase-Locked Loops (PLL-RIs)

Publication Year: 2017, Page(s):1651 - 1660
Cited by:  Papers (1)
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In this paper, we use synchronization to reduce phase-locked loop (PLL) phase noise and improve its locking behavior with an attenuated reference signal injection (RI) into a voltage-controlled CMOS delay-line ring-type oscillator. The transient and steady-state behavior of the PLL-RI are described by a nonlinear differential equation, which is further studied by the phase-plane method. The nonlin... View full abstract»

• ### An Ultralow-Power Wake-Up Receiver Based on Direct Active RF Detection

Publication Year: 2017, Page(s):1661 - 1672
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An ultralow-power direct active RF detection wake-up receiver (WuRx) is presented. In order to reduce the power consumption and system complexity, a differential RF envelope detector is implemented in a complementary current-reuse architecture. The detector sensitivity is enhanced through an embedded matching network with signal passive amplification. A prototype receiver is fabricated in 0.18-μm ... View full abstract»

• ### A 5-GS/s 10-b 76-mW Time-Interleaved SAR ADC in 28 nm CMOS

Publication Year: 2017, Page(s):1673 - 1683
Cited by:  Papers (3)
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This paper presents a 5-GS/s 12-way 10-b time-interleaved successive approximation register (SAR) ADC for direct sampling receivers. Proper signal and clock distribution along the multiple channels are utilized to mitigate interchannel bandwidth and timing mismatches. A digitally assisted calibration is introduced to remove the interchannel offset, gain, and timing mismatch. The T-type bootstrappe... View full abstract»

• ### A 12b 180MS/s 0.068mm2With Full-Calibration-Integrated Pipelined-SAR ADC

Publication Year: 2017, Page(s):1684 - 1695
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This paper presents a 12b 180 MS/s 0.068 mm22× time-interleaved pipelined-SAR analog-to-digital converter (ADC) with gain and offset calibrations fully embedded on-chip. The proposed binary-search gain calibration (BSGC) technique corrects the inter-stage gain error caused by the open-loop residue amplifier. The BSGC, fully integrated into the second-stage SAR ADC, contributes to a comp... View full abstract»

• ### A Charge-Redistribution Phase-Domain ADC Using an IQ-Assisted Binary-Search Algorithm

Publication Year: 2017, Page(s):1696 - 1705
Cited by:  Papers (1)
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Phase-domain Analog-to-Digital Converters (Ph-ADCs) have been considered for power-efficient implementation of body-area network transceivers employing phase demodulation. Conventional implementations of the Ph-ADCs, which work based on a full-flash zero-crossing algorithm, use linear resistive/current combiners to determine the thermometer digital code of the signal phase. These architectures suf... View full abstract»

• ### A Self-Biased Current-Mode Amplifier With an Application to 10-bit Pipeline ADC

Publication Year: 2017, Page(s):1706 - 1717
Cited by:  Papers (2)
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This paper presents a self-biased current-mode amplifier (CMAMP) suitable for a switched-capacitor circuit. The CMAMP uses a subthreshold-biased transimpedance stage as a current-sensing load, and minimizes static power dissipation by passing bias current only at the input stage. The first-order system behavior with single dominant pole gives stable phase margin without complicated frequency compe... View full abstract»

• ### Black-Box Calibration for ADCs With Hard Nonlinear Errors Using a Novel INL-Based Additive Code: A Pipeline ADC Case Study

Publication Year: 2017, Page(s):1718 - 1729
Cited by:  Papers (1)
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This paper presents a digital nonlinearity calibration technique for ADCs with strong input-output discontinuities between adjacent codes, such as pipeline, algorithmic, and SAR ADCs with redundancy. In this kind of converter, the ADC transfer function often involves multivalued regions, where conventional integral-nonlinearity (INL)-based calibration methods tend to miscalibrate, negatively affec... View full abstract»

• ### Mitigation of Sampling Errors in VCO-Based ADCs

Publication Year: 2017, Page(s):1730 - 1739
Cited by:  Papers (1)
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Voltage-controlled-oscillator-based analog-to-digital converter (ADC) is a scaling-friendly architecture to build ADCs in fine-feature complimentary metal-oxide-semiconductor processes. Lending itself to an implementation with digital components, such a converter enables design automation with existing digital CAD hence reducing design and porting costs compared with a custom design flow. However,... View full abstract»

• ### 0.9-V Class-AB Miller OTA in 0.35- $\mu \text{m}$ CMOS With Threshold-Lowered Non-Tailed Differential Pair

Publication Year: 2017, Page(s):1740 - 1747
Cited by:  Papers (1)
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This paper presents a CMOS operational transconductance amplifier (OTA), suitable for sub-1-V supply applications, whose (input) common-mode voltage can be set to (VDD+ VSS)/2 thanks to two combined techniques applied to the differential pair, namely, threshold voltage lowering and elimination of the tail current generator. Both techniques are implemented through a single com... View full abstract»

• ### An Improved Describing Function With Applications for OTA-Based Circuits

Publication Year: 2017, Page(s):1748 - 1757
Cited by:  Papers (1)
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Electronic systems make extensive use of operational transconductance amplifiers (OTAs) to build filters and oscillators. Studying the effects of the saturation nonlinearity on these OTA-based circuits is difficult and often requires lengthy simulations to check the system's performance under large-signal operation. The describing function (DF) theory allows to circumvent these simulations by deri... View full abstract»

• ### Broadband Efficiency-Enhanced Mutually Coupled Harmonic Postmatching Doherty Power Amplifier

Publication Year: 2017, Page(s):1758 - 1771
Cited by:  Papers (2)
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The postmatching topology is an effective approach for broadening the bandwidth of a Doherty power amplifier (DPA). Its efficiency can be enhanced using a second-harmonic short-circuit network (SHSN), but at the expense of bandwidth. In this paper, the SHSNs with mutual coupling are proposed to achieve efficiency enhancement without sacrificing bandwidth. A broadband Doherty amplifier was designed... View full abstract»

• ### Tuning of Multiple Parameters With a BIST System

Publication Year: 2017, Page(s):1772 - 1780
Cited by:  Papers (2)
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This paper presents a low-power built-in self-test system to compensate for mismatch and variations in CMOS IC. The system is designed and compiled on a low-power field programmable analog array (FPAA) fabricated on a 350-nm CMOS process. A second-order bandpass filter is used as a device under test. A set of 12 parallel filter banks are compiled on three different FPAA chips and compensated for l... View full abstract»

• ### Parameter Optimization in Waveform Relaxation for Fractional-Order $RC$ Circuits

Publication Year: 2017, Page(s):1781 - 1790
Cited by:  Papers (2)
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The longitudinal waveform relaxation (WR) proposed by Gander and Ruehli converges faster than the classical WR method. For the former, a free parameter α is contained, which has a significant effect on the convergence rate. The optimization of this parameter is thus an important issue in practice. Here, we apply this new WR method to the fractional-order RC circuits, and optimize such a parameter ... View full abstract»

• ### A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist

Publication Year: 2017, Page(s):1791 - 1802
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This paper presents a 28-nm 256-kb 6T static random access memory operating down to near-threshold regime. The cell array is built on foundry 4-by-2 mini-array with split single-ended large signal sensing to enable an ultra-short local bit-line of 4-b length to improve variation tolerance and performance, and to reduce disturb while maintaining manufacturability. The design employs threshold power... View full abstract»

• ### Reliability Enhancement of Low-Power Sequential Circuits Using Reconfigurable Pulsed Latches

Publication Year: 2017, Page(s):1803 - 1814
Cited by:  Papers (2)
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Pulsed latches are gaining increased visibility in low-power ASIC designs. They provide an alternative sequential element with high performance and low area and power consumption, taking advantage of both latch and flip-flop features. While the circuit reliability and robustness against different process, voltage, and temperature variations are considered as critical issues with current technologi... View full abstract»

• ### Efficient FPGA Implementation of Low-Complexity Systolic Karatsuba Multiplier Over $GF(2^{m})$ Based on NIST Polynomials

Publication Year: 2017, Page(s):1815 - 1825
Cited by:  Papers (1)
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Systolic implementation of Karatsuba algorithm (KA)-based digit-serial multiplier over GF(2<sup>m</sup>) on field-programmable gate array (FPGA) platforms has many attractive features, such as efficient tradeoff in area-time complexity and high-throughput rate. But on the other side, it suffers from high register-complexity, which leads to increase in area and power consumption. In thi... View full abstract»

• ### Biparametric Wave Digital Filters

Publication Year: 2017, Page(s):1826 - 1838
Cited by:  Papers (4)
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We propose a novel class of wave digital filters (WDFs), called Biparametric WDFs (BWDFs), whose power-normalized waves are defined as having two free parameters instead of just one. We explore the advantages brought by this generalization by first deriving the scattering relations and the corresponding adaptation conditions for the most common circuit elements. We then show that the added free pa... View full abstract»

• ### A General Structure of Linear-Phase FIR Filters With Derivative Constraints

Publication Year: 2017, Page(s):1839 - 1852
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In this paper, a general structure of linear-phase finite impulse response filters, whose frequency responses satisfy given derivative constraints imposed upon an arbitrary frequency, is proposed. It is comprised of a linear combination of parallelly connected subfilters, called the cardinal filters, with weighted coefficients being the successive derivatives of the desired frequency response at t... View full abstract»

• ### Memory-Optimized Re-Gridding Architecture for Non-Uniform Fast Fourier Transform

Publication Year: 2017, Page(s):1853 - 1864
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This paper proposes a power-efficient and memory-optimized FPGA-based solution for the memory and compute-intense re-gridding process used in implementing Non-uniform Fast Fourier Transform (NuFFT) algorithm. Re-gridding refers to mapping non-equispaced sampled data onto a uniform grid using an interpolation kernel function. Re-gridding is the most time-consuming step in the entire NuFFT computati... View full abstract»

• ### Adaptive Transmit-Side Equalization for Serial Electrical Interconnects at 100 Gb/s Using Duobinary

Publication Year: 2017, Page(s):1865 - 1876
Cited by:  Papers (1)
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The ever-increasing demand for more efficient data communication calls for new, advanced techniques for high speed serial communication. Although newly developed systems are setting records, off-line determination of the optimal equalizer settings is often needed. Well-known adaptive algorithms are mainly applied for receive-side equalization. However, transmit-side equalization is desirable for i... View full abstract»

• ### Resistive Coupling-Based Waveform Relaxation Algorithm for Analysis of Interconnect Circuits

Publication Year: 2017, Page(s):1877 - 1890
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A parallel waveform relaxation (WR) algorithm is presented for transient analysis of large distributed interconnect networks. The proposed algorithm partitions interconnect circuits using a Norton interface derived from positive and negative resistors. A theoretical framework is provided to study the convergence properties of the proposed algorithm. From this discussion, a procedure to select the ... View full abstract»

• ### Cooperative Stabilization of a Class of LTI Plants With Distributed Observers

Publication Year: 2017, Page(s):1891 - 1902
Cited by:  Papers (2)
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Over the last decades, the cooperative design of complex networked systems has received an increasing attention in real-world engineering practices. Traditionally, each node in the network is assumed to obtain the same signal. However, each agent often possesses different measurement due to the observability or configuration of the systems. To solve the stabilization problem in this case, we aim t... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK